From 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 24 Sep 2009 09:55:50 +0200
Subject: ppc4xx: Convert PPC4xx UIC defines from lower case to upper case

The latest PPC4xx register cleanup patch missed the UIC defines.
This patch now changes lower case UIC defines to upper case.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/amcc/yosemite/yosemite.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

(limited to 'board/amcc/yosemite/yosemite.c')

diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 2a654fa..731d441 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -82,21 +82,21 @@ int board_early_init_f(void)
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
 	/*--------------------------------------------------------------------
 	 * Setup other serial configuration
-- 
cgit v1.1


From 95b602bab5fec2fffab07a01ea3947c70d1bacc1 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 24 Sep 2009 13:59:57 +0200
Subject: ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case

The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).

Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/amcc/yosemite/yosemite.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'board/amcc/yosemite/yosemite.c')

diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 731d441..1ec13eb 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -237,7 +237,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
 	/* go through all possible SDRAM0_TR1[RDCT] values */
 	for (i=0; i<=0x1ff; i++) {
 		/* set the current value for TR1 */
-		mtsdram(mem_tr1, (0x80800800 | i));
+		mtsdram(SDRAM0_TR1, (0x80800800 | i));
 
 		/* write values */
 		for (j=0; j<NUM_TRIES; j++) {
@@ -289,15 +289,15 @@ phys_size_t initdram(int board)
 	/*--------------------------------------------------------------------
 	 * Setup some default
 	 *------------------------------------------------------------------*/
-	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
-	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
-	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
-	mtsdram(mem_clktr, 0x40000000);	/* ?? */
-	mtsdram(mem_wddctr, 0x40000000);	/* ?? */
+	mtsdram(SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram(SDRAM0_SLIO, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
+	mtsdram(SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram(SDRAM0_CLKTR, 0x40000000);	/* ?? */
+	mtsdram(SDRAM0_WDDCTR, 0x40000000);	/* ?? */
 
 	/*clear this first, if the DDR is enabled by a debugger
 	  then you can not make changes. */
-	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */
+	mtsdram(SDRAM0_CFG0, 0x00000000);	/* Disable EEC */
 
 	/*--------------------------------------------------------------------
 	 * Setup for board-specific specific mem
@@ -305,29 +305,29 @@ phys_size_t initdram(int board)
 	/*
 	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
 	 */
-	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
-	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */
+	mtsdram(SDRAM0_B0CR, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram(SDRAM0_B1CR, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */
 
-	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
-	mtsdram(mem_rtr, 0x04080000);	/* ?? */
-	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
-	mtsdram(mem_cfg0, 0x30000000);	/* Disable EEC */
+	mtsdram(SDRAM0_TR0, 0x410a4012);	/* ?? */
+	mtsdram(SDRAM0_RTR, 0x04080000);	/* ?? */
+	mtsdram(SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	mtsdram(SDRAM0_CFG0, 0x30000000);	/* Disable EEC */
 	udelay(400);		/* Delay 200 usecs (min)            */
 
 	/*--------------------------------------------------------------------
 	 * Enable the controller, then wait for DCEN to complete
 	 *------------------------------------------------------------------*/
-	mtsdram(mem_cfg0, 0x80000000);	/* Enable */
+	mtsdram(SDRAM0_CFG0, 0x80000000);	/* Enable */
 
 	for (;;) {
-		mfsdram(mem_mcsts, reg);
+		mfsdram(SDRAM0_MCSTS, reg);
 		if (reg & 0x80000000)
 			break;
 	}
 
 	sdram_tr1_set(0x00000000, &tr1_bank1);
 	sdram_tr1_set(0x08000000, &tr1_bank2);
-	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
+	mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
 
 	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);	/* return bytes */
 }
-- 
cgit v1.1