From ea2e142843533ca593fcb5cb3e1daf1b7f5e5949 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 20:57:11 +0100 Subject: ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese --- board/amcc/sequoia/init.S | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board/amcc/sequoia/init.S') diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 5fe3af9..c7da521 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -98,7 +98,11 @@ tlbtab: #endif /* TLB-entry for DDR SDRAM (Up to 2GB) */ +#ifdef CONFIG_4xx_DCACHE + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) +#else tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#endif #ifdef CFG_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ -- cgit v1.1 From c68f59fe3ec16769f82b5fca7421983c336d3aac Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 22 Dec 2007 15:34:20 -0500 Subject: Use definitions from "asm-ppc/mmu.h" in init.S for Sequoia Signed-off-by: Larry Johnson --- board/amcc/sequoia/init.S | 50 +---------------------------------------------- 1 file changed, 1 insertion(+), 49 deletions(-) (limited to 'board/amcc/sequoia/init.S') diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index c7da521..ff6ae66 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -20,57 +20,9 @@ */ #include +#include #include -/* General */ -#define TLB_VALID 0x00000200 -#define _256M 0x10000000 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_8M 0x00000060 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - /************************************************************************** * TLB TABLE * -- cgit v1.1 From 4d332dbeb08f5863d1ea69d91a00c5499d3a87ed Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Thu, 10 Jan 2008 18:50:33 +0100 Subject: ppc4xx: Make Sequoia boot vxWorks vxWorks expects in TLB 0 a entry for the Machine Check interrupt TLB 1 a entry for the RAM TLB 2 a entry for the EBC TLB 3 a entry for the boot flash After changing the baudrate to 9600 I had no problems to boot the vxWorks image as distributed by WindRiver (Revision 2.0/1 from June 18, 2007) Signed-off-by: Niklaus Giger --- board/amcc/sequoia/init.S | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) (limited to 'board/amcc/sequoia/init.S') diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index ff6ae66..306c92c 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -39,15 +39,8 @@ tlbtab: tlbtab_start - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ -#ifndef CONFIG_NAND_SPL - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) -#else - tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) -#endif + /* vxWorks needs this as first entry for the Machine Check interrupt */ + tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for DDR SDRAM (Up to 2GB) */ #ifdef CONFIG_4xx_DCACHE @@ -56,6 +49,18 @@ tlbtab: tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) #endif + /* TLB-entry for EBC */ + tlbentry( CFG_BCSR_BASE, SZ_256M, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ +#ifndef CONFIG_NAND_SPL + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) +#else + tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) +#endif + #ifdef CFG_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) @@ -67,9 +72,6 @@ tlbtab: tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) - /* TLB-entry for EBC */ - tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - /* TLB-entry for NAND */ tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) -- cgit v1.1