From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/amcc/ocotea/config.mk | 2 +- board/amcc/ocotea/flash.c | 14 +++++++------- board/amcc/ocotea/init.S | 10 +++++----- board/amcc/ocotea/ocotea.c | 12 ++++++------ board/amcc/ocotea/ocotea.h | 10 +++++----- 5 files changed, 24 insertions(+), 24 deletions(-) (limited to 'board/amcc/ocotea') diff --git a/board/amcc/ocotea/config.mk b/board/amcc/ocotea/config.mk index 9e18335..b62e776 100644 --- a/board/amcc/ocotea/config.mk +++ b/board/amcc/ocotea/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c index 46c6946..a83f93a 100644 --- a/board/amcc/ocotea/flash.c +++ b/board/amcc/ocotea/flash.c @@ -53,9 +53,9 @@ #define FLASH_ONBD_N_VAL 2 #define FLASH_SRAM_SEL_VAL 1 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ @@ -83,8 +83,8 @@ static int write_word(flash_info_t * info, ulong dest, ulong data); unsigned long flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; + unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; unsigned char switch_status; unsigned short index = 0; int i; @@ -107,7 +107,7 @@ unsigned long flash_init(void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -131,8 +131,8 @@ unsigned long flash_init(void) } /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[i]); #ifdef CONFIG_ENV_IS_IN_FLASH (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S index d211c71..8bcfbb1 100644 --- a/board/amcc/ocotea/init.S +++ b/board/amcc/ocotea/init.S @@ -49,9 +49,9 @@ tlbtab: * routine. */ - tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X) + tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I) tlbtab_end diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 4d1d093..fe45408 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -42,7 +42,7 @@ void fpga_init (void); int board_early_init_f (void) { unsigned long mfr; - unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; + unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE; unsigned char switch_status; unsigned long cs0_base; unsigned long cs0_size; @@ -315,7 +315,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*--------------------------------------------------------------------------+ @@ -330,7 +330,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -339,12 +339,12 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h index 95ce1fd..400852a 100644 --- a/board/amcc/ocotea/ocotea.h +++ b/board/amcc/ocotea/ocotea.h @@ -22,7 +22,7 @@ */ /* Board specific FPGA stuff ... */ -#define FPGA_REG0 (CFG_FPGA_BASE + 0x00) +#define FPGA_REG0 (CONFIG_SYS_FPGA_BASE + 0x00) #define FPGA_REG0_SSCG_MASK 0x80 #define FPGA_REG0_SSCG_DISABLE 0x00 #define FPGA_REG0_SSCG_ENABLE 0x80 @@ -48,7 +48,7 @@ #define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 #define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 #define FPGA_REG0_FLASH 0x01 -#define FPGA_REG1 (CFG_FPGA_BASE + 0x01) +#define FPGA_REG1 (CONFIG_SYS_FPGA_BASE + 0x01) #define FPGA_REG1_9772_FSELFBX_MASK 0x80 #define FPGA_REG1_9772_FSELFBX_6 0x00 #define FPGA_REG1_9772_FSELFBX_10 0x80 @@ -71,7 +71,7 @@ #define FPGA_REG1_SOURCE_SSDIV1 0x05 #define FPGA_REG1_SOURCE_SSDIV2 0x06 #define FPGA_REG1_SOURCE_SSDIV4 0x07 -#define FPGA_REG2 (CFG_FPGA_BASE + 0x02) +#define FPGA_REG2 (CONFIG_SYS_FPGA_BASE + 0x02) #define FPGA_REG2_TC0 0x80 #define FPGA_REG2_TC1 0x40 #define FPGA_REG2_TC2 0x20 @@ -82,7 +82,7 @@ #define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 #define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/ #define FPGA_REG2_DEFAULT_UART1_N 0x01 -#define FPGA_REG3 (CFG_FPGA_BASE + 0x03) +#define FPGA_REG3 (CONFIG_SYS_FPGA_BASE + 0x03) #define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ #define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ #define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ @@ -108,7 +108,7 @@ #define FPGA_REG3_STAT_LED4_DISAB 0x00 #define FPGA_REG3_STAT_LED2_DISAB 0x00 #define FPGA_REG3_STAT_LED1_DISAB 0x00 -#define FPGA_REG4 (CFG_FPGA_BASE + 0x04) +#define FPGA_REG4 (CONFIG_SYS_FPGA_BASE + 0x04) #define FPGA_REG4_GPHY_MODE10 0x80 #define FPGA_REG4_GPHY_MODE100 0x40 #define FPGA_REG4_GPHY_MODE1000 0x20 -- cgit v1.1