From c440bfe6d6d92d66478a7e84402b31f48413617b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 6 Jun 2007 11:42:13 +0200 Subject: ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese --- board/amcc/acadia/Makefile | 2 +- board/amcc/acadia/acadia.c | 10 ++- board/amcc/acadia/cmd_acadia.c | 101 ++++++++++++++++++++++++++++ board/amcc/acadia/config.mk | 6 ++ board/amcc/acadia/memory.c | 11 ++- board/amcc/acadia/u-boot-nand.lds | 137 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 263 insertions(+), 4 deletions(-) create mode 100644 board/amcc/acadia/cmd_acadia.c create mode 100644 board/amcc/acadia/u-boot-nand.lds (limited to 'board/amcc/acadia') diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile index abcbf3e..ddbcb80 100644 --- a/board/amcc/acadia/Makefile +++ b/board/amcc/acadia/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cpr.o memory.o +COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o SOBJS = SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 3b63c8a..46d63e6 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -63,8 +63,14 @@ int board_early_init_f(void) acadia_gpio_init(); /* Configure 405EZ for NAND usage */ - mtsdr(sdrnand0, 0x80c00000); - mtsdr(sdrultra0, 0x8d110000); + mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); + mfsdr(sdrultra0, reg); + reg &= ~SDR_ULTRA0_CSN_MASK; + reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) | + SDR_ULTRA0_NDGPIOBP | + SDR_ULTRA0_EBCRDYEN | + SDR_ULTRA0_NFSRSTEN; + mtsdr(sdrultra0, reg); /* USB Host core needs this bit set */ mfsdr(sdrultra1, reg); diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c new file mode 100644 index 0000000..fb7ea35 --- /dev/null +++ b/board/amcc/acadia/cmd_acadia.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +static u8 boot_267_nor[] = { + 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, + 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static u8 boot_267_nand[] = { + 0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00, + 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 chip; + u8 *buf; + int cpu_freq; + + if (argc < 3) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + cpu_freq = simple_strtol(argv[1], NULL, 10); + if (cpu_freq != 267) { + printf("Unsupported cpu-frequency - only 267 supported\n"); + return 1; + } + + /* use 0x50 as I2C EEPROM address for now */ + chip = 0x50; + + if ((strcmp(argv[2], "nor") != 0) && + (strcmp(argv[2], "nand") != 0)) { + printf("Unsupported boot-device - only nor|nand support\n"); + return 1; + } + + if (strcmp(argv[2], "nand") == 0) { + switch (cpu_freq) { + case 267: + buf = boot_267_nand; + break; + default: + break; + } + } else { + switch (cpu_freq) { + case 267: + buf = boot_267_nor; + break; + default: + break; + } + } + + if (i2c_write(chip, 0, 1, buf, 16) != 0) + printf("Error writing to EEPROM at address 0x%x\n", chip); + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0) + printf("Error2 writing to EEPROM at address 0x%x\n", chip); + + printf("Done\n"); + printf("Please power-cycle the board for the changes to take effect\n"); + + return 0; +} + +U_BOOT_CMD( + bootstrap, 3, 0, do_bootstrap, + "bootstrap - program the I2C bootstrap EEPROM\n", + " - program the I2C bootstrap EEPROM\n" + ); diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk index c8566ec..af5a46c 100644 --- a/board/amcc/acadia/config.mk +++ b/board/amcc/acadia/config.mk @@ -21,6 +21,12 @@ # MA 02111-1307 USA # +# +# AMCC 405EZ Reference Platform (Acadia) board +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + ifndef TEXT_BASE TEXT_BASE = 0xFFFC0000 endif diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 5375d36..25904d3 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -39,6 +39,7 @@ void sdram_init(void) return; } +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { wr_val <<= 2; @@ -62,9 +63,12 @@ static void cram_bcr_write(u32 wr_val) return; } +#endif long int initdram(int board_type) { +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + int i; u32 val; /* 1. EBC need to program READY, CLK, ADV for ASync mode */ @@ -92,7 +96,12 @@ long int initdram(int board_type) /* Config EBC to use RDY */ mfsdr(sdrultra0, val); - mtsdr(sdrultra0, val | 0x04000000); + mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN); + + /* Wait a short while, since for NAND booting this is too fast */ + for (i=0; i<200000; i++) + ; +#endif return (CFG_MBYTES_RAM << 20); } diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds new file mode 100644 index 0000000..a5dae0e --- /dev/null +++ b/board/amcc/acadia/u-boot-nand.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From 86ba99e34194394052d24c04dc40d1263d29a26f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 19 Jun 2007 16:40:58 +0200 Subject: [ppc4xx] Change board/amcc/acadia/cpr.c to pll.c Signed-off-by: Stefan Roese --- board/amcc/acadia/cpr.c | 195 ------------------------------------------------ board/amcc/acadia/pll.c | 195 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 195 insertions(+), 195 deletions(-) delete mode 100644 board/amcc/acadia/cpr.c create mode 100644 board/amcc/acadia/pll.c (limited to 'board/amcc/acadia') diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c deleted file mode 100644 index 9dcce35..0000000 --- a/board/amcc/acadia/cpr.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* test-only: move into cpu directory!!! */ - -#if defined(PLLMR0_200_133_66) -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 200.0 | 4 (0x02)| - * | PLB | 133.3 | 6 (0x06)| - * | OPB | 66.6 | 12 (0x0C)| - * | EBC | 66.6 | 12 (0x0C)| - * | SPI | 66.6 | 12 (0x0C)| - * | UART0 | 10.0 | 40 (0x28)| - * | UART1 | 10.0 | 40 (0x28)| - * | DAC | 2.0 | 200 (0xC8)| - * | ADC | 2.0 | 200 (0xC8)| - * | PWM | 100.0 | 4 (0x04)| - * | EMAC | 25.0 | 16 (0x10)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(cprpllc, 0x0000033c); - mtcpr(cprplld, 0x0c010200); - mtcpr(cprprimad, 0x04060c0c); - mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprclkupd, 0x40000000); -} - -#elif defined(PLLMR0_266_160_80) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 266.64 | 3 | - * | PLB | 159.98 | 5 (0x05)| - * | OPB | 79.99 | 10 (0x0A)| - * | EBC | 79.99 | 10 (0x0A)| - * | SPI | 79.99 | 10 (0x0A)| - * | UART0 | 28.57 | 7 (0x07)| - * | UART1 | 28.57 | 7 (0x07)| - * | DAC | 28.57 | 7 (0xA7)| - * | ADC | 4 | 50 (0x32)| - * | PWM | 28.57 | 7 (0x07)| - * | EMAC | 4 | 50 (0x32)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(cprpllc, 0x20000238); - mtcpr(cprplld, 0x03010400); - mtcpr(cprprimad, 0x03050a0a); - mtcpr(cprperc0, 0x00000000); - mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0x07323200); - mtcpr(cprclkupd, 0x40000000); -} - -#elif defined(PLLMR0_333_166_83) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 333.33 | 2 | - * | PLB | 166.66 | 4 (0x04)| - * | OPB | 83.33 | 8 (0x08)| - * | EBC | 83.33 | 8 (0x08)| - * | SPI | 83.33 | 8 (0x08)| - * | UART0 | 16.66 | 5 (0x05)| - * | UART1 | 16.66 | 5 (0x05)| - * | DAC | ???? | 166 (0xA6)| - * | ADC | ???? | 166 (0xA6)| - * | PWM | 41.66 | 3 (0x03)| - * | EMAC | ???? | 3 (0x03)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(cprpllc, 0x0000033C); - mtcpr(cprplld, 0x0a010000); - mtcpr(cprprimad, 0x02040808); - mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xA6A60300); - mtcpr(cprclkupd, 0x40000000); -} - -#elif defined(PLLMR0_100_100_12) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------- - * | CLK | FREQ (MHz) | - * ---------------------- - * | CPU | 100.00 | - * | PLB | 100.00 | - * | OPB | 12.00 | - * | EBC | 49.00 | - * ---------------------- - */ - - /* Initialize PLL */ - mtcpr(cprpllc, 0x000003BC); - mtcpr(cprplld, 0x06060600); - mtcpr(cprprimad, 0x02020004); - mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xC8C81600); - mtcpr(cprclkupd, 0x40000000); -} -#endif /* CPU__405EZ */ - -#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk(void) -{ - unsigned long cpr_plld; - unsigned long cpr_primad; - unsigned long primad_cpudv; - unsigned long pllFbkDiv; - unsigned long freqProcessor; - - /* - * Read PLL Mode registers - */ - mfcpr(cprplld, cpr_plld); - - /* - * Read CPR_PRIMAD register - */ - mfcpr(cprprimad, cpr_primad); - - /* - * Determine CPU clock frequency - */ - primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) - primad_cpudv = 16; - - /* - * Determine FBK_DIV. - */ - pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (pllFbkDiv == 0) - pllFbkDiv = 256; - - freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; - - return (freqProcessor); -} -#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c new file mode 100644 index 0000000..9dcce35 --- /dev/null +++ b/board/amcc/acadia/pll.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* test-only: move into cpu directory!!! */ + +#if defined(PLLMR0_200_133_66) +void board_pll_init_f(void) +{ + /* + * set PLL clocks based on input sysclk is 33M + * + * ---------------------------------- + * | CLK | FREQ (MHz) | DIV RATIO | + * ---------------------------------- + * | CPU | 200.0 | 4 (0x02)| + * | PLB | 133.3 | 6 (0x06)| + * | OPB | 66.6 | 12 (0x0C)| + * | EBC | 66.6 | 12 (0x0C)| + * | SPI | 66.6 | 12 (0x0C)| + * | UART0 | 10.0 | 40 (0x28)| + * | UART1 | 10.0 | 40 (0x28)| + * | DAC | 2.0 | 200 (0xC8)| + * | ADC | 2.0 | 200 (0xC8)| + * | PWM | 100.0 | 4 (0x04)| + * | EMAC | 25.0 | 16 (0x10)| + * ----------------------------------- + */ + + /* Initialize PLL */ + mtcpr(cprpllc, 0x0000033c); + mtcpr(cprplld, 0x0c010200); + mtcpr(cprprimad, 0x04060c0c); + mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprclkupd, 0x40000000); +} + +#elif defined(PLLMR0_266_160_80) + +void board_pll_init_f(void) +{ + /* + * set PLL clocks based on input sysclk is 33M + * + * ---------------------------------- + * | CLK | FREQ (MHz) | DIV RATIO | + * ---------------------------------- + * | CPU | 266.64 | 3 | + * | PLB | 159.98 | 5 (0x05)| + * | OPB | 79.99 | 10 (0x0A)| + * | EBC | 79.99 | 10 (0x0A)| + * | SPI | 79.99 | 10 (0x0A)| + * | UART0 | 28.57 | 7 (0x07)| + * | UART1 | 28.57 | 7 (0x07)| + * | DAC | 28.57 | 7 (0xA7)| + * | ADC | 4 | 50 (0x32)| + * | PWM | 28.57 | 7 (0x07)| + * | EMAC | 4 | 50 (0x32)| + * ----------------------------------- + */ + + /* Initialize PLL */ + mtcpr(cprpllc, 0x20000238); + mtcpr(cprplld, 0x03010400); + mtcpr(cprprimad, 0x03050a0a); + mtcpr(cprperc0, 0x00000000); + mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0x07323200); + mtcpr(cprclkupd, 0x40000000); +} + +#elif defined(PLLMR0_333_166_83) + +void board_pll_init_f(void) +{ + /* + * set PLL clocks based on input sysclk is 33M + * + * ---------------------------------- + * | CLK | FREQ (MHz) | DIV RATIO | + * ---------------------------------- + * | CPU | 333.33 | 2 | + * | PLB | 166.66 | 4 (0x04)| + * | OPB | 83.33 | 8 (0x08)| + * | EBC | 83.33 | 8 (0x08)| + * | SPI | 83.33 | 8 (0x08)| + * | UART0 | 16.66 | 5 (0x05)| + * | UART1 | 16.66 | 5 (0x05)| + * | DAC | ???? | 166 (0xA6)| + * | ADC | ???? | 166 (0xA6)| + * | PWM | 41.66 | 3 (0x03)| + * | EMAC | ???? | 3 (0x03)| + * ----------------------------------- + */ + + /* Initialize PLL */ + mtcpr(cprpllc, 0x0000033C); + mtcpr(cprplld, 0x0a010000); + mtcpr(cprprimad, 0x02040808); + mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0xA6A60300); + mtcpr(cprclkupd, 0x40000000); +} + +#elif defined(PLLMR0_100_100_12) + +void board_pll_init_f(void) +{ + /* + * set PLL clocks based on input sysclk is 33M + * + * ---------------------- + * | CLK | FREQ (MHz) | + * ---------------------- + * | CPU | 100.00 | + * | PLB | 100.00 | + * | OPB | 12.00 | + * | EBC | 49.00 | + * ---------------------- + */ + + /* Initialize PLL */ + mtcpr(cprpllc, 0x000003BC); + mtcpr(cprplld, 0x06060600); + mtcpr(cprprimad, 0x02020004); + mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0xC8C81600); + mtcpr(cprclkupd, 0x40000000); +} +#endif /* CPU__405EZ */ + +#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) +/* + * Get timebase clock frequency + */ +unsigned long get_tbclk(void) +{ + unsigned long cpr_plld; + unsigned long cpr_primad; + unsigned long primad_cpudv; + unsigned long pllFbkDiv; + unsigned long freqProcessor; + + /* + * Read PLL Mode registers + */ + mfcpr(cprplld, cpr_plld); + + /* + * Read CPR_PRIMAD register + */ + mfcpr(cprprimad, cpr_primad); + + /* + * Determine CPU clock frequency + */ + primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); + if (primad_cpudv == 0) + primad_cpudv = 16; + + /* + * Determine FBK_DIV. + */ + pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); + if (pllFbkDiv == 0) + pllFbkDiv = 256; + + freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; + + return (freqProcessor); +} +#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ -- cgit v1.1 From df8a24cdd30151505cf57bbee5289e91bf53bd1b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 19 Jun 2007 16:42:31 +0200 Subject: [ppc4xx] Fix problem with NAND booting on AMCC Acadia The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese --- board/amcc/acadia/Makefile | 2 +- board/amcc/acadia/acadia.c | 2 ++ board/amcc/acadia/memory.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) (limited to 'board/amcc/acadia') diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile index ddbcb80..c56b273 100644 --- a/board/amcc/acadia/Makefile +++ b/board/amcc/acadia/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o +COBJS = $(BOARD).o cmd_acadia.o memory.o pll.o SOBJS = SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 46d63e6..0f54025 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -55,10 +55,12 @@ int board_early_init_f(void) { unsigned int reg; +#if !defined(CONFIG_NAND_U_BOOT) /* don't reinit PLL when booting via I2C bootstrap option */ mfsdr(SDR_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); +#endif acadia_gpio_init(); diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 25904d3..9346d2c 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -31,6 +31,8 @@ #include #include +extern void board_pll_init_f(void); + /* * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! */ @@ -67,6 +69,15 @@ static void cram_bcr_write(u32 wr_val) long int initdram(int board_type) { +#if defined(CONFIG_NAND_SPL) + u32 reg; + + /* don't reinit PLL when booting via I2C bootstrap option */ + mfsdr(SDR_PINSTP, reg); + if (reg != 0xf0000000) + board_pll_init_f(); +#endif + #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) int i; u32 val; -- cgit v1.1