From b5aaa03634a171d04824336b42790f3e77203bf2 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 5 Dec 2015 17:55:19 +0100
Subject: arm: socfpga: cyclone5-socdk: Remove Micrel PHY configuration

The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 board/altera/cyclone5-socdk/socfpga.c | 40 -----------------------------------
 1 file changed, 40 deletions(-)

(limited to 'board/altera/cyclone5-socdk')

diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c
index 0fbbc34..ccb1b4b 100644
--- a/board/altera/cyclone5-socdk/socfpga.c
+++ b/board/altera/cyclone5-socdk/socfpga.c
@@ -12,10 +12,6 @@
 #include <usb/dwc2_udc.h>
 #include <usb_mass_storage.h>
 
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void s_init(void) {}
@@ -31,42 +27,6 @@ int board_init(void)
 	return 0;
 }
 
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					 0xf0f0);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
 	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
-- 
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