From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/ads5121/ads5121.c | 136 ++++++++++++++++++++++---------------------- board/ads5121/ads5121_diu.c | 4 +- board/ads5121/pci.c | 44 +++++++------- 3 files changed, 92 insertions(+), 92 deletions(-) (limited to 'board/ads5121') diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index deaa292..0610928 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -53,16 +53,16 @@ long int fixed_sdram(void); int board_early_init_f (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 lpcaw; /* * Initialize Local Window for the CPLD registers access (CS2 selects * the CPLD chip) */ - im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) | - CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE); - im->lpc.cs_cfg[2] = CFG_CS2_CFG; + im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) | + CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE); + im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG; /* * According to MPC5121e RM, configuring local access windows should @@ -80,21 +80,21 @@ int board_early_init_f (void) */ #ifdef CONFIG_ADS5121_REV2 - *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; + *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1; #else - if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) { - *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; + if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) { + *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1; } else { /* running from Backup flash */ - *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32; + *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32; } #endif /* * Configure Flash Speed */ - *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG; + *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG; if (SVR_MJREV (im->sysconf.spridr) >= 2) { - *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING; + *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING; } /* * Enable clocks @@ -120,8 +120,8 @@ phys_size_t initdram (int board_type) */ long int fixed_sdram (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2 (msize); u32 i; @@ -129,7 +129,7 @@ long int fixed_sdram (void) im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR; /* Initialize DDR Local Window */ - im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000; + im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000; im->sysconf.ddrlaw.ar = msize_log2 - 1; /* @@ -141,68 +141,68 @@ long int fixed_sdram (void) __asm__ __volatile__ ("isync"); /* Enable DDR */ - im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN; + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN; /* Initialize DDR Priority Manager */ - im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1; - im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2; - im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG; - im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU; - im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML; - im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU; - im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML; - im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU; - im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML; - im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU; - im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML; - im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU; - im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML; - im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU; - im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL; - im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU; - im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL; - im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU; - im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL; - im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU; - im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL; - im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU; - im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL; + im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1; + im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2; + im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG; + im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU; + im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML; + im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU; + im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML; + im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU; + im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML; + im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU; + im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML; + im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU; + im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML; + im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU; + im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL; + im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU; + im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL; + im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU; + im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL; + im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU; + im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL; + im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU; + im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL; /* Initialize MDDRC */ - im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG; - im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0; - im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1; - im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2; + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG; + im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1; + im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2; /* Initialize DDR */ for (i = 0; i < 10; i++) - im->mddrc.ddr_command = CFG_MICRON_NOP; - - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_RFSH; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_RFSH; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_EM2; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_EM2; - im->mddrc.ddr_command = CFG_MICRON_EM3; - im->mddrc.ddr_command = CFG_MICRON_EN_DLL; - im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_RFSH; - im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT; - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + + im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; /* Start MDDRC */ - im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN; - im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN; + im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN; + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN; return msize; } @@ -292,8 +292,8 @@ static iopin_t ioregs_init[] = { int checkboard (void) { - ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); - uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); + ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); + uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", brd_rev, cpld_rev); diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c index 26628d3..11450aa 100644 --- a/board/ads5121/ads5121_diu.c +++ b/board/ads5121/ads5121_diu.c @@ -43,7 +43,7 @@ static int xres, yres; void diu_set_pixel_clock(unsigned int pixclock) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile clk512x_t *clk = &immap->clk; volatile unsigned int *clkdvdr = &clk->scfr[0]; unsigned long speed_ccb, temp, pixval; @@ -100,7 +100,7 @@ int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp, } U_BOOT_CMD( - diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp, + diufb, CONFIG_SYS_MAXARGS, 1, ads5121diu_init_show_bmp, "diufb init | addr - Init or Display BMP file\n", "init\n - initialize DIU\n" "addr\n - display bmp at address 'addr'\n" diff --git a/board/ads5121/pci.c b/board/ads5121/pci.c index a338604..b747e81 100644 --- a/board/ads5121/pci.c +++ b/board/ads5121/pci.c @@ -33,8 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; /* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE static struct pci_controller pci_hose; @@ -46,7 +46,7 @@ static struct pci_controller pci_hose; void pci_init_board(void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile law512x_t *pci_law; volatile pot512x_t *pci_pot; volatile pcictrl512x_t *pci_ctrl; @@ -87,10 +87,10 @@ pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; /* @@ -98,18 +98,18 @@ pci_init_board(void) */ /* PCI mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M; /* PCI IO space */ - pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; /* PCI mmio - non-prefetch mem space */ - pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; /* @@ -129,23 +129,23 @@ pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, - CFG_PCI_MEM_BASE, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, + CONFIG_SYS_PCI_MEM_BASE, + CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_PHYS, - CFG_PCI_MMIO_SIZE, + CONFIG_SYS_PCI_MMIO_BASE, + CONFIG_SYS_PCI_MMIO_PHYS, + CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, - CFG_PCI_IO_BASE, - CFG_PCI_IO_PHYS, - CFG_PCI_IO_SIZE, + CONFIG_SYS_PCI_IO_BASE, + CONFIG_SYS_PCI_IO_PHYS, + CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* System memory space */ @@ -158,8 +158,8 @@ pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMR + 0x8300), - (CFG_IMMR + 0x8304)); + (CONFIG_SYS_IMMR + 0x8300), + (CONFIG_SYS_IMMR + 0x8304)); pci_register_hose(hose); -- cgit v1.1