From 2290fe06421720d1c54523a9acf1052181bc6e87 Mon Sep 17 00:00:00 2001 From: Hannes Schmelzer Date: Wed, 22 Jun 2016 12:36:13 +0200 Subject: board/BuR: rename tseries board to brppt1 Rename B&R tseries board to brppt1 Signed-off-by: Hannes Schmelzer Reviewed-by: Tom Rini --- board/BuR/brppt1/Kconfig | 15 +++ board/BuR/brppt1/MAINTAINERS | 8 ++ board/BuR/brppt1/Makefile | 14 +++ board/BuR/brppt1/board.c | 174 +++++++++++++++++++++++++++++ board/BuR/brppt1/mux.c | 254 ++++++++++++++++++++++++++++++++++++++++++ board/BuR/tseries/Kconfig | 15 --- board/BuR/tseries/MAINTAINERS | 8 -- board/BuR/tseries/Makefile | 14 --- board/BuR/tseries/board.c | 174 ----------------------------- board/BuR/tseries/mux.c | 254 ------------------------------------------ 10 files changed, 465 insertions(+), 465 deletions(-) create mode 100644 board/BuR/brppt1/Kconfig create mode 100644 board/BuR/brppt1/MAINTAINERS create mode 100644 board/BuR/brppt1/Makefile create mode 100644 board/BuR/brppt1/board.c create mode 100644 board/BuR/brppt1/mux.c delete mode 100644 board/BuR/tseries/Kconfig delete mode 100644 board/BuR/tseries/MAINTAINERS delete mode 100644 board/BuR/tseries/Makefile delete mode 100644 board/BuR/tseries/board.c delete mode 100644 board/BuR/tseries/mux.c (limited to 'board/BuR') diff --git a/board/BuR/brppt1/Kconfig b/board/BuR/brppt1/Kconfig new file mode 100644 index 0000000..e006c80 --- /dev/null +++ b/board/BuR/brppt1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BRPPT1 + +config SYS_BOARD + default "brppt1" + +config SYS_VENDOR + default "BuR" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "brppt1" + +endif diff --git a/board/BuR/brppt1/MAINTAINERS b/board/BuR/brppt1/MAINTAINERS new file mode 100644 index 0000000..9eddab4 --- /dev/null +++ b/board/BuR/brppt1/MAINTAINERS @@ -0,0 +1,8 @@ +BRPPT1 BOARD +M: Hannes Schmelzer +S: Maintained +F: board/BuR/brppt1/ +F: include/configs/brppt1.h +F: configs/brppt1_mmc_defconfig +F: configs/brppt1_nand_defconfig +F: configs/brppt1_spi_defconfig diff --git a/board/BuR/brppt1/Makefile b/board/BuR/brppt1/Makefile new file mode 100644 index 0000000..43945d2 --- /dev/null +++ b/board/BuR/brppt1/Makefile @@ -0,0 +1,14 @@ +# +# Makefile +# +# Copyright (C) 2013 Hannes Schmelzer +# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y := mux.o +endif +obj-y += ../common/common.o +obj-y += board.o diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c new file mode 100644 index 0000000..a227221 --- /dev/null +++ b/board/BuR/brppt1/board.c @@ -0,0 +1,174 @@ +/* + * board.c + * + * Board functions for B&R BRPPT1 + * + * Copyright (C) 2013 Hannes Schmelzer + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/bur_common.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* --------------------------------------------------------------------------*/ +/* -- defines for GPIO -- */ +#define REPSWITCH (0+20) /* GPIO0_20 */ + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +/* + * called from spl_nand.c + * return 0 for loading linux, return 1 for loading u-boot + */ +int spl_start_uboot(void) +{ + if (0 == gpio_get_value(REPSWITCH)) { + mdelay(1000); + printf("SPL: entering u-boot instead kernel image.\n"); + return 1; + } + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ + +#define OSC (V_OSCK/1000000) +static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; + /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/ + struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; + + /* + * in TRM they write a reset value of 1 (=CLK_M_OSC) for the + * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set + * the source of timer6 clk to CLK_M_OSC + */ + writel(0x01, &cmdpll->clktimer6clk); + + /* enable additional clocks of modules which are accessed later */ + u32 *const clk_domains[] = { + &cmper->lcdcclkstctrl, + 0 + }; + + u32 *const clk_modules_tsspecific[] = { + &cmper->lcdclkctrl, + &cmper->timer5clkctrl, + &cmper->timer6clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_tsspecific, 1); + + /* setup LCD-Pixel Clock */ + writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */ + + /* setup I2C */ + enable_i2c_pin_mux(); + i2c_set_bus_num(0); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + pmicsetup(0); + + gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */ + gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */ +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ + +/* Basic board specific setup. Pinmux has been handled already. */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#ifdef CONFIG_NAND + gpmc_init(); +#endif + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + if (0 == gpio_get_value(REPSWITCH)) { + lcd_position_cursor(1, 8); + lcd_puts( + "switching to network-console ... "); + setenv("bootcmd", "run netconsole"); + } + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/brppt1/mux.c b/board/BuR/brppt1/mux.c new file mode 100644 index 0000000..ab3788f --- /dev/null +++ b/board/BuR/brppt1/mux.c @@ -0,0 +1,254 @@ +/* + * mux.c + * + * Pinmux Setting for B&R BRPPT1 Board(s) + * + * Copyright (C) 2013 Hannes Schmelzer + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_RTS */ + {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)}, + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; +static struct module_pin_mux uart1_pin_mux[] = { + /* UART1_RTS as I2C2-SCL */ + {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART1_CTS as I2C2-SDA */ + {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART1_RXD */ + {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART1_TXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; +#ifdef CONFIG_MMC +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ + + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + {-1}, +}; +#endif +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + /* SPI0_SCLK */ + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D0 */ + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_D1 */ + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + /* SPI0_CS0 */ + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ + {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ + {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ + {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ + {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ + {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ + {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ + {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ + {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ + {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ + {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ + {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ + {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ + {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)}, + /* + * MII2_CRS is shared with + * NAND_WAIT0 + */ + {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */ + {-1}, +}; +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; +#endif +static struct module_pin_mux gpIOs[] = { + /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */ + {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ + {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, + /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */ + {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)}, + /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ + {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ + {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */ + {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */ + {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */ + {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */ + {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */ + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO2_0 (GPMC_nCS3) - DCOK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* + * GPIO0_7 (PWW0 OUT) + * DISPLAY_ONOFF (Backlight Enable at LVDS Versions) + */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */ + {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - REP-Switch */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)}, + /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */ + {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */ + {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, + /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */ + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, + /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, +#ifndef CONFIG_NAND + /* GPIO2_3 - NAND_OE */ + {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, + /* GPIO2_4 - NAND_WEN */ + {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, + /* GPIO2_5 - NAND_BE_CLE */ + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, +#endif + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mii2_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_MMC) + configure_module_pin_mux(mmc1_pin_mux); +#endif + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(uart1_pin_mux); + configure_module_pin_mux(gpIOs); +} diff --git a/board/BuR/tseries/Kconfig b/board/BuR/tseries/Kconfig deleted file mode 100644 index ed48300..0000000 --- a/board/BuR/tseries/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TSERIES - -config SYS_BOARD - default "tseries" - -config SYS_VENDOR - default "BuR" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "tseries" - -endif diff --git a/board/BuR/tseries/MAINTAINERS b/board/BuR/tseries/MAINTAINERS deleted file mode 100644 index e2e67e6..0000000 --- a/board/BuR/tseries/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -TSERIES BOARD -M: Hannes Schmelzer -S: Maintained -F: board/BuR/tseries/ -F: include/configs/tseries.h -F: configs/tseries_mmc_defconfig -F: configs/tseries_nand_defconfig -F: configs/tseries_spi_defconfig diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile deleted file mode 100644 index 43945d2..0000000 --- a/board/BuR/tseries/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Makefile -# -# Copyright (C) 2013 Hannes Schmelzer -# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifeq ($(CONFIG_SPL_BUILD),y) -obj-y := mux.o -endif -obj-y += ../common/common.o -obj-y += board.o diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c deleted file mode 100644 index bc119e6..0000000 --- a/board/BuR/tseries/board.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * board.c - * - * Board functions for B&R LEIT Board - * - * Copyright (C) 2013 Hannes Schmelzer - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/bur_common.h" -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* --------------------------------------------------------------------------*/ -/* -- defines for GPIO -- */ -#define REPSWITCH (0+20) /* GPIO0_20 */ - -#if defined(CONFIG_SPL_BUILD) -/* TODO: check ram-timing ! */ -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41K256M16HA125E_RD_DQS, - .datawdsratio0 = MT41K256M16HA125E_WR_DQS, - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, - .zq_config = MT41K256M16HA125E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, -}; - -static const struct ctrl_ioregs ddr3_ioregs = { - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, -}; - -#ifdef CONFIG_SPL_OS_BOOT -/* - * called from spl_nand.c - * return 0 for loading linux, return 1 for loading u-boot - */ -int spl_start_uboot(void) -{ - if (0 == gpio_get_value(REPSWITCH)) { - mdelay(1000); - printf("SPL: entering u-boot instead kernel image.\n"); - return 1; - } - return 0; -} -#endif /* CONFIG_SPL_OS_BOOT */ - -#define OSC (V_OSCK/1000000) -static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; - -void am33xx_spl_board_init(void) -{ - struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; - /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/ - struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; - - /* - * in TRM they write a reset value of 1 (=CLK_M_OSC) for the - * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set - * the source of timer6 clk to CLK_M_OSC - */ - writel(0x01, &cmdpll->clktimer6clk); - - /* enable additional clocks of modules which are accessed later */ - u32 *const clk_domains[] = { - &cmper->lcdcclkstctrl, - 0 - }; - - u32 *const clk_modules_tsspecific[] = { - &cmper->lcdclkctrl, - &cmper->timer5clkctrl, - &cmper->timer6clkctrl, - 0 - }; - do_enable_clocks(clk_domains, clk_modules_tsspecific, 1); - - /* setup LCD-Pixel Clock */ - writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */ - - /* setup I2C */ - enable_i2c_pin_mux(); - i2c_set_bus_num(0); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - pmicsetup(0); - - gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */ - gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */ -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr3; -} - -void sdram_init(void) -{ - config_ddr(400, &ddr3_ioregs, - &ddr3_data, - &ddr3_cmd_ctrl_data, - &ddr3_emif_reg_data, 0); -} -#endif /* CONFIG_SPL_BUILD */ - -/* Basic board specific setup. Pinmux has been handled already. */ -int board_init(void) -{ -#if defined(CONFIG_HW_WATCHDOG) - hw_watchdog_init(); -#endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_NAND - gpmc_init(); -#endif - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - if (0 == gpio_get_value(REPSWITCH)) { - lcd_position_cursor(1, 8); - lcd_puts( - "switching to network-console ... "); - setenv("bootcmd", "run netconsole"); - } - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c deleted file mode 100644 index 349788a..0000000 --- a/board/BuR/tseries/mux.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * mux.c - * - * Pinmux Setting for B&R LEIT Board(s) - * - * Copyright (C) 2013 Hannes Schmelzer - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -static struct module_pin_mux uart0_pin_mux[] = { - /* UART0_RTS */ - {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)}, - /* UART0_CTS */ - {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART0_RXD */ - {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART0_TXD */ - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, - {-1}, -}; -static struct module_pin_mux uart1_pin_mux[] = { - /* UART1_RTS as I2C2-SCL */ - {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART1_CTS as I2C2-SDA */ - {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART1_RXD */ - {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART1_TXD */ - {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, - {-1}, -}; -#ifdef CONFIG_MMC -static struct module_pin_mux mmc1_pin_mux[] = { - {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ - {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ - {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ - {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ - - {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ - {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ - {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ - {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ - {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ - {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ - {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ - {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ - {-1}, -}; -#endif -static struct module_pin_mux i2c0_pin_mux[] = { - /* I2C_DATA */ - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, - /* I2C_SCLK */ - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux spi0_pin_mux[] = { - /* SPI0_SCLK */ - {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, - /* SPI0_D0 */ - {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, - /* SPI0_D1 */ - {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, - /* SPI0_CS0 */ - {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, - {-1}, -}; - -static struct module_pin_mux mii1_pin_mux[] = { - {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ - {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ - {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ - {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ - {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ - {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ - {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ - {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ - {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ - {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ - {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ - {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ - {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ - {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ - {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {-1}, -}; - -static struct module_pin_mux mii2_pin_mux[] = { - {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ - {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ - {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ - {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ - {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ - {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ - {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ - {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ - {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ - {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ - {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ - {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ - {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ - {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)}, - /* - * MII2_CRS is shared with - * NAND_WAIT0 - */ - {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */ - {-1}, -}; -#ifdef CONFIG_NAND -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ - {-1}, -}; -#endif -static struct module_pin_mux gpIOs[] = { - /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */ - {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ - {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, - /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */ - {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)}, - /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ - {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ - {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */ - {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */ - {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */ - {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */ - {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */ - {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO2_0 (GPMC_nCS3) - DCOK */ - {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, - /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ - {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) }, - /* - * GPIO0_7 (PWW0 OUT) - * DISPLAY_ONOFF (Backlight Enable at LVDS Versions) - */ - {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */ - {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* GPIO0_20 (DMA_INTR1) - REP-Switch */ - {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)}, - /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */ - {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, - /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */ - {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, - /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */ - {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, - /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ - {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, -#ifndef CONFIG_NAND - /* GPIO2_3 - NAND_OE */ - {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, - /* GPIO2_4 - NAND_WEN */ - {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, - /* GPIO2_5 - NAND_BE_CLE */ - {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, -#endif - {-1}, -}; - -static struct module_pin_mux lcd_pin_mux[] = { - {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ - {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ - {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ - {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ - {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ - {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ - {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ - {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ - {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ - {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ - {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ - {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ - {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ - {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ - {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ - {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ - - {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ - {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ - {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ - {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ - {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ - {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ - {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ - {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ - - {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ - {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ - {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ - {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ - - {-1}, -}; - -void enable_uart0_pin_mux(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void enable_i2c_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); -} - -void enable_board_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); - configure_module_pin_mux(mii1_pin_mux); - configure_module_pin_mux(mii2_pin_mux); -#ifdef CONFIG_NAND - configure_module_pin_mux(nand_pin_mux); -#elif defined(CONFIG_MMC) - configure_module_pin_mux(mmc1_pin_mux); -#endif - configure_module_pin_mux(spi0_pin_mux); - configure_module_pin_mux(lcd_pin_mux); - configure_module_pin_mux(uart1_pin_mux); - configure_module_pin_mux(gpIOs); -} -- cgit v1.1