From 680c613a5cc7be59a9123765c51287bc306df02f Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 9 Aug 2010 18:39:57 -0500 Subject: powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/interrupts.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 6 +++--- arch/powerpc/cpu/mpc85xx/traps.c | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 8 +++++--- arch/powerpc/include/asm/immap_85xx.h | 4 +--- arch/powerpc/include/asm/immap_86xx.h | 9 ++++++--- 8 files changed, 19 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f15d43c..3f80700 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -74,7 +74,7 @@ int checkcpu (void) puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2c3be6d..27236a0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -179,7 +179,7 @@ static void corenet_tb_init(void) volatile ccsr_rcpm_t *rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); volatile ccsr_pic_t *pic = - (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); u32 whoami = in_be32(&pic->whoami); /* Enable the timebase register for this core */ diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index ac8c01a..a62b031 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -35,7 +35,7 @@ int interrupt_init_cpu(unsigned int *decrementer_count) { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; out_be32(&pic->gcr, MPC85xx_PICGCR_RST); while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index e05257c..603baef 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -38,7 +38,7 @@ u32 get_my_id() int cpu_reset(int nr) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); /* the dummy read works around an errata on early 85xx MP PICs */ (void)in_be32(&pic->pir); @@ -207,7 +207,7 @@ static void plat_mp_up(unsigned long bootpg) gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); - pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; @@ -272,7 +272,7 @@ static void plat_mp_up(unsigned long bootpg) volatile u32 bpcr; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); u32 devdisr; int timeout = 10; diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 7e96664..7800717 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -288,7 +288,7 @@ UnknownException(struct pt_regs *regs) void ExtIntException(struct pt_regs *regs) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); uint vect; diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 97a94f4..5b30fbd 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -110,13 +110,15 @@ struct cpu_type *identify_cpu(u32 ver) } int cpu_numcores() { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->cpu; /* better to query feature reporting register than just assume 1 */ +#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 +#define MPC8xxx_PICFRR_NCPU_SHIFT 8 if (cpu == &cpu_type_unknown) - return ((in_be32(&pic->frr) & MPC85xx_PICFRR_NCPU_MASK) >> - MPC85xx_PICFRR_NCPU_SHIFT) + 1; + return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> + MPC8xxx_PICFRR_NCPU_SHIFT) + 1; return cpu->num_cores; } diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c1382c8..e5a02c3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -760,8 +760,6 @@ typedef struct ccsr_pic { u32 eoi; /* End Of IRQ */ u8 res9[3916]; u32 frr; /* Feature Reporting */ -#define MPC85xx_PICFRR_NCPU_MASK 0x00001f00 -#define MPC85xx_PICFRR_NCPU_SHIFT 8 u8 res10[28]; u32 gcr; /* Global Configuration */ #define MPC85xx_PICGCR_RST 0x80000000 @@ -2301,7 +2299,7 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_ADDR \ +#define CONFIG_SYS_MPC8xxx_PIC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) #define CONFIG_SYS_MPC85xx_CPM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 4bebb68..4e60cbb 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1250,12 +1250,15 @@ typedef struct immap { extern immap_t *immr; -#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC86xx_DDR_OFFSET 0x2000 #define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET) -#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC86xx_DDR2_OFFSET 0x6000 #define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) +#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000 +#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET) + #define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000 #ifdef CONFIG_MPC8610 -- cgit v1.1 From ed062e0f6c7ee8c56eb096fdd3e01712c53fc2e4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 17 Aug 2010 23:12:37 -0500 Subject: powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 8 ++++---- arch/powerpc/include/asm/fsl_liodn.h | 8 ++++---- arch/powerpc/include/asm/immap_85xx.h | 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 3861146..a6cfaa5 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -81,10 +81,10 @@ struct liodn_id_table fman2_liodn_tbl[] = { #endif struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JQ_LIODN_ENTRY(0, 146, 154), - SET_SEC_JQ_LIODN_ENTRY(1, 147, 155), - SET_SEC_JQ_LIODN_ENTRY(2, 178, 186), - SET_SEC_JQ_LIODN_ENTRY(3, 179, 187), + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), + SET_SEC_JR_LIODN_ENTRY(1, 147, 155), + SET_SEC_JR_LIODN_ENTRY(2, 178, 186), + SET_SEC_JR_LIODN_ENTRY(3, 179, 187), SET_SEC_RTIC_LIODN_ENTRY(a, 144), SET_SEC_RTIC_LIODN_ENTRY(b, 145), SET_SEC_RTIC_LIODN_ENTRY(c, 176), diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index acdc99a..4c17fe2 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -115,11 +115,11 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ -#define SET_SEC_JQ_LIODN_ENTRY(jqNum, liodnA, liodnB) \ - SET_LIODN_ENTRY_2("fsl,sec4.0-job-queue", liodnA, liodnB,\ - offsetof(ccsr_sec_t, jqliodnr[jqNum].ls) + \ +#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jqNum) + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) /* This is a bit evil since we treat rtic param as both a string & hex value */ #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index e5a02c3..3dd2b7f 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2063,7 +2063,7 @@ typedef struct ccsr_sec { struct { u32 ms; /* Job Ring LIODN Register, MS */ u32 ls; /* Job Ring LIODN Register, LS */ - } jqliodnr[4]; + } jrliodnr[4]; u8 res2[0x30]; struct { u32 ms; /* RTIC LIODN Register, MS */ @@ -2108,8 +2108,8 @@ typedef struct ccsr_sec { #define SEC_CTPR_MS_AXI_LIODN 0x08000000 #define SEC_CTPR_MS_QI 0x02000000 #define SEC_RVID_MA 0x0f000000 -#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 -#define SEC_CHANUM_MS_JQNUM_SHIFT 28 +#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JRNUM_SHIFT 28 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 #endif -- cgit v1.1 From 62a05573822fc253a1ad5037482511347d6abaa5 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Fri, 30 Jul 2010 14:12:12 +0800 Subject: nios2: fix bootm error on fdt args We should check argv[3] only if there are enough args. Otherwise, it might cause invalid memory access fault. Signed-off-by: Thomas Chou Signed-off-by: Scott McNutt --- arch/nios2/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index e25a113..40a4d15 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -42,7 +42,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima if (boot_get_fdt(flag, argc, argv, images, &of_flat_tree, &of_size)) return 1; #endif - if (!of_flat_tree) + if (!of_flat_tree && argc > 3) of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16); if (of_flat_tree) initrd_end = (ulong)of_flat_tree; -- cgit v1.1 From 7a6a7d10e6b96ab4a5c0d8852802ec52be2b582e Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Mon, 16 Aug 2010 10:49:44 +0800 Subject: nios2: fix out of reach case for do_reset There is a limitation (or bug?) of nios2 toolchain. The nios2 gcc didn't generate correct code when the reset vector is passed as a constant. It just generated a direct "call", which was wrong when the reset vector was not located in the same 256MB span as u-boot. The "Nios II Processor Reference Handbook" said, "call can transfer execution anywhere within the 256 MByte range determined by PC31..28. The Nios II GNU linker does not automatically handle cases in which the address is out of this range." So we have to use registered "callr" instruction to do the job. Signed-off-by: Thomas Chou Signed-off-by: Scott McNutt --- arch/nios2/cpu/cpu.c | 11 +++++------ arch/nios2/include/asm/system.h | 5 +++++ 2 files changed, 10 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 6379534..d9c6544 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -40,11 +40,10 @@ int checkcpu (void) return (0); } - -int do_reset (void) +int do_reset(void) { - void (*rst)(void) = (void(*)(void))CONFIG_SYS_RESET_ADDR; - disable_interrupts (); - rst(); - return(0); + disable_interrupts(); + /* indirect call to go beyond 256MB limitation of toolchain */ + nios2_callr(CONFIG_SYS_RESET_ADDR); + return 0; } diff --git a/arch/nios2/include/asm/system.h b/arch/nios2/include/asm/system.h index bb03ca5..086d92b 100644 --- a/arch/nios2/include/asm/system.h +++ b/arch/nios2/include/asm/system.h @@ -56,4 +56,9 @@ ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ }) +/* indirect call to go beyond 256MB limitation of toolchain */ +#define nios2_callr(addr) __asm__ __volatile__ ( \ + "callr %0" \ + : : "r" (addr)) + #endif /* __ASM_NIOS2_SYSTEM_H */ -- cgit v1.1 From b80d30546e88c70985094d81297d449b2bc59033 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Thu, 19 Aug 2010 13:57:48 -0500 Subject: mpx85xx/fdt: Add cpu-release-addr for all cores We currently do not add a cpu-release-addr for core 0, this is needed when we want to reset core 0 and later restart it from Linux Signed-off-by: Matthew McClintock Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/fdt.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 8e7b827..4540364 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -54,18 +54,19 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) { + u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; + val = cpu_to_fdt32(val); if (*reg == id) { - fdt_setprop_string(blob, off, "status", "okay"); + fdt_setprop_string(blob, off, "status", + "okay"); } else { - u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; - val = cpu_to_fdt32(val); fdt_setprop_string(blob, off, "status", "disabled"); - fdt_setprop_string(blob, off, "enable-method", - "spin-table"); - fdt_setprop(blob, off, "cpu-release-addr", - &val, sizeof(val)); } + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); } else { printf ("cpu NULL\n"); } -- cgit v1.1 From 46d8ece4e8fd2c4b92c99f7139332f49c368384e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 18 Aug 2010 19:39:08 -0500 Subject: omap2: i2c: add syss offset OMAP2420 ES2.3 trm defines syss register offset as 0x10. Add it. Cc: Steve Sakoman Cc: Heiko Cc: Sandeep Paulraj Cc: Wolfang Denk Signed-off-by: Nishanth Menon Acked-by: Steve Sakoman --- arch/arm/include/asm/arch-omap24xx/i2c.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h index 19046aa..418a432 100644 --- a/arch/arm/include/asm/arch-omap24xx/i2c.h +++ b/arch/arm/include/asm/arch-omap24xx/i2c.h @@ -36,7 +36,9 @@ struct i2c { unsigned short stat; /* 0x08 */ unsigned short res3; unsigned short iv; /* 0x0C */ - unsigned short res4[3]; + unsigned short res4; + unsigned short syss; /* 0x10 */ + unsigned short res4p1; unsigned short buf; /* 0x14 */ unsigned short res5; unsigned short cnt; /* 0x18 */ -- cgit v1.1 From a947f4b68b04fa73d8c862185b8cb7e61abda211 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 18 Aug 2010 19:39:09 -0500 Subject: omap2: i2c: remove redundant header definitions Remove the register offset and common defines which are already present in drivers/i2c/omap24xx.h. All of these defines carry the same value even. Cc: Steve Sakoman Cc: Heiko Cc: Sandeep Paulraj Cc: Wolfang Denk Signed-off-by: Nishanth Menon Acked-by: Steve Sakoman --- arch/arm/include/asm/arch-omap24xx/i2c.h | 106 ------------------------------- 1 file changed, 106 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h index 418a432..6f64519 100644 --- a/arch/arm/include/asm/arch-omap24xx/i2c.h +++ b/arch/arm/include/asm/arch-omap24xx/i2c.h @@ -65,110 +65,4 @@ struct i2c { #define I2C_BUS_MAX 2 -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */ -#define OMAP_I2C_STANDARD 100000 -#define OMAP_I2C_FAST_MODE 400000 -#define OMAP_I2C_HIGH_SPEED 3400000 - -#define SYSTEM_CLOCK_12 12000000 -#define SYSTEM_CLOCK_13 13000000 -#define SYSTEM_CLOCK_192 19200000 -#define SYSTEM_CLOCK_96 96000000 - -#ifndef I2C_IP_CLK -#define I2C_IP_CLK SYSTEM_CLOCK_96 -#endif - -#ifndef I2C_INTERNAL_SAMPLING_CLK -#define I2C_INTERNAL_SAMPLING_CLK 19200000 -#endif - -/* These are the trim values for standard and fast speed */ -#ifndef I2C_FASTSPEED_SCLL_TRIM -#define I2C_FASTSPEED_SCLL_TRIM 6 -#endif -#ifndef I2C_FASTSPEED_SCLH_TRIM -#define I2C_FASTSPEED_SCLH_TRIM 6 -#endif - -/* These are the trim values for high speed */ -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif - -#define I2C_PSC_MAX 0x0f -#define I2C_PSC_MIN 0x00 - - #endif -- cgit v1.1 From 8d9207c79223497666580c51be7c4f9e2d7a4d1f Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 27 Aug 2010 16:25:56 -0500 Subject: Fix parameters to support RDIMM for P2020DS Signed-off-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index dccb7aa..e82082e 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -613,6 +613,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR3) md_en = popts->mirrored_dimm; #endif + rcw_en = popts->registered_dimm_en; qd_en = popts->quad_rank_present ? 1 : 0; ddr->ddr_sdram_cfg_2 = (0 | ((frc_sr & 0x1) << 31) -- cgit v1.1 From c1ab75c7d4e5d080c630335b78681c50aa3569a5 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 26 Aug 2010 17:14:51 +0200 Subject: ppc4xx: Fix 440EPx bug in reconfigure_pll() This patch fixes a bug in reconfigure_pll(), where the detection of the current bootstrap option is wrong. The ICS bits where incorrectly shifted. This bug was found on the lwmon5 board, which uses bootstrap option H (I2C bootstrap EEPROM). Additionally a bit of code was moved into the if statement, since its only used after later on. No need to run this code all the time. Also, a few empty lines are added to make the code better readable. Signed-off-by: Stefan Roese Cc: Rupjyoti Sarmah Cc: Victor Gallardo --- arch/powerpc/cpu/ppc4xx/cpu_init.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede..b31bd0b 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq) * modify it. */ if (temp == 1) { - mfcpr(CPR0_PLLD, reg); - /* Get current value of fbdv. */ - temp = (reg & PLLD_FBDV_MASK) >> 24; - fbdv = temp ? temp : 32; - /* Get current value of lfbdv. */ - temp = (reg & PLLD_LFBDV_MASK); - lfbdv = temp ? temp : 64; /* * Load register that contains current boot strapping option. */ mfcpr(CPR0_ICFG, reg); - /* Shift strapping option into low 3 bits.*/ - reg = (reg >> 28); + /* + * Strapping option bits (ICS) are already in correct position, + * only masking needed. + */ + reg &= CPR0_ICFG_ICS_MASK; if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { + mfcpr(CPR0_PLLD, reg); + + /* Get current value of fbdv. */ + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + + /* Get current value of lfbdv. */ + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + /* * Get current value of FWDVA. Assign current FWDVA to * new FWDVB. @@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq) mfcpr(CPR0_PLLD, reg); target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; fwdvb = target_fwdvb ? target_fwdvb : 8; + /* * Get current value of FWDVB. Assign current FWDVB to * new FWDVA. */ target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; fwdva = target_fwdva ? target_fwdva : 16; + /* * Update CPR0_PLLD with switched FWDVA and FWDVB. */ @@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq) ((fbdv == 32 ? 0 : fbdv) << 24) | (lfbdv == 64 ? 0 : lfbdv); mtcpr(CPR0_PLLD, reg); + /* Acknowledge that a reset is required. */ reset_needed = 1; } -- cgit v1.1 From f3cac5384074f3c20b5bcbbdbccbe1e2e25ffc76 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 31 Aug 2010 11:27:14 +0200 Subject: ppc4xx: Invalidate d-cache when used as init-ram We need to invalidate the data cache after it has been used as init-ram. This problem was detected on the lwmon5 update. Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/start.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 5296dad..4bad32f 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1459,6 +1459,11 @@ relocate_code: mtspr SPRN_DTV3,r6 msync isync + + /* Invalidate data cache, now no longer our stack */ + dccci 0,0 + sync + isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ /* -- cgit v1.1