From 2f6d42b9dfc5fb40ad59c5e81dab6298a192452b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 24 Nov 2014 21:18:20 -0700 Subject: x86: Add ivybridge directory to Makefile It is now required to add subdirectories in the x86 cpu Makefile. Add this to fix a build breakage for chromebook_link. Signed-off-by: Simon Glass --- arch/x86/cpu/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 2b9e9b9..818969f 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -13,4 +13,6 @@ obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o obj-y += interrupts.o cpu.o call64.o obj-$(CONFIG_SYS_COREBOOT) += coreboot/ +obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ +obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_PCI) += pci.o -- cgit v1.1 From 65990d568074ad878cbc7e4eb1053508e3707cb6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:22 -0700 Subject: x86: Remove board_early_init_r() This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/coreboot/coreboot.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 2df7288..cfacc05 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -39,17 +39,6 @@ int board_early_init_f(void) return 0; } -int board_early_init_r(void) -{ - /* CPU Speed to 100MHz */ - gd->cpu_clk = 100000000; - - /* Crystal is 33.000MHz */ - gd->bus_clk = 33000000; - - return 0; -} - int print_cpuinfo(void) { return default_print_cpuinfo(); -- cgit v1.1 From 512e581c86a4066147a9a095eaed05a7aa9043df Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:23 -0700 Subject: x86: Panic if there is no relocation data This normally indicates a problem which will prevent relocation from functioning, resulting in a hang. Panic in this case to make it easier to debug. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/relocate.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index faca38f..b33586b 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -76,6 +76,9 @@ int do_elf_reloc_fixups(void) /* The size of the region of u-boot that runs out of RAM. */ uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; + if (re_src == re_end) + panic("No relocation data"); + do { /* Get the location from the relocation entry */ offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; -- cgit v1.1 From 091c4943539f8a0b238246e043683e3cbf657b5e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:24 -0700 Subject: x86: Ensure that all relocation data is included in the image Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/u-boot.lds | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index f48bff5..124a361 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -44,7 +44,9 @@ SECTIONS . = ALIGN(4); __rel_dyn_start = .; - .rel.dyn : { *(.rel.dyn) } + .rel.dyn : { + *(.rel*) + } __rel_dyn_end = .; . = ALIGN(4); _end = .; -- cgit v1.1 From a6a957849a0ad20323156ef2439b490306bd5e35 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:25 -0700 Subject: x86: Factor out common values in the link script Define the reset base in config.mk so that it does not need to be calculated twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values to fit with this new approach. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/config.mk | 5 +++-- arch/x86/cpu/u-boot.lds | 14 +++++++++----- 2 files changed, 12 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index f7b01d3..84aeaf3 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -12,5 +12,6 @@ PLATFORM_CPPFLAGS += -D__I386__ -Werror # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! LDPPFLAGS += -DRESET_SEG_START=0xffff0000 LDPPFLAGS += -DRESET_SEG_SIZE=0x10000 -LDPPFLAGS += -DRESET_VEC_LOC=0xfff0 -LDPPFLAGS += -DSTART_16=0xf800 +LDPPFLAGS += -DRESET_VEC_LOC=0xfffffff0 +LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) +LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)" diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index 124a361..b0d8531 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -66,15 +66,19 @@ SECTIONS /DISCARD/ : { *(.gnu*) } #ifdef CONFIG_X86_RESET_VECTOR - /* * The following expressions place the 16-bit Real-Mode code and * Reset Vector at the end of the Flash ROM */ - . = START_16; - .start16 : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); } + . = START_16 - RESET_SEG_START; + .start16 : AT (START_16) { + KEEP(*(.start16)); + } - . = RESET_VEC_LOC; - .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); } + . = RESET_VEC_LOC - RESET_SEG_START; + .resetvec : AT (RESET_VEC_LOC) { + KEEP(*(.resetvec)); + } #endif + } -- cgit v1.1 From a2f5d091ccdc6ffd8fa11c140bc5a93234ee4833 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:27 -0700 Subject: x86: Add ioapic.h header Add definitions for the I/O Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass --- arch/x86/include/asm/ioapic.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/x86/include/asm/ioapic.h (limited to 'arch') diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h new file mode 100644 index 0000000..699160f --- /dev/null +++ b/arch/x86/include/asm/ioapic.h @@ -0,0 +1,38 @@ +/* + * From coreboot file of the same name + * + * Copyright (C) 2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_IOAPIC_H +#define __ASM_IOAPIC_H + +#define IO_APIC_ADDR 0xfec00000 +#define IO_APIC_INDEX IO_APIC_ADDR +#define IO_APIC_DATA (IO_APIC_ADDR + 0x10) +#define IO_APIC_INTERRUPTS 24 + +#define ALL (0xff << 24) +#define NONE 0 +#define DISABLED (1 << 16) +#define ENABLED (0 << 16) +#define TRIGGER_EDGE (0 << 15) +#define TRIGGER_LEVEL (1 << 15) +#define POLARITY_HIGH (0 << 13) +#define POLARITY_LOW (1 << 13) +#define PHYSICAL_DEST (0 << 11) +#define LOGICAL_DEST (1 << 11) +#define ExtINT (7 << 8) +#define NMI (4 << 8) +#define SMI (2 << 8) +#define INT (1 << 8) + +u32 io_apic_read(u32 ioapic_base, u32 reg); +void io_apic_write(u32 ioapic_base, u32 reg, u32 value); +void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); +void setup_ioapic(u32 ioapic_base, u8 ioapic_id); +void clear_ioapic(u32 ioapic_base); + +#endif -- cgit v1.1 From e94ea6f656641e30392cf76089b65ea9aecde160 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:28 -0700 Subject: x86: pci: Add handlers before and after a PCI hose scan Some boards will want to do some setup before and after a PCI hose is scanned. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/pci.c | 12 ++++++++++++ arch/x86/include/asm/pci.h | 3 +++ 2 files changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index e399388..f3492c3 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -33,6 +33,16 @@ int pci_early_init_hose(struct pci_controller **hosep) return 0; } +__weak int board_pci_pre_scan(struct pci_controller *hose) +{ + return 0; +} + +__weak int board_pci_post_scan(struct pci_controller *hose) +{ + return 0; +} + void pci_init_board(void) { struct pci_controller *hose = &x86_hose; @@ -44,7 +54,9 @@ void pci_init_board(void) pci_setup_type1(hose); pci_register_hose(hose); + board_pci_pre_scan(hose); hose->last_busno = pci_hose_scan(hose); + board_pci_post_scan(hose); } static struct pci_controller *get_hose(void) diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 98817aa..ac1a808 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -34,6 +34,9 @@ void board_pci_setup_hose(struct pci_controller *hose); */ int pci_early_init_hose(struct pci_controller **hosep); +int board_pci_pre_scan(struct pci_controller *hose); +int board_pci_post_scan(struct pci_controller *hose); + /* * Simple PCI access routines - these work from either the early PCI hose * or the 'real' one, created after U-Boot has memory available -- cgit v1.1 From a0bd851ecec0e04c5e3f224a912b2872618f77ba Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:31 -0700 Subject: x86: Set up edge triggering on interrupt 9 Add this additional init in case it is needed by the OS. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/interrupt.h | 11 +++++++++++ arch/x86/lib/pcat_interrupts.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) (limited to 'arch') diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index 3f46e09..25abde7 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -27,4 +27,15 @@ void specific_eoi(int irq); extern char exception_stack[]; +/** + * configure_irq_trigger() - Configure IRQ triggering + * + * Switch the given interrupt to be level / edge triggered + * + * @param int_num legacy interrupt number (3-7, 9-15) + * @param is_level_triggered true for level triggered interrupt, false for + * edge triggered interrupt + */ +void configure_irq_trigger(int int_num, bool is_level_triggered); + #endif diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c index 4c86f7f..2dc2fbd 100644 --- a/arch/x86/lib/pcat_interrupts.c +++ b/arch/x86/lib/pcat_interrupts.c @@ -62,6 +62,9 @@ int interrupt_init(void) */ unmask_irq(2); + /* Interrupt 9 should be level triggered (SCI). The OS might do this */ + configure_irq_trigger(9, true); + enable_interrupts(); return 0; @@ -114,3 +117,38 @@ void specific_eoi(int irq) outb(OCW2_SEOI | irq, MASTER_PIC + OCW2); } + +#define ELCR1 0x4d0 +#define ELCR2 0x4d1 + +void configure_irq_trigger(int int_num, bool is_level_triggered) +{ + u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8); + + debug("%s: current interrupts are 0x%x\n", __func__, int_bits); + if (is_level_triggered) + int_bits |= (1 << int_num); + else + int_bits &= ~(1 << int_num); + + /* Write new values */ + debug("%s: try to set interrupts 0x%x\n", __func__, int_bits); + outb((u8)(int_bits & 0xff), ELCR1); + outb((u8)(int_bits >> 8), ELCR2); + +#ifdef PARANOID_IRQ_TRIGGERS + /* + * Try reading back the new values. This seems like an error but is + * not + */ + if (inb(ELCR1) != (int_bits & 0xff)) { + printf("%s: lower order bits are wrong: want 0x%x, got 0x%x\n", + __func__, (int_bits & 0xff), inb(ELCR1)); + } + + if (inb(ELCR2) != (int_bits >> 8)) { + printf("%s: higher order bits are wrong: want 0x%x, got 0x%x\n", + __func__, (int_bits>>8), inb(ELCR2)); + } +#endif +} -- cgit v1.1 From 4e7a6acac7a46cc5ab0ea7986cc9e74351eed165 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:32 -0700 Subject: x86: ivybridge: Add support for BD82x6x PCH Add basic setup for the PCH. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 99 +++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/pci.c | 40 +++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 14 ++++ arch/x86/include/asm/arch-ivybridge/pch.h | 13 ++++ 5 files changed, 167 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/bd82x6x.c create mode 100644 arch/x86/include/asm/arch-ivybridge/bd82x6x.h (limited to 'arch') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 721b37e..b37fb8f 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += bd82x6x.o obj-y += car.o obj-y += cpu.o obj-y += early_init.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c new file mode 100644 index 0000000..fab7c53 --- /dev/null +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void bd82x6x_pci_init(pci_dev_t dev) +{ + u16 reg16; + u8 reg8; + + debug("bd82x6x PCI init.\n"); + /* Enable Bus Master */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* This device has no interrupt */ + pci_write_config8(dev, INTR, 0xff); + + /* disable parity error response and SERR */ + reg16 = pci_read_config16(dev, BCTRL); + reg16 &= ~(1 << 0); + reg16 &= ~(1 << 1); + pci_write_config16(dev, BCTRL, reg16); + + /* Master Latency Count must be set to 0x04! */ + reg8 = pci_read_config8(dev, SMLT); + reg8 &= 0x07; + reg8 |= (0x04 << 3); + pci_write_config8(dev, SMLT, reg8); + + /* Will this improve throughput of bus masters? */ + pci_write_config8(dev, PCI_MIN_GNT, 0x06); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, PSTS); + /* reg16 |= 0xf900; */ + pci_write_config16(dev, PSTS, reg16); + + reg16 = pci_read_config16(dev, SECSTS); + /* reg16 |= 0xf900; */ + pci_write_config16(dev, SECSTS, reg16); +} + +#define PCI_BRIDGE_UPDATE_COMMAND +void bd82x6x_pci_dev_enable_resources(pci_dev_t dev) +{ + uint16_t command; + + command = pci_read_config16(dev, PCI_COMMAND); + command |= PCI_COMMAND_IO; +#ifdef PCI_BRIDGE_UPDATE_COMMAND + /* + * If we write to PCI_COMMAND, on some systems this will cause the + * ROM and APICs to become invisible. + */ + debug("%x cmd <- %02x\n", dev, command); + pci_write_config16(dev, PCI_COMMAND, command); +#else + printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); +#endif +} + +void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) +{ + uint16_t ctrl; + + ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + ctrl |= PCI_COMMAND_IO; + ctrl |= PCI_BRIDGE_CTL_VGA; + debug("%x bridge ctrl <- %04x\n", dev, ctrl); + pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + + bd82x6x_pci_dev_enable_resources(dev); +} + +int bd82x6x_init_pci_devices(void) +{ + return 0; +} + +int bd82x6x_init(void) +{ + bd82x6x_pci_init(PCH_DEV); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c index c1ae658..452d1c3 100644 --- a/arch/x86/cpu/ivybridge/pci.c +++ b/arch/x86/cpu/ivybridge/pci.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *table) @@ -58,3 +60,41 @@ void board_pci_setup_hose(struct pci_controller *hose) hose->region_count = 3; } + +int board_pci_pre_scan(struct pci_controller *hose) +{ + pci_dev_t dev; + u16 reg16; + + bd82x6x_init(); + + reg16 = 0xff; + dev = PCH_DEV; + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + pci_write_bar32(hose, dev, 0, 0xf0000000); + + return 0; +} + +int board_pci_post_scan(struct pci_controller *hose) +{ + int ret; + + ret = bd82x6x_init_pci_devices(); + if (ret) { + printf("bd82x6x_init_pci_devices() failed: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h new file mode 100644 index 0000000..e02520c --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_BD82X6X_H +#define _ASM_ARCH_BD82X6X_H + +void bd82x6x_pci_init(pci_dev_t dev); +int bd82x6x_init_pci_devices(void); +int bd82x6x_init(void); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index c6efdb8..aa626ad 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -19,6 +19,16 @@ #define SMBUS_IO_BASE 0x0400 +/* PCI Configuration Space (D30:F0): PCI2PCI */ +#define PSTS 0x06 +#define SMLT 0x1b +#define SECSTS 0x1e +#define INTR 0x3c +#define BCTRL 0x3e +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) + #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0) @@ -343,6 +353,9 @@ #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +int lpc_init(struct pci_controller *hose, pci_dev_t dev); +void lpc_enable(pci_dev_t dev); + /** * lpc_early_init() - set up LPC serial ports and other early things * -- cgit v1.1 From 3e0332c0b90323ca3c0584e9ae5592b04b121bae Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:33 -0700 Subject: x86: Add a simple header file for ACPI We don't use many features yet, so this only has a few declarations. It will be expanded as needed. Signed-off-by: Simon Glass --- arch/x86/include/asm/acpi.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/x86/include/asm/acpi.h (limited to 'arch') diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h new file mode 100644 index 0000000..4872b92 --- /dev/null +++ b/arch/x86/include/asm/acpi.h @@ -0,0 +1,24 @@ +/* + * From coreboot + * + * Copyright (C) 2004 SUSE LINUX AG + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2008-2009 coresystems GmbH + * (Written by Stefan Reinauer ) + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ACPI_H +#define __ASM_ACPI_H + +#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ +#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */ +#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */ +#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */ + +/* 0 = S0, 1 = S1 ...*/ +int acpi_get_slp_type(void); +void apci_set_slp_type(int type); + +#endif -- cgit v1.1 From 8c74a57318d1302d28a10ae862a7faa9086e2660 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:34 -0700 Subject: x86: ivybridge: Add PCH init Add required init for the Intel Platform Controller Hub in ivybridge. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/pch.c | 123 ++++++++++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/pch.h | 49 ++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/pch.c (limited to 'arch') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index b37fb8f..479e446 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -12,6 +12,7 @@ obj-y += early_me.o obj-y += lpc.o obj-y += me_status.o obj-y += microcode_intel.o +obj-y += pch.o obj-y += pci.o obj-y += report_platform.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c new file mode 100644 index 0000000..fa04d48 --- /dev/null +++ b/arch/x86/cpu/ivybridge/pch.c @@ -0,0 +1,123 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +static int pch_revision_id = -1; +static int pch_type = -1; + +int pch_silicon_revision(void) +{ + pci_dev_t dev; + + dev = PCH_LPC_DEV; + + if (pch_revision_id < 0) + pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); + return pch_revision_id; +} + +int pch_silicon_type(void) +{ + pci_dev_t dev; + + dev = PCH_LPC_DEV; + + if (pch_type < 0) + pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); + return pch_type; +} + +int pch_silicon_supported(int type, int rev) +{ + int cur_type = pch_silicon_type(); + int cur_rev = pch_silicon_revision(); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned try = IOBP_RETRY; + u32 data; + + while (try--) { + data = readl(RCB_REG(IOBPS)); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printf("IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data; + + /* Set the address */ + writel(address, RCB_REG(IOBPIRI)); + + /* READ OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_READ_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = readl(RCB_REG(IOBPD)); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { + printf("IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Write IOBP data */ + writel(data, RCB_REG(IOBPD)); + if (!iobp_poll()) + return; +} diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index aa626ad..b3ec7c5 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -14,11 +14,31 @@ #include +/* PCH types */ +#define PCH_TYPE_CPT 0x1c /* CougarPoint */ +#define PCH_TYPE_PPT 0x1e /* IvyBridge */ + +/* PCH stepping values for LPC device */ +#define PCH_STEP_A0 0 +#define PCH_STEP_A1 1 +#define PCH_STEP_B0 2 +#define PCH_STEP_B1 3 +#define PCH_STEP_B2 4 +#define PCH_STEP_B3 5 #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 #define SMBUS_IO_BASE 0x0400 +int pch_silicon_revision(void); +int pch_silicon_type(void); +int pch_silicon_supported(int type, int rev); +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b @@ -40,6 +60,35 @@ /* PCI Configuration Space (D31:F0): LPC */ #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) +#define SERIRQ_CNTL 0x64 + +#define GEN_PMCON_1 0xa0 +#define GEN_PMCON_2 0xa2 +#define GEN_PMCON_3 0xa4 +#define ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) + +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0xDC +#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ +#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_ROUT 0xb8 + +#define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 +#define PIRQE_ROUT 0x68 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6A +#define PIRQH_ROUT 0x6B #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 -- cgit v1.1 From 72cd085aaed511abf1ece0b406b79b90d26826af Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:35 -0700 Subject: x86: ivybridge: Add additional LPC init Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/bd82x6x.c | 6 + arch/x86/cpu/ivybridge/lpc.c | 523 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 528 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index fab7c53..be4db74 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -88,6 +88,12 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) int bd82x6x_init_pci_devices(void) { + struct pci_controller *hose; + + hose = pci_bus_to_hose(0); + lpc_enable(PCH_LPC_DEV); + lpc_init(hose, PCH_LPC_DEV); + return 0; } diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 621ef2c..43fdd31 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -9,10 +9,460 @@ #include #include #include +#include #include +#include +#include +#include +#include #include #include +#define NMI_OFF 0 + +#define ENABLE_ACPI_MODE_IN_COREBOOT 0 +#define TEST_SMM_FLASH_LOCKDOWN 0 + +static int pch_enable_apic(pci_dev_t dev) +{ + u32 reg32; + int i; + + /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */ + pci_write_config8(dev, ACPI_CNTL, 0x80); + + writel(0, IO_APIC_INDEX); + writel(1 << 25, IO_APIC_DATA); + + /* affirm full set of redirection table entries ("write once") */ + writel(1, IO_APIC_INDEX); + reg32 = readl(IO_APIC_DATA); + writel(1, IO_APIC_INDEX); + writel(reg32, IO_APIC_DATA); + + writel(0, IO_APIC_INDEX); + reg32 = readl(IO_APIC_DATA); + debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); + if (reg32 != (1 << 25)) { + printf("APIC Error - cannot write to registers\n"); + return -EPERM; + } + + debug("Dumping IOAPIC registers\n"); + for (i = 0; i < 3; i++) { + writel(i, IO_APIC_INDEX); + debug(" reg 0x%04x:", i); + reg32 = readl(IO_APIC_DATA); + debug(" 0x%08x\n", reg32); + } + + /* Select Boot Configuration register. */ + writel(3, IO_APIC_INDEX); + + /* Use Processor System Bus to deliver interrupts. */ + writel(1, IO_APIC_DATA); + + return 0; +} + +static void pch_enable_serial_irqs(pci_dev_t dev) +{ + u32 value; + + /* Set packet length and toggle silent mode bit for one frame. */ + value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); +#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE + pci_write_config8(dev, SERIRQ_CNTL, value); +#else + pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6)); +#endif +} + +static int pch_pirq_init(const void *blob, int node, pci_dev_t dev) +{ + uint8_t route[8], *ptr; + + if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route, + sizeof(route))) + return -EINVAL; + ptr = route; + pci_write_config8(dev, PIRQA_ROUT, *ptr++); + pci_write_config8(dev, PIRQB_ROUT, *ptr++); + pci_write_config8(dev, PIRQC_ROUT, *ptr++); + pci_write_config8(dev, PIRQD_ROUT, *ptr++); + + pci_write_config8(dev, PIRQE_ROUT, *ptr++); + pci_write_config8(dev, PIRQF_ROUT, *ptr++); + pci_write_config8(dev, PIRQG_ROUT, *ptr++); + pci_write_config8(dev, PIRQH_ROUT, *ptr++); + + /* + * TODO(sjg@chromium.org): U-Boot does not set up the interrupts + * here. It's unclear if it is needed + */ + return 0; +} + +static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev) +{ + u8 route[16]; + u32 reg; + int gpi; + + if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route, + sizeof(route))) + return -EINVAL; + + for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) + reg |= route[gpi] << (gpi * 2); + + pci_write_config32(dev, 0xb8, reg); + + return 0; +} + +static int pch_power_options(const void *blob, int node, pci_dev_t dev) +{ + u8 reg8; + u16 reg16, pmbase; + u32 reg32; + const char *state; + int pwr_on; + int nmi_option; + int ret; + + /* + * Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + * + * If the option is not existent (Laptops), use Kconfig setting. + * TODO(sjg@chromium.org): Make this configurable + */ + pwr_on = MAINBOARD_POWER_ON; + + reg16 = pci_read_config16(dev, GEN_PMCON_3); + reg16 &= 0xfffe; + switch (pwr_on) { + case MAINBOARD_POWER_OFF: + reg16 |= 1; + state = "off"; + break; + case MAINBOARD_POWER_ON: + reg16 &= ~1; + state = "on"; + break; + case MAINBOARD_POWER_KEEP: + reg16 &= ~1; + state = "state keep"; + break; + default: + state = "undefined"; + } + + reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + + reg16 &= ~(1 << 10); + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + + pci_write_config16(dev, GEN_PMCON_3, reg16); + debug("Set power %s after power failure.\n", state); + + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x70); + /* TODO(sjg@chromium.org): Make this configurable */ + nmi_option = NMI_OFF; + if (nmi_option) { + debug("NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + debug("NMI sources disabled.\n"); + /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); + } + outb(reg8, 0x70); + + /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ + reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ + reg16 |= (3 << 0); /* Periodic SMI every 8s */ +#endif + pci_write_config16(dev, GEN_PMCON_1, reg16); + + /* Set the board's GPI routing. */ + ret = pch_gpi_routing(blob, node, dev); + if (ret) + return ret; + + pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + + writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node, + "intel,gpe0-enable", 0)); + writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node, + "intel,alt-gp-smi-enable", 0)); + + /* Set up power management block and determine sleep mode */ + reg32 = inl(pmbase + 0x04); /* PM1_CNT */ + reg32 &= ~(7 << 10); /* SLP_TYP */ + reg32 |= (1 << 0); /* SCI_EN */ + outl(reg32, pmbase + 0x04); + + /* Clear magic status bits to prevent unexpected wake */ + setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); + clrbits_le32(RCB_REG(0x3f02), 0xf); + + return 0; +} + +static void pch_rtc_init(pci_dev_t dev) +{ + int rtc_failed; + u8 reg8; + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(dev, GEN_PMCON_3, reg8); + } + debug("rtc_failed = 0x%x\n", rtc_failed); + +#if CONFIG_HAVE_ACPI_RESUME + /* Avoid clearing pending interrupts and resetting the RTC control + * register in the resume path because the Linux kernel relies on + * this to know if it should restart the RTC timerqueue if the wake + * was due to the RTC alarm. + */ + if (acpi_get_slp_type() == 3) + return; +#endif + /* TODO: Handle power failure */ + if (rtc_failed) + printf("RTC power failed\n"); + rtc_init(); +} + +/* CougarPoint PCH Power Management init */ +static void cpt_pm_init(pci_dev_t dev) +{ + debug("CougarPoint PM init\n"); + pci_write_config8(dev, 0xa9, 0x47); + setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); + + setbits_le32(RCB_REG(0x228c), 1 << 0); + setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); + setbits_le32(RCB_REG(0x0900), 1 << 14); + writel(0xc0388400, RCB_REG(0x2304)); + setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); + setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); + clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); + writel(0x050f0000, RCB_REG(0x3318)); + writel(0x04000000, RCB_REG(0x3324)); + setbits_le32(RCB_REG(0x3340), 0xfffff); + setbits_le32(RCB_REG(0x3344), 1 << 1); + + writel(0x0001c000, RCB_REG(0x3360)); + writel(0x00061100, RCB_REG(0x3368)); + writel(0x7f8fdfff, RCB_REG(0x3378)); + writel(0x000003fc, RCB_REG(0x337c)); + writel(0x00001000, RCB_REG(0x3388)); + writel(0x0001c000, RCB_REG(0x3390)); + writel(0x00000800, RCB_REG(0x33a0)); + writel(0x00001000, RCB_REG(0x33b0)); + writel(0x00093900, RCB_REG(0x33c0)); + writel(0x24653002, RCB_REG(0x33cc)); + writel(0x062108fe, RCB_REG(0x33d0)); + clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); + writel(0x01010000, RCB_REG(0x3a28)); + writel(0x01010404, RCB_REG(0x3a2c)); + writel(0x01041041, RCB_REG(0x3a80)); + clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); + setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */ + setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */ + writel(0x00000001, RCB_REG(0x3a6c)); + clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c); + clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); + writel(0, RCB_REG(0x33c8)); + setbits_le32(RCB_REG(0x21b0), 0xf); +} + +/* PantherPoint PCH Power Management init */ +static void ppt_pm_init(pci_dev_t dev) +{ + debug("PantherPoint PM init\n"); + pci_write_config8(dev, 0xa9, 0x47); + setbits_le32(RCB_REG(0x2238), 1 << 0); + setbits_le32(RCB_REG(0x228c), 1 << 0); + setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); + setbits_le16(RCB_REG(0x0900), 1 << 14); + writel(0xc03b8400, RCB_REG(0x2304)); + setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); + setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); + clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); + writel(0x054f0000, RCB_REG(0x3318)); + writel(0x04000000, RCB_REG(0x3324)); + setbits_le32(RCB_REG(0x3340), 0xfffff); + setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0)); + writel(0x0001c000, RCB_REG(0x3360)); + writel(0x00061100, RCB_REG(0x3368)); + writel(0x7f8fdfff, RCB_REG(0x3378)); + writel(0x000003fd, RCB_REG(0x337c)); + writel(0x00001000, RCB_REG(0x3388)); + writel(0x0001c000, RCB_REG(0x3390)); + writel(0x00000800, RCB_REG(0x33a0)); + writel(0x00001000, RCB_REG(0x33b0)); + writel(0x00093900, RCB_REG(0x33c0)); + writel(0x24653002, RCB_REG(0x33cc)); + writel(0x067388fe, RCB_REG(0x33d0)); + clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); + writel(0x01010000, RCB_REG(0x3a28)); + writel(0x01010404, RCB_REG(0x3a2c)); + writel(0x01040000, RCB_REG(0x3a80)); + clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); + /* SATA 2/3 disabled */ + setbits_le32(RCB_REG(0x3a84), 1 << 24); + /* SATA 4/5 disabled */ + setbits_le32(RCB_REG(0x3a88), 1 << 0); + writel(0x00000001, RCB_REG(0x3a6c)); + clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); + clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); + setbits_le32(RCB_REG(0x33a4), (1 << 0)); + writel(0, RCB_REG(0x33c8)); + setbits_le32(RCB_REG(0x21b0), 0xf); +} + +static void enable_hpet(void) +{ + /* Move HPET to default address 0xfed00000 and enable it */ + clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7); +} + +static void enable_clock_gating(pci_dev_t dev) +{ + u32 reg32; + u16 reg16; + + setbits_le32(RCB_REG(0x2234), 0xf); + + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 |= (1 << 2) | (1 << 11); + pci_write_config16(dev, GEN_PMCON_1, reg16); + + pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); + pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); + pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + + reg32 = readl(RCB_REG(CG)); + reg32 |= (1 << 31); + reg32 |= (1 << 29) | (1 << 28); + reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); + reg32 |= (1 << 16); + reg32 |= (1 << 17); + reg32 |= (1 << 18); + reg32 |= (1 << 22); + reg32 |= (1 << 23); + reg32 &= ~(1 << 20); + reg32 |= (1 << 19); + reg32 |= (1 << 0); + reg32 |= (0xf << 1); + writel(reg32, RCB_REG(CG)); + + setbits_le32(RCB_REG(0x38c0), 0x7); + setbits_le32(RCB_REG(0x36d4), 0x6680c004); + setbits_le32(RCB_REG(0x3564), 0x3); +} + +#if CONFIG_HAVE_SMI_HANDLER +static void pch_lock_smm(pci_dev_t dev) +{ +#if TEST_SMM_FLASH_LOCKDOWN + u8 reg8; +#endif + + if (acpi_slp_type != 3) { +#if ENABLE_ACPI_MODE_IN_COREBOOT + debug("Enabling ACPI via APMC:\n"); + outb(0xe1, 0xb2); /* Enable ACPI mode */ + debug("done.\n"); +#else + debug("Disabling ACPI via APMC:\n"); + outb(0x1e, 0xb2); /* Disable ACPI mode */ + debug("done.\n"); +#endif + } + + /* Don't allow evil boot loaders, kernels, or + * userspace applications to deceive us: + */ + smm_lock(); + +#if TEST_SMM_FLASH_LOCKDOWN + /* Now try this: */ + debug("Locking BIOS to RO... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", + (reg8 & 1) ? "rw" : "ro"); + reg8 &= ~(1 << 0); /* clear BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + reg8 |= (1 << 1); /* set BLE */ + pci_write_config8(dev, 0xdc, reg8); + debug("ok.\n"); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", + (reg8 & 1) ? "rw" : "ro"); + + debug("Writing:\n"); + writeb(0, 0xfff00000); + debug("Testing:\n"); + reg8 |= (1 << 0); /* set BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", + (reg8 & 1) ? "rw" : "ro"); + debug("Done.\n"); +#endif +} +#endif + +static void pch_disable_smm_only_flashing(pci_dev_t dev) +{ + u8 reg8; + + debug("Enabling BIOS updates outside of SMM... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 &= ~(1 << 5); + pci_write_config8(dev, 0xdc, reg8); +} + +static void pch_fixups(pci_dev_t dev) +{ + u8 gen_pmcon_2; + + /* Indicate DRAM init done for MRC S3 to know it can resume */ + gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); + gen_pmcon_2 |= (1 << 7); + pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + + /* Enable DMI ASPM in the PCH */ + clrbits_le32(RCB_REG(0x2304), 1 << 10); + setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10)); + setbits_le32(RCB_REG(0x21a8), 0x3); +} + int lpc_early_init(const void *blob, int node, pci_dev_t dev) { struct reg_info { @@ -22,7 +472,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) int count; int i; - count = fdtdec_get_int_array_count(blob, node, "gen-dec", + count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec", (u32 *)values, sizeof(values) / sizeof(u32)); if (count < 0) return -EINVAL; @@ -46,3 +496,74 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) return 0; } + +int lpc_init(struct pci_controller *hose, pci_dev_t dev) +{ + const void *blob = gd->fdt_blob; + int node; + + debug("pch: lpc_init\n"); + pci_write_bar32(hose, dev, 0, 0); + pci_write_bar32(hose, dev, 1, 0xff800000); + pci_write_bar32(hose, dev, 2, 0xfec00000); + pci_write_bar32(hose, dev, 3, 0x800); + pci_write_bar32(hose, dev, 4, 0x900); + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + if (node < 0) + return -ENOENT; + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + + /* IO APIC initialization. */ + pch_enable_apic(dev); + + pch_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + pch_pirq_init(blob, node, dev); + + /* Setup power options. */ + pch_power_options(blob, node, dev); + + /* Initialize power management */ + switch (pch_silicon_type()) { + case PCH_TYPE_CPT: /* CougarPoint */ + cpt_pm_init(dev); + break; + case PCH_TYPE_PPT: /* PantherPoint */ + ppt_pm_init(dev); + break; + default: + printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev), + PCI_FUNC(dev)); + return -ENOSYS; + } + + /* Initialize the real time clock. */ + pch_rtc_init(dev); + + /* Initialize the High Precision Event Timers, if present. */ + enable_hpet(); + + /* Initialize Clock Gating */ + enable_clock_gating(dev); + + pch_disable_smm_only_flashing(dev); + +#if CONFIG_HAVE_SMI_HANDLER + pch_lock_smm(dev); +#endif + + pch_fixups(dev); + + return 0; +} + +void lpc_enable(pci_dev_t dev) +{ + /* Enable PCH Display Port */ + writew(0x0010, RCB_REG(DISPBDF)); + setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); +} -- cgit v1.1 From b021e05535c3dabc07fbac2222db535d414110dc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:36 -0700 Subject: x86: dts: Move PCI peripherals into a pci node These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass --- arch/x86/dts/link.dts | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index 9329916..4520db5 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -163,21 +163,23 @@ }; }; - lpc { - compatible = "intel,lpc"; - #address-cells = <1>; - #size-cells = <1>; - gen-dec = <0x800 0xfc 0x900 0xfc>; - cros-ec@200 { - compatible = "google,cros-ec"; - reg = <0x204 1 0x200 1 0x880 0x80>; - - /* This describes the flash memory within the EC */ + pci { + lpc { + compatible = "intel,lpc"; #address-cells = <1>; #size-cells = <1>; - flash@8000000 { - reg = <0x08000000 0x20000>; - erase-value = <0xff>; + gen-dec = <0x800 0xfc 0x900 0xfc>; + cros-ec@200 { + compatible = "google,cros-ec"; + reg = <0x204 1 0x200 1 0x880 0x80>; + + /* Describes the flash memory within the EC */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0xff>; + }; }; }; }; -- cgit v1.1 From 05efc3961cf01916b32ef58a3965d46a11636e68 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:37 -0700 Subject: x86: dts: Add LPC settings for link Add some settings required to set up the LPC correctly. Signed-off-by: Simon Glass --- arch/x86/dts/link.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index 4520db5..28cef07 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -169,6 +169,14 @@ #address-cells = <1>; #size-cells = <1>; gen-dec = <0x800 0xfc 0x900 0xfc>; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; + intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b + 0x80 0x80 0x80 0x80>; + intel,gpi-routing = <0 0 0 0 0 0 0 2 + 1 0 0 0 0 0 0 0>; + /* Enable EC SMI source */ + intel,alt-gp-smi-enable = <0x0100>; + cros-ec@200 { compatible = "google,cros-ec"; reg = <0x204 1 0x200 1 0x880 0x80>; -- cgit v1.1 From 3ac839352db2fb464e1e6e6a4bc50f06fb29cdb0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:38 -0700 Subject: x86: ivybridge: Add SATA init Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 20 +++ arch/x86/cpu/ivybridge/sata.c | 225 ++++++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 + arch/x86/include/asm/arch-ivybridge/pch.h | 58 +++++++ 5 files changed, 306 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/sata.c (limited to 'arch') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 479e446..c6342cd 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -15,4 +15,5 @@ obj-y += microcode_intel.o obj-y += pch.o obj-y += pci.o obj-y += report_platform.o +obj-y += sata.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index be4db74..b54f5c7 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -88,18 +88,38 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) int bd82x6x_init_pci_devices(void) { + const void *blob = gd->fdt_blob; struct pci_controller *hose; + int sata_node; hose = pci_bus_to_hose(0); lpc_enable(PCH_LPC_DEV); lpc_init(hose, PCH_LPC_DEV); + sata_node = fdtdec_next_compatible(blob, 0, + COMPAT_INTEL_PANTHERPOINT_AHCI); + if (sata_node < 0) { + debug("%s: Cannot find SATA node\n", __func__); + return -EINVAL; + } + bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); return 0; } int bd82x6x_init(void) { + const void *blob = gd->fdt_blob; + int sata_node; + + sata_node = fdtdec_next_compatible(blob, 0, + COMPAT_INTEL_PANTHERPOINT_AHCI); + if (sata_node < 0) { + debug("%s: Cannot find SATA node\n", __func__); + return -EINVAL; + } + bd82x6x_pci_init(PCH_DEV); + bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); return 0; } diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c new file mode 100644 index 0000000..bbcd47d --- /dev/null +++ b/arch/x86/cpu/ivybridge/sata.c @@ -0,0 +1,225 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include + +static inline u32 sir_read(pci_dev_t dev, int idx) +{ + pci_write_config32(dev, SATA_SIRI, idx); + return pci_read_config32(dev, SATA_SIRD); +} + +static inline void sir_write(pci_dev_t dev, int idx, u32 value) +{ + pci_write_config32(dev, SATA_SIRI, idx); + pci_write_config32(dev, SATA_SIRD, value); +} + +static void common_sata_init(pci_dev_t dev, unsigned int port_map) +{ + u32 reg32; + u16 reg16; + + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* Port enable */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; + reg16 |= port_map; + pci_write_config16(dev, 0x92, reg16); + + /* SATA Initialization register */ + port_map &= 0xff; + pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); +} + +void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) +{ + unsigned int port_map, speed_support, port_tx; + struct pci_controller *hose = pci_bus_to_hose(0); + const char *mode; + u32 reg32; + u16 reg16; + + debug("SATA: Initializing...\n"); + + /* SATA configuration */ + port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); + speed_support = fdtdec_get_int(blob, node, + "sata_interface_speed_support", 0); + + /* Enable BARs */ + pci_write_config16(dev, PCI_COMMAND, 0x0007); + + mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); + if (!mode || !strcmp(mode, "ahci")) { + u32 abar; + + debug("SATA: Controller in AHCI mode\n"); + + /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0x0a); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); + + common_sata_init(dev, 0x8000 | port_map); + + /* Initialize AHCI memory-mapped space */ + abar = pci_read_bar32(hose, dev, 5); + debug("ABAR: %08X\n", abar); + /* CAP (HBA Capabilities) : enable power management */ + reg32 = readl(abar + 0x00); + reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ + reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ + /* Set ISS, if available */ + if (speed_support) { + reg32 &= ~0x00f00000; + reg32 |= (speed_support & 0x03) << 20; + } + writel(reg32, abar + 0x00); + /* PI (Ports implemented) */ + writel(port_map, abar + 0x0c); + (void) readl(abar + 0x0c); /* Read back 1 */ + (void) readl(abar + 0x0c); /* Read back 2 */ + /* CAP2 (HBA Capabilities Extended)*/ + reg32 = readl(abar + 0x24); + reg32 &= ~0x00000002; + writel(reg32, abar + 0x24); + /* VSP (Vendor Specific Register */ + reg32 = readl(abar + 0xa0); + reg32 &= ~0x00000005; + writel(reg32, abar + 0xa0); + } else if (!strcmp(mode, "combined")) { + debug("SATA: Controller in combined mode\n"); + + /* No AHCI: clear AHCI base */ + pci_write_bar32(hose, dev, 5, 0x00000000); + /* And without AHCI BAR no memory decoding */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + pci_write_config8(dev, 0x09, 0x80); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + + common_sata_init(dev, port_map); + } else { + debug("SATA: Controller in plain-ide mode\n"); + + /* No AHCI: clear AHCI base */ + pci_write_bar32(hose, dev, 5, 0x00000000); + + /* And without AHCI BAR no memory decoding */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* + * Native mode capable on both primary and secondary (0xa) + * OR'ed with enabled (0x50) = 0xf + */ + pci_write_config8(dev, 0x09, 0x8f); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0xff); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_SITRE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); + + common_sata_init(dev, port_map); + } + + /* Set Gen3 Transmitter settings if needed */ + port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); + if (port_tx) + pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx); + + port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); + if (port_tx) + pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx); + + /* Additional Programming Requirements */ + sir_write(dev, 0x04, 0x00001600); + sir_write(dev, 0x28, 0xa0000033); + reg32 = sir_read(dev, 0x54); + reg32 &= 0xff000000; + reg32 |= 0x5555aa; + sir_write(dev, 0x54, reg32); + sir_write(dev, 0x64, 0xcccc8484); + reg32 = sir_read(dev, 0x68); + reg32 &= 0xffff0000; + reg32 |= 0xcccc; + sir_write(dev, 0x68, reg32); + reg32 = sir_read(dev, 0x78); + reg32 &= 0x0000ffff; + reg32 |= 0x88880000; + sir_write(dev, 0x78, reg32); + sir_write(dev, 0x84, 0x001c7000); + sir_write(dev, 0x88, 0x88338822); + sir_write(dev, 0xa0, 0x001c7000); + sir_write(dev, 0xc4, 0x0c0c0c0c); + sir_write(dev, 0xc8, 0x0c0c0c0c); + sir_write(dev, 0xd4, 0x10000000); + + pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); + pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); +} + +void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node) +{ + unsigned port_map; + const char *mode; + u16 map = 0; + + /* + * Set SATA controller mode early so the resource allocator can + * properly assign IO/Memory resources for the controller. + */ + mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); + if (mode && !strcmp(mode, "ahci")) + map = 0x0060; + port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); + + map |= (port_map ^ 0x3f) << 8; + pci_write_config16(dev, 0x90, map); +} diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index e02520c..644755f 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -7,6 +7,8 @@ #ifndef _ASM_ARCH_BD82X6X_H #define _ASM_ARCH_BD82X6X_H +void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); +void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); void bd82x6x_pci_init(pci_dev_t dev); int bd82x6x_init_pci_devices(void); int bd82x6x_init(void); diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index b3ec7c5..21df083 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -122,6 +122,64 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) +/* PCI Configuration Space (D31:F1): IDE */ +#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) +#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2) +#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5) + +#define INTR_LN 0x3c +#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) +#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ + +#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) + +#define IDE_SDMA_TIM 0x4a + +#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) + +#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ +#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ +#define SATA_SP 0xd0 /* Scratchpad */ + +/* SATA IOBP Registers */ +#define SATA_IOBP_SP0G3IR 0xea000151 +#define SATA_IOBP_SP1G3IR 0xea000051 + /* PCI Configuration Space (D31:F3): SMBus */ #define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3) #define SMB_BASE 0x20 -- cgit v1.1 From 4896f4acc8b67155026cd1095b5dcdb22e70445a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:39 -0700 Subject: x86: dts: Add SATA settings for link Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass --- arch/x86/dts/link.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index 28cef07..d3c94e0 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -164,6 +164,13 @@ }; pci { + sata { + compatible = "intel,pantherpoint-ahci"; + intel,sata-mode = "ahci"; + intel,sata-port-map = <1>; + intel,sata-port0-gen3-tx = <0x00880a7f>; + }; + lpc { compatible = "intel,lpc"; #address-cells = <1>; -- cgit v1.1 From 9baeca4b8936edc01e1c748a6f119915acb100c4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:40 -0700 Subject: x86: ivybridge: Set up EHCI USB Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 2 ++ arch/x86/cpu/ivybridge/usb_ehci.c | 29 +++++++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 + 4 files changed, 33 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c (limited to 'arch') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index c6342cd..4a00757 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -17,3 +17,4 @@ obj-y += pci.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o +obj-y += usb_ehci.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index b54f5c7..1fcbc28 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -102,6 +102,8 @@ int bd82x6x_init_pci_devices(void) return -EINVAL; } bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); + bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); + bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); return 0; } diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c new file mode 100644 index 0000000..291c971 --- /dev/null +++ b/arch/x86/cpu/ivybridge/usb_ehci.c @@ -0,0 +1,29 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +void bd82x6x_usb_ehci_init(pci_dev_t dev) +{ + u32 reg32; + + /* Disable Wake on Disconnect in RMH */ + reg32 = readl(RCB_REG(0x35b0)); + reg32 |= 0x22; + writel(reg32, RCB_REG(0x35b0)); + + debug("EHCI: Setting up controller.. "); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + /* reg32 |= PCI_COMMAND_SERR; */ + pci_write_config32(dev, PCI_COMMAND, reg32); + + debug("done.\n"); +} diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 644755f..2e6a079 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -10,6 +10,7 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); void bd82x6x_pci_init(pci_dev_t dev); +void bd82x6x_usb_ehci_init(pci_dev_t dev); int bd82x6x_init_pci_devices(void); int bd82x6x_init(void); -- cgit v1.1 From a6d4c453069303c3d1a499d2282f423b35c8f3b0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:42 -0700 Subject: x86: ivybridge: Set up XHCI USB Add init for XHCI so that high-speed USB can be used. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/usb_xhci.c | 32 +++++++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 + 3 files changed, 34 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/usb_xhci.c (limited to 'arch') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 4a00757..aedc395 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -18,3 +18,4 @@ obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o obj-y += usb_ehci.o +obj-y += usb_xhci.o diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c new file mode 100644 index 0000000..4a32a7e --- /dev/null +++ b/arch/x86/cpu/ivybridge/usb_xhci.c @@ -0,0 +1,32 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +void bd82x6x_usb_xhci_init(pci_dev_t dev) +{ + u32 reg32; + + debug("XHCI: Setting up controller.. "); + + /* lock overcurrent map */ + reg32 = pci_read_config32(dev, 0x44); + reg32 |= 1; + pci_write_config32(dev, 0x44, reg32); + + /* Enable clock gating */ + reg32 = pci_read_config32(dev, 0x40); + reg32 &= ~((1 << 20) | (1 << 21)); + reg32 |= (1 << 19) | (1 << 18) | (1 << 17); + reg32 |= (1 << 10) | (1 << 9) | (1 << 8); + reg32 |= (1 << 31); /* lock */ + pci_write_config32(dev, 0x40, reg32); + + debug("done.\n"); +} diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 2e6a079..6454dd9 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -11,6 +11,7 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); void bd82x6x_pci_init(pci_dev_t dev); void bd82x6x_usb_ehci_init(pci_dev_t dev); +void bd82x6x_usb_xhci_init(pci_dev_t dev); int bd82x6x_init_pci_devices(void); int bd82x6x_init(void); -- cgit v1.1 From 18739e2ccc66e13dba10a7cb4578910daf455f01 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:43 -0700 Subject: x86: Add Intel speedstep and turbo mode code Intel chips have a turbo mode where they can run faster for a short period until they reach thermal limits. Add code to adjust and query this feature. Signed-off-by: Simon Glass --- arch/x86/cpu/Makefile | 1 + arch/x86/cpu/turbo.c | 98 ++++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/speedstep.h | 89 ++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/turbo.h | 31 +++++++++++++ 4 files changed, 219 insertions(+) create mode 100644 arch/x86/cpu/turbo.c create mode 100644 arch/x86/include/asm/speedstep.h create mode 100644 arch/x86/include/asm/turbo.h (limited to 'arch') diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 818969f..3839262 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_PCI) += pci.o +obj-y += turbo.o diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c new file mode 100644 index 0000000..254d0de --- /dev/null +++ b/arch/x86/cpu/turbo.c @@ -0,0 +1,98 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2011 The Chromium Authors. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED +static inline int get_global_turbo_state(void) +{ + return TURBO_UNKNOWN; +} + +static inline void set_global_turbo_state(int state) +{ +} +#else +static int g_turbo_state = TURBO_UNKNOWN; + +static inline int get_global_turbo_state(void) +{ + return g_turbo_state; +} + +static inline void set_global_turbo_state(int state) +{ + g_turbo_state = state; +} +#endif + +static const char *const turbo_state_desc[] = { + [TURBO_UNKNOWN] = "unknown", + [TURBO_UNAVAILABLE] = "unavailable", + [TURBO_DISABLED] = "available but hidden", + [TURBO_ENABLED] = "available and visible" +}; + +/* + * Determine the current state of Turbo and cache it for later. + * Turbo is a package level config so it does not need to be + * enabled on every core. + */ +int turbo_get_state(void) +{ + struct cpuid_result cpuid_regs; + int turbo_en, turbo_cap; + msr_t msr; + int turbo_state = get_global_turbo_state(); + + /* Return cached state if available */ + if (turbo_state != TURBO_UNKNOWN) + return turbo_state; + + cpuid_regs = cpuid(CPUID_LEAF_PM); + turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); + + msr = msr_read(MSR_IA32_MISC_ENABLES); + turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); + + if (!turbo_cap && turbo_en) { + /* Unavailable */ + turbo_state = TURBO_UNAVAILABLE; + } else if (!turbo_cap && !turbo_en) { + /* Available but disabled */ + turbo_state = TURBO_DISABLED; + } else if (turbo_cap && turbo_en) { + /* Available */ + turbo_state = TURBO_ENABLED; + } + + set_global_turbo_state(turbo_state); + debug("Turbo is %s\n", turbo_state_desc[turbo_state]); + return turbo_state; +} + +void turbo_enable(void) +{ + msr_t msr; + + /* Only possible if turbo is available but hidden */ + if (turbo_get_state() == TURBO_DISABLED) { + /* Clear Turbo Disable bit in Misc Enables */ + msr = msr_read(MSR_IA32_MISC_ENABLES); + msr.hi &= ~H_MISC_DISABLE_TURBO; + msr_write(MSR_IA32_MISC_ENABLES, msr); + + /* Update cached turbo state */ + set_global_turbo_state(TURBO_ENABLED); + debug("Turbo has been enabled\n"); + } +} diff --git a/arch/x86/include/asm/speedstep.h b/arch/x86/include/asm/speedstep.h new file mode 100644 index 0000000..b938b86 --- /dev/null +++ b/arch/x86/include/asm/speedstep.h @@ -0,0 +1,89 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_SPEEDSTEP_H +#define _ASM_SPEEDSTEP_H + +/* Magic value used to locate speedstep configuration in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + +/* MWAIT coordination I/O base address. This must match + * the \_PR_.CPU0 PM base address. + */ +#define PMB0_BASE 0x510 + +/* PMB1: I/O port that triggers SMI once cores are in the same state. + * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] + */ +#define PMB1_BASE 0x800 + +struct sst_state { + uint8_t dynfsb:1; /* whether this is SLFM */ + uint8_t nonint:1; /* add .5 to ratio */ + uint8_t ratio:6; + uint8_t vid; + uint8_t is_turbo; + uint8_t is_slfm; + uint32_t power; +}; +#define SPEEDSTEP_RATIO_SHIFT 8 +#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) +#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) +#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_VID_MASK 0x3f +#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \ + 0, /* dynfsb won't be read. */ \ + ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ + (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ + >> SPEEDSTEP_RATIO_SHIFT), \ + (val & mask) & SPEEDSTEP_VID_MASK, \ + 0, /* not turbo by default */ \ + 0, /* not slfm by default */ \ + 0 /* power is hardcoded in software. */ \ + }) +#define SPEEDSTEP_ENCODE_STATE(state) ( \ + ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ + ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ + ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ + ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) +#define SPEEDSTEP_DOUBLE_RATIO(state) ( \ + ((uint8_t)(state).ratio * 2) + (state).nonint) + +struct sst_params { + struct sst_state slfm; + struct sst_state min; + struct sst_state max; + struct sst_state turbo; +}; + +/* Looking at core2's spec, the highest normal bus ratio for an eist enabled + processor is 14, the lowest is always 6. This makes 5 states with the + minimal step width of 2. With turbo mode and super LFM we have at most 7. */ +#define SPEEDSTEP_MAX_NORMAL_STATES 5 +#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) +struct sst_table { + /* Table of p-states for EMTTM and ACPI by decreasing performance. */ + struct sst_state states[SPEEDSTEP_MAX_STATES]; + int num_states; +}; + +void speedstep_gen_pstates(struct sst_table *); + +#define SPEEDSTEP_MAX_POWER_YONAH 31000 +#define SPEEDSTEP_MIN_POWER_YONAH 13100 +#define SPEEDSTEP_MAX_POWER_MEROM 35000 +#define SPEEDSTEP_MIN_POWER_MEROM 25000 +#define SPEEDSTEP_SLFM_POWER_MEROM 12000 +#define SPEEDSTEP_MAX_POWER_PENRYN 35000 +#define SPEEDSTEP_MIN_POWER_PENRYN 15000 +#define SPEEDSTEP_SLFM_POWER_PENRYN 12000 + +#endif diff --git a/arch/x86/include/asm/turbo.h b/arch/x86/include/asm/turbo.h new file mode 100644 index 0000000..bb0d4b4 --- /dev/null +++ b/arch/x86/include/asm/turbo.h @@ -0,0 +1,31 @@ +/* + * From coreboot file of the same name + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_TURBO_H +#define _ASM_TURBO_H + +#define CPUID_LEAF_PM 6 +#define PM_CAP_TURBO_MODE (1 << 1) + +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define H_MISC_DISABLE_TURBO (1 << 6) + +enum { + TURBO_UNKNOWN, + TURBO_UNAVAILABLE, + TURBO_DISABLED, + TURBO_ENABLED, +}; + +/* Return current turbo state */ +int turbo_get_state(void); + +/* Enable turbo */ +void turbo_enable(void); + +#endif -- cgit v1.1 From 4372a9eca5561ec21277b616b5223cf23ab526ca Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 20 Nov 2014 16:10:49 +0800 Subject: x86: Call cpu_init_interrupts() from interrupt_init() Currently cpu_init_interrupts() is called from cpu_init_r() to setup the interrupt and exception of the cpu core, but at that time the i8259 has not been initialized to mask all the irqs and remap the master i8259 interrupt vector base, so the whole system is at risk of being interrupted, and if interrupted, wrong interrupt/exception message is shown. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass --- arch/x86/cpu/cpu.c | 2 -- arch/x86/lib/pcat_interrupts.c | 3 +++ 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index b391b7a..ac25392 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -322,8 +322,6 @@ int x86_cpu_init_f(void) int x86_cpu_init_r(void) { - /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts(); return 0; } int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c index 2dc2fbd..f388db2 100644 --- a/arch/x86/lib/pcat_interrupts.c +++ b/arch/x86/lib/pcat_interrupts.c @@ -65,6 +65,9 @@ int interrupt_init(void) /* Interrupt 9 should be level triggered (SCI). The OS might do this */ configure_irq_trigger(9, true); + /* Initialize core interrupt and exception functionality of CPU */ + cpu_init_interrupts(); + enable_interrupts(); return 0; -- cgit v1.1 From a549f7497b4d719d37e4a20378c81c1b29bf0404 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 20 Nov 2014 16:11:00 +0800 Subject: x86: Remove cpu_init_r() for x86 Since cpu_init_interrupts() was moved out of cpu_init_r(), it is useless to keep cpu_init_r() for x86, thus remove it. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass --- arch/x86/cpu/cpu.c | 6 ------ arch/x86/include/asm/u-boot-x86.h | 2 -- 2 files changed, 8 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index ac25392..cf421fa 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -320,12 +320,6 @@ int x86_cpu_init_f(void) return 0; } -int x86_cpu_init_r(void) -{ - return 0; -} -int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); - void x86_enable_caches(void) { unsigned long cr0; diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 98217dd..36145cb 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -10,8 +10,6 @@ /* cpu/.../cpu.c */ int arch_cpu_init(void); -int x86_cpu_init_r(void); -int cpu_init_r(void); int x86_cpu_init_f(void); int cpu_init_f(void); void init_gd(gd_t *id, u64 *gdt_addr); -- cgit v1.1 From 1dae2e0eb660553fd18870b53e4c43bd56414e3b Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 20 Nov 2014 16:11:16 +0800 Subject: x86: Refactor interrupt_init() Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to i8259_init() and create a new interrupt_init() in arch/x86/cpu/interrupt.c to call i8259_init() followed by a call to cpu_init_interrupts(). Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass --- arch/x86/cpu/interrupts.c | 26 ++++++++++++++++++++------ arch/x86/include/asm/i8259.h | 2 ++ arch/x86/lib/pcat_interrupts.c | 9 +-------- 3 files changed, 23 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 51e2c59..ea03724 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -20,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -128,9 +129,6 @@ int cpu_init_interrupts(void) int irq_entry_size = irq_1 - irq_0; void *irq_entry = (void *)irq_0; - /* Just in case... */ - disable_interrupts(); - /* Setup the IDT */ for (i = 0; i < 256; i++) { idt[i].access = 0x8e; @@ -146,9 +144,6 @@ int cpu_init_interrupts(void) load_idt(&idt_ptr); - /* It is now safe to enable interrupts */ - enable_interrupts(); - return 0; } @@ -172,6 +167,25 @@ int disable_interrupts(void) return flags & X86_EFLAGS_IF; } +int interrupt_init(void) +{ + /* Just in case... */ + disable_interrupts(); + +#ifdef CONFIG_SYS_PCAT_INTERRUPTS + /* Initialize the master/slave i8259 pic */ + i8259_init(); +#endif + + /* Initialize core interrupt and exception functionality of CPU */ + cpu_init_interrupts(); + + /* It is now safe to enable interrupts */ + enable_interrupts(); + + return 0; +} + /* IRQ Low-Level Service Routine */ void irq_llsr(struct irq_regs *regs) { diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index 73113f9..bc4033b 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -69,4 +69,6 @@ #define ICW4_AEOI 0x02 /* Automatic EOI Mode */ #define ICW4_PM 0x01 /* Microprocessor Mode */ +int i8259_init(void); + #endif diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c index f388db2..a9af87e 100644 --- a/arch/x86/lib/pcat_interrupts.c +++ b/arch/x86/lib/pcat_interrupts.c @@ -24,12 +24,10 @@ #error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined" #endif -int interrupt_init(void) +int i8259_init(void) { u8 i; - disable_interrupts(); - /* Mask all interrupts */ outb(0xff, MASTER_PIC + IMR); outb(0xff, SLAVE_PIC + IMR); @@ -65,11 +63,6 @@ int interrupt_init(void) /* Interrupt 9 should be level triggered (SCI). The OS might do this */ configure_irq_trigger(9, true); - /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts(); - - enable_interrupts(); - return 0; } -- cgit v1.1 From b636dd1079fcdd55a38412afacb2be91a82cce1e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 24 Nov 2014 21:18:14 -0700 Subject: x86: Drop old CONFIG_INTEL_CORE_ARCH code This is no-longer used, so drop it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/interrupts.c | 28 ---------------------------- 1 file changed, 28 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index ea03724..a21d2a6 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -617,31 +617,3 @@ asm(".globl irq_common_entry\n" \ DECLARE_INTERRUPT(253) \ DECLARE_INTERRUPT(254) \ DECLARE_INTERRUPT(255)); - -#if defined(CONFIG_INTEL_CORE_ARCH) -/* - * Get the number of CPU time counter ticks since it was read first time after - * restart. This yields a free running counter guaranteed to take almost 6 - * years to wrap around even at 100GHz clock rate. - */ -u64 get_ticks(void) -{ - u64 now_tick = rdtsc(); - - if (!gd->arch.tsc_base) - gd->arch.tsc_base = now_tick; - - return now_tick - gd->arch.tsc_base; -} - -#define PLATFORM_INFO_MSR 0xce - -unsigned long get_tbclk(void) -{ - u32 ratio; - u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); - - ratio = (platform_info >> 8) & 0xff; - return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */ -} -#endif -- cgit v1.1 From 0c9075e9ad21caa43c524288d7def9e8b081fa11 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 24 Nov 2014 21:18:15 -0700 Subject: x86: Add LAPIC setup code Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/Makefile | 1 + arch/x86/cpu/lapic.c | 57 ++++++++++++++++++++ arch/x86/include/asm/lapic.h | 124 ++++++++++++++++++++++++++++++++++++++++++- arch/x86/include/asm/post.h | 1 + 4 files changed, 181 insertions(+), 2 deletions(-) create mode 100644 arch/x86/cpu/lapic.c (limited to 'arch') diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 3839262..7f09db5 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -15,5 +15,6 @@ obj-y += interrupts.o cpu.o call64.o obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ +obj-y += lapic.o obj-$(CONFIG_PCI) += pci.o obj-y += turbo.o diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c new file mode 100644 index 0000000..4690603 --- /dev/null +++ b/arch/x86/cpu/lapic.c @@ -0,0 +1,57 @@ +/* + * From coreboot file of same name + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +void lapic_setup(void) +{ +#if NEED_LAPIC == 1 + /* Only Pentium Pro and later have those MSR stuff */ + debug("Setting up local apic: "); + + /* Enable the local apic */ + enable_lapic(); + + /* + * Set Task Priority to 'accept all'. + */ + lapic_write_around(LAPIC_TASKPRI, + lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK); + + /* Put the local apic in virtual wire mode */ + lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) & + ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE); + lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | + LAPIC_DELIVERY_MODE_MASK)) | + (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | + LAPIC_DELIVERY_MODE_EXTINT)); + lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | + LAPIC_DELIVERY_MODE_MASK)) | + (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | + LAPIC_DELIVERY_MODE_NMI)); + + debug("apic_id: 0x%02lx, ", lapicid()); +#else /* !NEED_LLAPIC */ + /* Only Pentium Pro and later have those MSR stuff */ + debug("Disabling local apic: "); + disable_lapic(); +#endif /* !NEED_LAPIC */ + debug("done.\n"); + post_code(POST_LAPIC); +} diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h index 948e643..0a7f443 100644 --- a/arch/x86/include/asm/lapic.h +++ b/arch/x86/include/asm/lapic.h @@ -14,6 +14,13 @@ #include #include +/* See if I need to initialize the local apic */ +#if CONFIG_SMP || CONFIG_IOAPIC +# define NEED_LAPIC 1 +#else +# define NEED_LAPIC 0 +#endif + static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg) { @@ -37,8 +44,9 @@ static inline void enable_lapic(void) msr = msr_read(LAPIC_BASE_MSR); msr.hi &= 0xffffff00; - msr.lo &= 0x000007ff; - msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11); + msr.lo |= LAPIC_BASE_MSR_ENABLE; + msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; + msr.lo |= LAPIC_DEFAULT_BASE; msr_write(LAPIC_BASE_MSR, msr); } @@ -56,4 +64,116 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) return lapic_read(LAPIC_ID) >> 24; } +#if !CONFIG_AP_IN_SIPI_WAIT +/* If we need to go back to sipi wait, we use the long non-inlined version of + * this function in lapic_cpu_init.c + */ +static inline __attribute__((always_inline)) void stop_this_cpu(void) +{ + /* Called by an AP when it is ready to halt and wait for a new task */ + for (;;) + cpu_hlt(); +} +#else +void stop_this_cpu(void); +#endif + +#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ + sizeof(*(ptr)))) + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +/* + * Note: no "lock" prefix even on SMP: xchg always implies lock anyway + * Note 2: xchg has side effect, so that attribute volatile is necessary, + * but generally the primitive is invalid, *ptr is output argument. --ANK + */ +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + switch (size) { + case 1: + __asm__ __volatile__("xchgb %b0,%1" + : "=q" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + case 2: + __asm__ __volatile__("xchgw %w0,%1" + : "=r" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + case 4: + __asm__ __volatile__("xchgl %0,%1" + : "=r" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + } + + return x; +} + +static inline void lapic_write_atomic(unsigned long reg, unsigned long v) +{ + (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v); +} + + +#ifdef X86_GOOD_APIC +# define FORCE_READ_AROUND_WRITE 0 +# define lapic_read_around(x) lapic_read(x) +# define lapic_write_around(x, y) lapic_write((x), (y)) +#else +# define FORCE_READ_AROUND_WRITE 1 +# define lapic_read_around(x) lapic_read(x) +# define lapic_write_around(x, y) lapic_write_atomic((x), (y)) +#endif + +static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue) +{ + int timeout; + unsigned long status; + int result; + lapic_wait_icr_idle(); + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); + timeout = 0; + do { + status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; + } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); + + result = -1; + if (status == LAPIC_ICR_RR_VALID) { + *pvalue = lapic_read(LAPIC_RRR); + result = 0; + } + return result; +} + + +void lapic_setup(void); + +#if CONFIG_SMP +struct device; +int start_cpu(struct device *cpu); +#endif /* CONFIG_SMP */ + +int boot_cpu(void); + +/** + * struct x86_cpu_priv - Information about a single CPU + * + * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is + * just a number representing the CPU core + * + * TODO: Move this to driver model once lifecycle is understood + */ +struct x86_cpu_priv { + int apic_id; + int start_err; +}; + #endif diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h index ce68839..6d2ae5d 100644 --- a/arch/x86/include/asm/post.h +++ b/arch/x86/include/asm/post.h @@ -30,6 +30,7 @@ #define POST_PRE_MRC 0x2e #define POST_MRC 0x2f #define POST_DRAM 0x2f +#define POST_LAPIC 0x30 #define POST_RAM_FAILURE 0xea -- cgit v1.1 From bb80be391693a868c2114d1a9505c45dce7a3607 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 24 Nov 2014 21:18:16 -0700 Subject: x86: Add init for model 206AX CPU Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 6 + arch/x86/cpu/ivybridge/model_206ax.c | 514 ++++++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 3 + arch/x86/include/asm/msr-index.h | 2 + 5 files changed, 526 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/model_206ax.c (limited to 'arch') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index aedc395..95491b5 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -11,6 +11,7 @@ obj-y += early_init.o obj-y += early_me.o obj-y += lpc.o obj-y += me_status.o +obj-y += model_206ax.o obj-y += microcode_intel.o obj-y += pch.o obj-y += pci.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 1fcbc28..1a3c036 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -90,6 +90,7 @@ int bd82x6x_init_pci_devices(void) { const void *blob = gd->fdt_blob; struct pci_controller *hose; + struct x86_cpu_priv *cpu; int sata_node; hose = pci_bus_to_hose(0); @@ -105,6 +106,11 @@ int bd82x6x_init_pci_devices(void) bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); + cpu = calloc(1, sizeof(*cpu)); + if (!cpu) + return -ENOMEM; + model_206ax_init(cpu); + return 0; } diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c new file mode 100644 index 0000000..11dc625 --- /dev/null +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -0,0 +1,514 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void enable_vmx(void) +{ + struct cpuid_result regs; +#ifdef CONFIG_ENABLE_VMX + int enable = true; +#else + int enable = false; +#endif + msr_t msr; + + regs = cpuid(1); + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) + return; + + msr = msr_read(MSR_IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + debug("VMX is locked, so %s will do nothing\n", __func__); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + /* The IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = 0; + msr.lo = 0; + + debug("%s VMX\n", enable ? "Enabling" : "Disabling"); + + /* + * Even though the Intel manual says you must set the lock bit in + * addition to the VMX bit in order for VMX to work, it is incorrect. + * Thus we leave it unlocked for the OS to manage things itself. + * This is good for a few reasons: + * - No need to reflash the bios just to toggle the lock bit. + * - The VMX bits really really should match each other across cores, + * so hard locking it on one while another has the opposite setting + * can easily lead to crashes as code using VMX migrates between + * them. + * - Vendors that want to "upsell" from a bios that disables+locks to + * one that doesn't is sleazy. + * By leaving this to the OS (e.g. Linux), people can do exactly what + * they want on the fly, and do it correctly (e.g. across multiple + * cores). + */ + if (enable) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + msr_write(MSR_IA32_FEATURE_CONTROL, msr); +} + +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + +int cpu_config_tdp_levels(void) +{ + struct cpuid_result result; + msr_t platform_info; + + /* Minimum CPU revision */ + result = cpuid(1); + if (result.eax < IVB_CONFIG_TDP_MIN_CPUID) + return 0; + + /* Bits 34:33 indicate how many levels supported */ + platform_info = msr_read(MSR_PLATFORM_INFO); + return (platform_info.hi >> 1) & 3; +} + +/* + * Configure processor power limits if possible + * This must be done AFTER set of BIOS_RESET_CPL + */ +void set_power_limits(u8 power_limit_1_time) +{ + msr_t msr = msr_read(MSR_PLATFORM_INFO); + msr_t limit; + unsigned power_unit; + unsigned tdp, min_power, max_power, max_time; + u8 power_limit_1_val; + + if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) + return; + + if (!(msr.lo & PLATFORM_INFO_SET_TDP)) + return; + + /* Get units */ + msr = msr_read(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + + /* Get power defaults for this SKU */ + msr = msr_read(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + min_power = (msr.lo >> 16) & 0x7fff; + max_power = msr.hi & 0x7fff; + max_time = (msr.hi >> 16) & 0x7f; + + debug("CPU TDP: %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit to 1.25 * TDP */ + limit.hi = 0; + limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Power limit 2 time is only programmable on SNB EP/EX */ + + msr_write(MSR_PKG_POWER_LIMIT, limit); + + /* Use nominal TDP values for CPUs with configurable TDP */ + if (cpu_config_tdp_levels()) { + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + limit.hi = 0; + limit.lo = msr.lo & 0xff; + msr_write(MSR_TURBO_ACTIVATION_RATIO, limit); + } +} + +static void configure_c_states(void) +{ + struct cpuid_result result; + msr_t msr; + + msr = msr_read(MSR_PMG_CST_CONFIG_CTL); + msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */ + msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */ + msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */ + msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */ + msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */ + msr.lo |= 7; /* No package C-state limit */ + msr_write(MSR_PMG_CST_CONFIG_CTL, msr); + + msr = msr_read(MSR_PMG_IO_CAPTURE_ADR); + msr.lo &= ~0x7ffff; + msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */ + msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */ + msr_write(MSR_PMG_IO_CAPTURE_ADR, msr); + + msr = msr_read(MSR_MISC_PWR_MGMT); + msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */ + msr_write(MSR_MISC_PWR_MGMT, msr); + + msr = msr_read(MSR_POWER_CTL); + msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */ + msr.lo |= (1 << 1); /* C1E Enable */ + msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */ + msr_write(MSR_POWER_CTL, msr); + + /* C3 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; + msr_write(MSR_PKGC3_IRTL, msr); + + /* C6 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; + msr_write(MSR_PKGC6_IRTL, msr); + + /* C7 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; + msr_write(MSR_PKGC7_IRTL, msr); + + /* Primary Plane Current Limit */ + msr = msr_read(MSR_PP0_CURRENT_CONFIG); + msr.lo &= ~0x1fff; + msr.lo |= PP0_CURRENT_LIMIT; + msr_write(MSR_PP0_CURRENT_CONFIG, msr); + + /* Secondary Plane Current Limit */ + msr = msr_read(MSR_PP1_CURRENT_CONFIG); + msr.lo &= ~0x1fff; + result = cpuid(1); + if (result.eax >= 0x30600) + msr.lo |= PP1_CURRENT_LIMIT_IVB; + else + msr.lo |= PP1_CURRENT_LIMIT_SNB; + msr_write(MSR_PP1_CURRENT_CONFIG, msr); +} + +static int configure_thermal_target(void) +{ + int tcc_offset; + msr_t msr; + int node; + + /* Find pointer to CPU configuration */ + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_INTEL_MODEL_206AX); + if (node < 0) + return -ENOENT; + tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0); + + /* Set TCC activaiton offset if supported */ + msr = msr_read(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && tcc_offset) { + msr = msr_read(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (tcc_offset & 0xf) << 24; + msr_write(MSR_TEMPERATURE_TARGET, msr); + } + + return 0; +} + +static void configure_misc(void) +{ + msr_t msr; + + msr = msr_read(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr_write(IA32_MISC_ENABLE, msr); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + msr_write(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = msr_read(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + msr_write(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + struct cpuid_result cpuid_regs; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + cpuid_regs = cpuid(1); + if (cpuid_regs.ecx & (1 << 18)) { + msr = msr_read(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + msr_write(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void set_max_ratio(void) +{ + msr_t msr, perf_ctl; + + perf_ctl.hi = 0; + + /* Check for configurable TDP option */ + if (cpu_config_tdp_levels()) { + /* Set to nominal TDP ratio */ + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = msr_read(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + msr_write(IA32_PERF_CTL, perf_ctl); + + debug("model_x06ax: frequency set to %d\n", + ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); +} + +static void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + + /* Energy Policy is bits 3:0 */ + msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr); + + debug("model_x06ax: energy policy set to %u\n", policy); +} + +static void configure_mca(void) +{ + msr_t msr; + int i; + + msr.lo = 0; + msr.hi = 0; + /* This should only be done on a cold boot */ + for (i = 0; i < 7; i++) + msr_write(IA32_MC0_STATUS + (i * 4), msr); +} + +#if CONFIG_USBDEBUG +static unsigned ehci_debug_addr; +#endif + +/* + * Initialize any extra cores/threads in this package. + */ +static int intel_cores_init(struct x86_cpu_priv *cpu) +{ + struct cpuid_result result; + unsigned threads_per_package, threads_per_core, i; + + /* Logical processors (threads) per core */ + result = cpuid_ext(0xb, 0); + threads_per_core = result.ebx & 0xffff; + + /* Logical processors (threads) per package */ + result = cpuid_ext(0xb, 1); + threads_per_package = result.ebx & 0xffff; + + debug("CPU: %u has %u cores, %u threads per core\n", + cpu->apic_id, threads_per_package / threads_per_core, + threads_per_core); + + for (i = 1; i < threads_per_package; ++i) { + struct x86_cpu_priv *new_cpu; + + new_cpu = calloc(1, sizeof(*new_cpu)); + if (!new_cpu) + return -ENOMEM; + + new_cpu->apic_id = cpu->apic_id + i; + + /* Update APIC ID if no hyperthreading */ + if (threads_per_core == 1) + new_cpu->apic_id <<= 1; + + debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id); + +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + /* Start the new cpu */ + if (!start_cpu(new_cpu)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU %u would not start!\n", + new_cpu->apic_id); + new_cpu->start_err = 1; + } +#endif + } + + return 0; +} + +int model_206ax_init(struct x86_cpu_priv *cpu) +{ + int ret; + + /* Clear out pending MCEs */ + configure_mca(); + +#if CONFIG_USBDEBUG + /* Is this caution really needed? */ + if (!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + + /* Setup MTRRs based on physical address size */ +#if 0 /* TODO: Implement this */ + struct cpuid_result cpuid_regs; + + cpuid_regs = cpuid(0x80000008); + x86_setup_fixed_mtrrs(); + x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_mtrr_check(); +#endif + +#if CONFIG_USBDEBUG + set_ehci_debug(ehci_debug_addr); +#endif + + /* Enable the local cpu apics */ + enable_lapic_tpr(); + lapic_setup(); + + /* Enable virtualization if enabled in CMOS */ + enable_vmx(); + + /* Configure C States */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* Thermal throttle activation offset */ + ret = configure_thermal_target(); + if (ret) + return ret; + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + /* Set Max Ratio */ + set_max_ratio(); + + /* Enable Turbo */ + turbo_enable(); + + /* Start up extra cores */ + intel_cores_init(cpu); + + return 0; +} diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 6454dd9..96d51c2 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -15,4 +15,7 @@ void bd82x6x_usb_xhci_init(pci_dev_t dev); int bd82x6x_init_pci_devices(void); int bd82x6x_init(void); +struct x86_cpu_priv; +int model_206ax_init(struct x86_cpu_priv *cpu); + #endif diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 6027d59..2cbb270 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -326,6 +326,8 @@ #define MSR_AMD_PERF_STATUS 0xc0010063 #define MSR_AMD_PERF_CTL 0xc0010062 +#define MSR_PMG_CST_CONFIG_CTL 0x000000e2 +#define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 #define MSR_IA32_MPERF 0x000000e7 #define MSR_IA32_APERF 0x000000e8 -- cgit v1.1 From d1ef1132bbcf2cc14f36f5114d88ff3fa74106df Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 24 Nov 2014 21:18:17 -0700 Subject: x86: Drop some msr functions that we don't support These are not available in U-Boot as yet, so drop them. Signed-off-by: Simon Glass --- arch/x86/include/asm/msr.h | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index df43983..1955a75 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -229,17 +229,6 @@ do { \ struct msr *msrs_alloc(void); void msrs_free(struct msr *msrs); -#ifdef CONFIG_SMP -int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); -int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); -void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); -void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); -int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); -int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); -int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); -int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); - -#endif /* CONFIG_SMP */ #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_MSR_H */ -- cgit v1.1 From 24774278c9dc4e44487cb565282d4a4830327fd4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 24 Nov 2014 21:18:18 -0700 Subject: x86: ivybridge: Add northbridge init functions Add init for the northbridge, another part of the platform controller hub. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 2 + arch/x86/cpu/ivybridge/northbridge.c | 188 ++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/model_206ax.h | 4 + arch/x86/include/asm/arch-ivybridge/sandybridge.h | 13 +- 5 files changed, 207 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/ivybridge/northbridge.c (limited to 'arch') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 95491b5..1296a78 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -13,6 +13,7 @@ obj-y += lpc.o obj-y += me_status.o obj-y += model_206ax.o obj-y += microcode_intel.o +obj-y += northbridge.o obj-y += pch.o obj-y += pci.o obj-y += report_platform.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 1a3c036..739f979 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -128,6 +128,8 @@ int bd82x6x_init(void) bd82x6x_pci_init(PCH_DEV); bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); + northbridge_enable(PCH_DEV); + northbridge_init(PCH_DEV); return 0; } diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c new file mode 100644 index 0000000..c50b5de --- /dev/null +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -0,0 +1,188 @@ +/* + * From Coreboot northbridge/intel/sandybridge/northbridge.c + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int bridge_revision_id = -1; + +int bridge_silicon_revision(void) +{ + if (bridge_revision_id < 0) { + struct cpuid_result result; + uint8_t stepping, bridge_id; + pci_dev_t dev; + + result = cpuid(1); + stepping = result.eax & 0xf; + dev = PCI_BDF(0, 0, 0); + bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0; + bridge_revision_id = bridge_id | stepping; + } + + return bridge_revision_id; +} + +/* + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) + * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI + */ +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 384; + +static int get_pcie_bar(u32 *base, u32 *len) +{ + pci_dev_t dev = PCI_BDF(0, 0, 0); + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: /* 256MB */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28)); + *len = 256 * 1024 * 1024; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27)); + *len = 128 * 1024 * 1024; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27) | (1 << 26)); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +static void add_fixed_resources(pci_dev_t dev, int index) +{ + u32 pcie_config_base, pcie_config_size; + + if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { + debug("Adding PCIe config bar base=0x%08x size=0x%x\n", + pcie_config_base, pcie_config_size); + } +} + +static void northbridge_dmi_init(pci_dev_t dev) +{ + /* Clear error status bits */ + writel(0xffffffff, DMIBAR_REG(0x1c4)); + writel(0xffffffff, DMIBAR_REG(0x1d0)); + + /* Steps prior to DMI ASPM */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), + 1 << 21); + } + + setbits_le32(DMIBAR_REG(0x238), 1 << 29); + + if (bridge_silicon_revision() >= SNB_STEP_D0) { + setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); + } else if (bridge_silicon_revision() >= SNB_STEP_D1) { + clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); + setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); + } + + /* Enable ASPM on SNB link, should happen before PCH link */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) + setbits_le32(DMIBAR_REG(0xd04), 1 << 4); + + setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); +} + +void northbridge_init(pci_dev_t dev) +{ + u32 bridge_type; + + add_fixed_resources(dev, 6); + northbridge_dmi_init(dev); + + bridge_type = readl(MCHBAR_REG(0x5f10)); + bridge_type &= ~0xff; + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* Enable Power Aware Interrupt Routing - fixed priority */ + clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); + + /* 30h for IvyBridge */ + bridge_type |= 0x30; + } else { + /* 20h for Sandybridge */ + bridge_type |= 0x20; + } + writel(bridge_type, MCHBAR_REG(0x5f10)); + + /* + * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management + */ + setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); + debug("Set BIOS_RESET_CPL\n"); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + set_power_limits(28); + + /* + * CPUs with configurable TDP also need power limits set + * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. + */ + if (cpu_config_tdp_levels()) { + msr_t msr = msr_read(MSR_PKG_POWER_LIMIT); + + writel(msr.lo, MCHBAR_REG(0x59A0)); + writel(msr.hi, MCHBAR_REG(0x59A4)); + } + + /* Set here before graphics PM init */ + writel(0x00100001, MCHBAR_REG(0x5500)); +} + +void northbridge_enable(pci_dev_t dev) +{ +#if CONFIG_HAVE_ACPI_RESUME + switch (pci_read_config32(dev, SKPAD)) { + case 0xcafebabe: + debug("Normal boot.\n"); + apci_set_slp_type(0); + break; + case 0xcafed00d: + debug("S3 Resume.\n"); + apci_set_slp_type(3); + break; + default: + debug("Unknown boot method, assuming normal.\n"); + apci_set_slp_type(0); + break; + } +#endif +} diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h index 8281d7a..7b4f2e7 100644 --- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -79,4 +79,8 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); + #endif diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index 114ee19..cf7457f 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -97,11 +97,22 @@ /* * MCHBAR */ -#define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg)) +#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg)) #define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define BIOS_RESET_CPL 0x5da8 /* 8bit */ +/* + * DMIBAR + */ + +#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x) + +int bridge_silicon_revision(void); + +void northbridge_enable(pci_dev_t dev); +void northbridge_init(pci_dev_t dev); + void report_platform_info(void); void sandybridge_early_init(int chipset_type); -- cgit v1.1 From e34aef1de36893250a788a272b6242e46da31b86 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 20:56:29 -0700 Subject: x86: Add GDT descriptors for option ROMs Option ROMs require a few additional descriptors. Add these, and remove the enum since we now have to access several descriptors from assembler. Signed-off-by: Simon Glass --- arch/x86/cpu/cpu.c | 9 ++++++--- arch/x86/include/asm/processor.h | 31 ++++++++++++------------------- 2 files changed, 18 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index cf421fa..30e5069 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -124,7 +124,7 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries) { struct gdt_ptr gdt; - gdt.len = (num_entries * 8) - 1; + gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; gdt.ptr = (u32)boot_gdt; asm volatile("lgdtl %0\n" : : "m" (gdt)); @@ -144,10 +144,13 @@ void setup_gdt(gd_t *id, u64 *gdt_addr) (ulong)&id->arch.gd_addr, 0xfffff); /* 16-bit CS: code, read/execute, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff); + gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); /* 16-bit DS: data, read/write, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff); + gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); + + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); load_ds(X86_GDT_ENTRY_32BIT_DS); diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index b9317cb..3e26202 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -8,25 +8,18 @@ #ifndef __ASM_PROCESSOR_H_ #define __ASM_PROCESSOR_H_ 1 -#define X86_GDT_ENTRY_SIZE 8 - -#ifndef __ASSEMBLY__ - -enum { - X86_GDT_ENTRY_NULL = 0, - X86_GDT_ENTRY_UNUSED, - X86_GDT_ENTRY_32BIT_CS, - X86_GDT_ENTRY_32BIT_DS, - X86_GDT_ENTRY_32BIT_FS, - X86_GDT_ENTRY_16BIT_CS, - X86_GDT_ENTRY_16BIT_DS, - X86_GDT_NUM_ENTRIES -}; -#else -/* NOTE: If the above enum is modified, this define must be checked */ -#define X86_GDT_ENTRY_32BIT_DS 3 -#define X86_GDT_NUM_ENTRIES 7 -#endif +#define X86_GDT_ENTRY_SIZE 8 + +#define X86_GDT_ENTRY_NULL 0 +#define X86_GDT_ENTRY_UNUSED 1 +#define X86_GDT_ENTRY_32BIT_CS 2 +#define X86_GDT_ENTRY_32BIT_DS 3 +#define X86_GDT_ENTRY_32BIT_FS 4 +#define X86_GDT_ENTRY_16BIT_CS 5 +#define X86_GDT_ENTRY_16BIT_DS 6 +#define X86_GDT_ENTRY_16BIT_FLAT_CS 7 +#define X86_GDT_ENTRY_16BIT_FLAT_DS 8 +#define X86_GDT_NUM_ENTRIES 9 #define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) -- cgit v1.1 From 22465fc46cdec15594277edb33e930c773b10b9e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 20:56:30 -0700 Subject: x86: Add vesa mode configuration options Add Kconfig options to allow selection of a vesa mode on x86 machines. Signed-off-by: Simon Glass --- arch/x86/Kconfig | 149 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 149 insertions(+) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 6e29868..4f5ce38 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -83,6 +83,155 @@ config X86_RAMTEST to work correctly. It is not exhaustive but can save time by detecting obvious failures. +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + +menu "Display" + +config FRAMEBUFFER_SET_VESA_MODE + prompt "Set framebuffer graphics resolution" + bool + help + Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) + +choice + prompt "framebuffer graphics resolution" + default FRAMEBUFFER_VESA_MODE_117 + depends on FRAMEBUFFER_SET_VESA_MODE + help + This option sets the resolution used for the coreboot framebuffer (and + bootsplash screen). + +config FRAMEBUFFER_VESA_MODE_100 + bool "640x400 256-color" + +config FRAMEBUFFER_VESA_MODE_101 + bool "640x480 256-color" + +config FRAMEBUFFER_VESA_MODE_102 + bool "800x600 16-color" + +config FRAMEBUFFER_VESA_MODE_103 + bool "800x600 256-color" + +config FRAMEBUFFER_VESA_MODE_104 + bool "1024x768 16-color" + +config FRAMEBUFFER_VESA_MODE_105 + bool "1024x7686 256-color" + +config FRAMEBUFFER_VESA_MODE_106 + bool "1280x1024 16-color" + +config FRAMEBUFFER_VESA_MODE_107 + bool "1280x1024 256-color" + +config FRAMEBUFFER_VESA_MODE_108 + bool "80x60 text" + +config FRAMEBUFFER_VESA_MODE_109 + bool "132x25 text" + +config FRAMEBUFFER_VESA_MODE_10A + bool "132x43 text" + +config FRAMEBUFFER_VESA_MODE_10B + bool "132x50 text" + +config FRAMEBUFFER_VESA_MODE_10C + bool "132x60 text" + +config FRAMEBUFFER_VESA_MODE_10D + bool "320x200 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_10E + bool "320x200 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_10F + bool "320x200 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_110 + bool "640x480 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_111 + bool "640x480 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_112 + bool "640x480 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_113 + bool "800x600 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_114 + bool "800x600 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_115 + bool "800x600 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_116 + bool "1024x768 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_117 + bool "1024x768 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_118 + bool "1024x768 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_119 + bool "1280x1024 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_11A + bool "1280x1024 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_11B + bool "1280x1024 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_USER + bool "Manually select VESA mode" + +endchoice + +# Map the config names to an integer (KB). +config FRAMEBUFFER_VESA_MODE + prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER + hex + default 0x100 if FRAMEBUFFER_VESA_MODE_100 + default 0x101 if FRAMEBUFFER_VESA_MODE_101 + default 0x102 if FRAMEBUFFER_VESA_MODE_102 + default 0x103 if FRAMEBUFFER_VESA_MODE_103 + default 0x104 if FRAMEBUFFER_VESA_MODE_104 + default 0x105 if FRAMEBUFFER_VESA_MODE_105 + default 0x106 if FRAMEBUFFER_VESA_MODE_106 + default 0x107 if FRAMEBUFFER_VESA_MODE_107 + default 0x108 if FRAMEBUFFER_VESA_MODE_108 + default 0x109 if FRAMEBUFFER_VESA_MODE_109 + default 0x10A if FRAMEBUFFER_VESA_MODE_10A + default 0x10B if FRAMEBUFFER_VESA_MODE_10B + default 0x10C if FRAMEBUFFER_VESA_MODE_10C + default 0x10D if FRAMEBUFFER_VESA_MODE_10D + default 0x10E if FRAMEBUFFER_VESA_MODE_10E + default 0x10F if FRAMEBUFFER_VESA_MODE_10F + default 0x110 if FRAMEBUFFER_VESA_MODE_110 + default 0x111 if FRAMEBUFFER_VESA_MODE_111 + default 0x112 if FRAMEBUFFER_VESA_MODE_112 + default 0x113 if FRAMEBUFFER_VESA_MODE_113 + default 0x114 if FRAMEBUFFER_VESA_MODE_114 + default 0x115 if FRAMEBUFFER_VESA_MODE_115 + default 0x116 if FRAMEBUFFER_VESA_MODE_116 + default 0x117 if FRAMEBUFFER_VESA_MODE_117 + default 0x118 if FRAMEBUFFER_VESA_MODE_118 + default 0x119 if FRAMEBUFFER_VESA_MODE_119 + default 0x11A if FRAMEBUFFER_VESA_MODE_11A + default 0x11B if FRAMEBUFFER_VESA_MODE_11B + default 0x117 if FRAMEBUFFER_VESA_MODE_USER + +endmenu + source "arch/x86/cpu/ivybridge/Kconfig" source "board/coreboot/coreboot/Kconfig" -- cgit v1.1 From 0ca2426beae04189f094180748e72463f48a9270 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 20:56:32 -0700 Subject: x86: Add support for running option ROMs natively On x86 machines we can use an emulator to run option ROMS as with other architectures. But with some additional effort (mostly due to the 16-bit nature of option ROMs) we can run them natively. Add support for this. Signed-off-by: Simon Glass --- arch/x86/lib/Makefile | 3 + arch/x86/lib/bios.c | 347 +++++++++++++++++++++++++++++++++++++++++ arch/x86/lib/bios.h | 98 ++++++++++++ arch/x86/lib/bios_asm.S | 281 +++++++++++++++++++++++++++++++++ arch/x86/lib/bios_interrupts.c | 217 ++++++++++++++++++++++++++ 5 files changed, 946 insertions(+) create mode 100644 arch/x86/lib/bios.c create mode 100644 arch/x86/lib/bios.h create mode 100644 arch/x86/lib/bios_asm.S create mode 100644 arch/x86/lib/bios_interrupts.c (limited to 'arch') diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index e146e64..55de788 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -5,6 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += bios.o +obj-y += bios_asm.o +obj-y += bios_interrupts.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cmd_boot.o obj-y += gcc.o diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c new file mode 100644 index 0000000..298fca6 --- /dev/null +++ b/arch/x86/lib/bios.c @@ -0,0 +1,347 @@ +/* + * From Coreboot file device/oprom/realmode/x86.c + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2009-2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "bios.h" + +/* Interrupt handlers for each interrupt the ROM can call */ +static int (*int_handler[256])(void); + +/* to have a common register file for interrupt handlers */ +X86EMU_sysEnv _X86EMU_env; + +asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi); + +asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, + u32 edx, u32 esi, u32 edi); + +static void setup_realmode_code(void) +{ + memcpy((void *)REALMODE_BASE, &asm_realmode_code, + asm_realmode_code_size); + + /* Ensure the global pointers are relocated properly. */ + realmode_call = PTR_TO_REAL_MODE(asm_realmode_call); + realmode_interrupt = PTR_TO_REAL_MODE(__realmode_interrupt); + + debug("Real mode stub @%x: %d bytes\n", REALMODE_BASE, + asm_realmode_code_size); +} + +static void setup_rombios(void) +{ + const char date[] = "06/11/99"; + memcpy((void *)0xffff5, &date, 8); + + const char ident[] = "PCI_ISA"; + memcpy((void *)0xfffd9, &ident, 7); + + /* system model: IBM-AT */ + writeb(0xfc, 0xffffe); +} + +static int int_exception_handler(void) +{ + /* compatibility shim */ + struct eregs reg_info = { + .eax = M.x86.R_EAX, + .ecx = M.x86.R_ECX, + .edx = M.x86.R_EDX, + .ebx = M.x86.R_EBX, + .esp = M.x86.R_ESP, + .ebp = M.x86.R_EBP, + .esi = M.x86.R_ESI, + .edi = M.x86.R_EDI, + .vector = M.x86.intno, + .error_code = 0, + .eip = M.x86.R_EIP, + .cs = M.x86.R_CS, + .eflags = M.x86.R_EFLG + }; + struct eregs *regs = ®_info; + + debug("Oops, exception %d while executing option rom\n", regs->vector); + cpu_hlt(); + + return 0; +} + +static int int_unknown_handler(void) +{ + debug("Unsupported software interrupt #0x%x eax 0x%x\n", + M.x86.intno, M.x86.R_EAX); + + return -1; +} + +/* setup interrupt handlers for mainboard */ +void bios_set_interrupt_handler(int intnum, int (*int_func)(void)) +{ + int_handler[intnum] = int_func; +} + +static void setup_interrupt_handlers(void) +{ + int i; + + /* + * The first 16 int_handler functions are not BIOS services, + * but the CPU-generated exceptions ("hardware interrupts") + */ + for (i = 0; i < 0x10; i++) + int_handler[i] = &int_exception_handler; + + /* Mark all other int_handler calls as unknown first */ + for (i = 0x10; i < 0x100; i++) { + /* Skip if bios_set_interrupt_handler() isn't called first */ + if (int_handler[i]) + continue; + + /* + * Now set the default functions that are actually needed + * to initialize the option roms. The board may override + * these with bios_set_interrupt_handler() + */ + switch (i) { + case 0x10: + int_handler[0x10] = &int10_handler; + break; + case 0x12: + int_handler[0x12] = &int12_handler; + break; + case 0x16: + int_handler[0x16] = &int16_handler; + break; + case 0x1a: + int_handler[0x1a] = &int1a_handler; + break; + default: + int_handler[i] = &int_unknown_handler; + break; + } + } +} + +static void write_idt_stub(void *target, u8 intnum) +{ + unsigned char *codeptr; + + codeptr = (unsigned char *)target; + memcpy(codeptr, &__idt_handler, __idt_handler_size); + codeptr[3] = intnum; /* modify int# in the code stub. */ +} + +static void setup_realmode_idt(void) +{ + struct realmode_idt *idts = NULL; + int i; + + /* + * Copy IDT stub code for each interrupt. This might seem wasteful + * but it is really simple + */ + for (i = 0; i < 256; i++) { + idts[i].cs = 0; + idts[i].offset = 0x1000 + (i * __idt_handler_size); + write_idt_stub((void *)((u32)idts[i].offset), i); + } + + /* + * Many option ROMs use the hard coded interrupt entry points in the + * system bios. So install them at the known locations. + */ + + /* int42 is the relocated int10 */ + write_idt_stub((void *)0xff065, 0x42); + /* BIOS Int 11 Handler F000:F84D */ + write_idt_stub((void *)0xff84d, 0x11); + /* BIOS Int 12 Handler F000:F841 */ + write_idt_stub((void *)0xff841, 0x12); + /* BIOS Int 13 Handler F000:EC59 */ + write_idt_stub((void *)0xfec59, 0x13); + /* BIOS Int 14 Handler F000:E739 */ + write_idt_stub((void *)0xfe739, 0x14); + /* BIOS Int 15 Handler F000:F859 */ + write_idt_stub((void *)0xff859, 0x15); + /* BIOS Int 16 Handler F000:E82E */ + write_idt_stub((void *)0xfe82e, 0x16); + /* BIOS Int 17 Handler F000:EFD2 */ + write_idt_stub((void *)0xfefd2, 0x17); + /* ROM BIOS Int 1A Handler F000:FE6E */ + write_idt_stub((void *)0xffe6e, 0x1a); +} + +static u8 vbe_get_mode_info(struct vbe_mode_info *mi) +{ + u16 buffer_seg; + u16 buffer_adr; + char *buffer; + + debug("VBE: Getting information about VESA mode %04x\n", + mi->video_mode); + buffer = PTR_TO_REAL_MODE(asm_realmode_buffer); + buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00; + buffer_adr = ((unsigned long)buffer) & 0xffff; + + realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode, + 0x0000, buffer_seg, buffer_adr); + memcpy(mi->mode_info_block, buffer, sizeof(struct vbe_mode_info)); + mi->valid = true; + + return 0; +} + +static u8 vbe_set_mode(struct vbe_mode_info *mi) +{ + debug("VBE: Setting VESA mode %#04x\n", mi->video_mode); + /* request linear framebuffer mode */ + mi->video_mode |= (1 << 14); + /* request clearing of framebuffer */ + mi->video_mode &= ~(1 << 15); + realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode, + 0x0000, 0x0000, 0x0000, 0x0000); + + return 0; +} + +static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info) +{ + unsigned char *framebuffer; + + mode_info->video_mode = (1 << 14) | vesa_mode; + vbe_get_mode_info(mode_info); + + framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr; + debug("VBE: resolution: %dx%d@%d\n", + le16_to_cpu(mode_info->vesa.x_resolution), + le16_to_cpu(mode_info->vesa.y_resolution), + mode_info->vesa.bits_per_pixel); + debug("VBE: framebuffer: %p\n", framebuffer); + if (!framebuffer) { + debug("VBE: Mode does not support linear framebuffer\n"); + return; + } + + vbe_set_mode(mode_info); +} + +void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode, + struct vbe_mode_info *mode_info) +{ + u32 num_dev; + + num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 | + PCI_FUNC(pcidev); + + /* Needed to avoid exceptions in some ROMs */ + interrupt_init(); + + /* Set up some legacy information in the F segment */ + setup_rombios(); + + /* Set up C interrupt handlers */ + setup_interrupt_handlers(); + + /* Set up real-mode IDT */ + setup_realmode_idt(); + + /* Make sure the code is placed. */ + setup_realmode_code(); + + disable_caches(); + debug("Calling Option ROM at %lx, pci device %#x...", addr, num_dev); + + /* Option ROM entry point is at OPROM start + 3 */ + realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, + 0x0); + debug("done\n"); + + if (vesa_mode != -1) + vbe_set_graphics(vesa_mode, mode_info); +} + +asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses, + u32 edi, u32 esi, u32 ebp, u32 esp, + u32 ebx, u32 edx, u32 ecx, u32 eax, + u32 cs_ip, u16 stackflags) +{ + u32 ip; + u32 cs; + u32 flags; + int ret = 0; + + ip = cs_ip & 0xffff; + cs = cs_ip >> 16; + flags = stackflags; + +#ifdef CONFIG_REALMODE_DEBUG + debug("oprom: INT# 0x%x\n", intnumber); + debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n", + eax, ebx, ecx, edx); + debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n", + ebp, esp, edi, esi); + debug("oprom: ip: %04x cs: %04x flags: %08x\n", + ip, cs, flags); + debug("oprom: stackflags = %04x\n", stackflags); +#endif + + /* + * Fetch arguments from the stack and put them to a place + * suitable for the interrupt handlers + */ + M.x86.R_EAX = eax; + M.x86.R_ECX = ecx; + M.x86.R_EDX = edx; + M.x86.R_EBX = ebx; + M.x86.R_ESP = esp; + M.x86.R_EBP = ebp; + M.x86.R_ESI = esi; + M.x86.R_EDI = edi; + M.x86.intno = intnumber; + M.x86.R_EIP = ip; + M.x86.R_CS = cs; + M.x86.R_EFLG = flags; + + /* Call the interrupt handler for this interrupt number */ + ret = int_handler[intnumber](); + + /* + * This code is quite strange... + * + * Put registers back on the stack. The assembler code will pop them + * later. We force (volatile!) changing the values of the parameters + * of this function. We know that they stay alive on the stack after + * we leave this function. + */ + *(volatile u32 *)&eax = M.x86.R_EAX; + *(volatile u32 *)&ecx = M.x86.R_ECX; + *(volatile u32 *)&edx = M.x86.R_EDX; + *(volatile u32 *)&ebx = M.x86.R_EBX; + *(volatile u32 *)&esi = M.x86.R_ESI; + *(volatile u32 *)&edi = M.x86.R_EDI; + flags = M.x86.R_EFLG; + + /* Pass success or error back to our caller via the CARRY flag */ + if (ret) { + flags &= ~1; /* no error: clear carry */ + } else { + debug("int%02x call returned error\n", intnumber); + flags |= 1; /* error: set carry */ + } + *(volatile u16 *)&stackflags = flags; + + return ret; +} diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h new file mode 100644 index 0000000..8491b4a --- /dev/null +++ b/arch/x86/lib/bios.h @@ -0,0 +1,98 @@ +/* + * From Coreboot file device/oprom/realmode/x86.h + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2009-2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _X86_LIB_BIOS_H +#define _X86_LIB_BIOS_H + +#define REALMODE_BASE 0x600 + +#ifdef __ASSEMBLY__ + +#define PTR_TO_REAL_MODE(x) (x - asm_realmode_code + REALMODE_BASE) + +#else + +/* Convert a symbol address to our real mode area */ +#define PTR_TO_REAL_MODE(sym)\ + (void *)(REALMODE_BASE + ((char *)&(sym) - (char *)&asm_realmode_code)) + +/* + * The following symbols cannot be used directly. They need to be fixed up + * to point to the correct address location after the code has been copied + * to REALMODE_BASE. Absolute symbols are not used because those symbols are + * relocated by U-Boot. + */ +extern unsigned char asm_realmode_call, __realmode_interrupt; +extern unsigned char asm_realmode_buffer; + +#define DOWNTO8(A) \ + union { \ + struct { \ + union { \ + struct { \ + uint8_t A##l; \ + uint8_t A##h; \ + } __packed; \ + uint16_t A##x; \ + } __packed; \ + uint16_t h##A##x; \ + } __packed; \ + uint32_t e##A##x; \ + } __packed; + +#define DOWNTO16(A) \ + union { \ + struct { \ + uint16_t A; \ + uint16_t h##A; \ + } __packed; \ + uint32_t e##A; \ + } __packed; + +struct eregs { + DOWNTO8(a); + DOWNTO8(c); + DOWNTO8(d); + DOWNTO8(b); + DOWNTO16(sp); + DOWNTO16(bp); + DOWNTO16(si); + DOWNTO16(di); + uint32_t vector; + uint32_t error_code; + uint32_t eip; + uint32_t cs; + uint32_t eflags; +}; + +struct realmode_idt { + u16 offset, cs; +}; + +void x86_exception(struct eregs *info); + +/* From x86_asm.S */ +extern unsigned char __idt_handler; +extern unsigned int __idt_handler_size; +extern unsigned char asm_realmode_code; +extern unsigned int asm_realmode_code_size; + +asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi); + +asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, + u32 edx, u32 esi, u32 edi); + +int int10_handler(void); +int int12_handler(void); +int int16_handler(void); +int int1a_handler(void); +#endif /*__ASSEMBLY__ */ + +#endif diff --git a/arch/x86/lib/bios_asm.S b/arch/x86/lib/bios_asm.S new file mode 100644 index 0000000..4faa70e --- /dev/null +++ b/arch/x86/lib/bios_asm.S @@ -0,0 +1,281 @@ +/* + * From coreboot x86_asm.S, cleaned up substantially + * + * Copyright (C) 2009-2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include "bios.h" + +#define SEG(segment) $segment * X86_GDT_ENTRY_SIZE + +/* + * This is the interrupt handler stub code. It gets copied to the IDT and + * to some fixed addresses in the F segment. Before the code can used, + * it gets patched up by the C function copying it: byte 3 (the $0 in + * movb $0, %al) is overwritten with the interrupt numbers. + */ + + .code16 + .globl __idt_handler +__idt_handler: + pushal + movb $0, %al /* This instruction gets modified */ + ljmp $0, $__interrupt_handler_16bit + .globl __idt_handler_size +__idt_handler_size: + .long . - __idt_handler + +.macro setup_registers + /* initial register values */ + movl 44(%ebp), %eax + movl %eax, __registers + 0 /* eax */ + movl 48(%ebp), %eax + movl %eax, __registers + 4 /* ebx */ + movl 52(%ebp), %eax + movl %eax, __registers + 8 /* ecx */ + movl 56(%ebp), %eax + movl %eax, __registers + 12 /* edx */ + movl 60(%ebp), %eax + movl %eax, __registers + 16 /* esi */ + movl 64(%ebp), %eax + movl %eax, __registers + 20 /* edi */ +.endm + +.macro enter_real_mode + /* Activate the right segment descriptor real mode. */ + ljmp SEG(X86_GDT_ENTRY_16BIT_CS), $PTR_TO_REAL_MODE(1f) +1: +.code16 + /* + * Load the segment registers with properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. + */ + mov SEG(X86_GDT_ENTRY_16BIT_DS), %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss + + /* Turn off protection */ + movl %cr0, %eax + andl $~X86_CR0_PE, %eax + movl %eax, %cr0 + + /* Now really going into real mode */ + ljmp $0, $PTR_TO_REAL_MODE(1f) +1: + /* + * Set up a stack: Put the stack at the end of page zero. That way + * we can easily share it between real and protected, since the + * 16-bit ESP at segment 0 will work for any case. + */ + mov $0x0, %ax + mov %ax, %ss + + /* Load 16 bit IDT */ + xor %ax, %ax + mov %ax, %ds + lidt __realmode_idt + +.endm + +.macro prepare_for_irom + movl $0x1000, %eax + movl %eax, %esp + + /* Initialise registers for option rom lcall */ + movl __registers + 0, %eax + movl __registers + 4, %ebx + movl __registers + 8, %ecx + movl __registers + 12, %edx + movl __registers + 16, %esi + movl __registers + 20, %edi + + /* Set all segments to 0x0000, ds to 0x0040 */ + push %ax + xor %ax, %ax + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov SEG(X86_GDT_ENTRY_16BIT_FLAT_DS), %ax + mov %ax, %ds + pop %ax + +.endm + +.macro enter_protected_mode + /* Go back to protected mode */ + movl %cr0, %eax + orl $X86_CR0_PE, %eax + movl %eax, %cr0 + + /* Now that we are in protected mode jump to a 32 bit code segment */ + data32 ljmp SEG(X86_GDT_ENTRY_32BIT_CS), $PTR_TO_REAL_MODE(1f) +1: + .code32 + mov SEG(X86_GDT_ENTRY_32BIT_DS), %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %gs + mov %ax, %ss + mov SEG(X86_GDT_ENTRY_32BIT_FS), %ax + mov %ax, %fs + + /* restore proper idt */ + lidt idt_ptr +.endm + +/* + * In order to be independent of U-Boot's position in RAM we relocate a part + * of the code to the first megabyte of RAM, so the CPU can use it in + * real-mode. This code lives at asm_realmode_code. + */ + .globl asm_realmode_code +asm_realmode_code: + +/* Realmode IDT pointer structure. */ +__realmode_idt = PTR_TO_REAL_MODE(.) + .word 1023 /* 16 bit limit */ + .long 0 /* 24 bit base */ + .word 0 + +/* Preserve old stack */ +__stack = PTR_TO_REAL_MODE(.) + .long 0 + +/* Register store for realmode_call and realmode_interrupt */ +__registers = PTR_TO_REAL_MODE(.) + .long 0 /* 0 - EAX */ + .long 0 /* 4 - EBX */ + .long 0 /* 8 - ECX */ + .long 0 /* 12 - EDX */ + .long 0 /* 16 - ESI */ + .long 0 /* 20 - EDI */ + +/* 256 byte buffer, used by int10 */ + .globl asm_realmode_buffer +asm_realmode_buffer: + .skip 256 + + .code32 + .globl asm_realmode_call +asm_realmode_call: + /* save all registers to the stack */ + pusha + pushf + movl %esp, __stack + movl %esp, %ebp + + /* + * This function is called with regparm=0 and we have to skip the + * 36 bytes from pushf+pusha. Hence start at 40. + * Set up our call instruction. + */ + movl 40(%ebp), %eax + mov %ax, __lcall_instr + 1 + andl $0xffff0000, %eax + shrl $4, %eax + mov %ax, __lcall_instr + 3 + + wbinvd + + setup_registers + enter_real_mode + prepare_for_irom + +__lcall_instr = PTR_TO_REAL_MODE(.) + .byte 0x9a + .word 0x0000, 0x0000 + + enter_protected_mode + + /* restore stack pointer, eflags and register values and exit */ + movl __stack, %esp + popf + popa + ret + + .globl __realmode_interrupt +__realmode_interrupt: + /* save all registers to the stack and store the stack pointer */ + pusha + pushf + movl %esp, __stack + movl %esp, %ebp + + /* + * This function is called with regparm=0 and we have to skip the + * 36 bytes from pushf+pusha. Hence start at 40. + * Prepare interrupt calling code. + */ + movl 40(%ebp), %eax + movb %al, __intXX_instr + 1 /* intno */ + + setup_registers + enter_real_mode + prepare_for_irom + +__intXX_instr = PTR_TO_REAL_MODE(.) + .byte 0xcd, 0x00 /* This becomes intXX */ + + enter_protected_mode + + /* restore stack pointer, eflags and register values and exit */ + movl __stack, %esp + popf + popa + ret + +/* + * This is the 16-bit interrupt entry point called by the IDT stub code. + * + * Before this code code is called, %eax is pushed to the stack, and the + * interrupt number is loaded into %al. On return this function cleans up + * for its caller. + */ + .code16 +__interrupt_handler_16bit = PTR_TO_REAL_MODE(.) + push %ds + push %es + push %fs + push %gs + + /* Clear DF to not break ABI assumptions */ + cld + + /* + * Clean up the interrupt number. We could do this in the stub, but + * it would cost two more bytes per stub entry. + */ + andl $0xff, %eax + pushl %eax /* ... and make it the first parameter */ + + enter_protected_mode + + /* Call the C interrupt handler */ + movl $interrupt_handler, %eax + call *%eax + + enter_real_mode + + /* + * Restore all registers, including those manipulated by the C + * handler + */ + popl %eax + pop %gs + pop %fs + pop %es + pop %ds + popal + iret + + .globl asm_realmode_code_size +asm_realmode_code_size: + .long . - asm_realmode_code diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c new file mode 100644 index 0000000..b0e2ecb --- /dev/null +++ b/arch/x86/lib/bios_interrupts.c @@ -0,0 +1,217 @@ +/* + * From Coreboot + * + * Copyright (C) 2001 Ronald G. Minnich + * Copyright (C) 2005 Nick.Barker9@btinternet.com + * Copyright (C) 2007-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include "bios_emul.h" + +/* errors go in AH. Just set these up so that word assigns will work */ +enum { + PCIBIOS_SUCCESSFUL = 0x0000, + PCIBIOS_UNSUPPORTED = 0x8100, + PCIBIOS_BADVENDOR = 0x8300, + PCIBIOS_NODEV = 0x8600, + PCIBIOS_BADREG = 0x8700 +}; + +int int10_handler(void) +{ + static u8 cursor_row, cursor_col; + int res = 0; + + switch ((M.x86.R_EAX & 0xff00) >> 8) { + case 0x01: /* Set cursor shape */ + res = 1; + break; + case 0x02: /* Set cursor position */ + if (cursor_row != ((M.x86.R_EDX >> 8) & 0xff) || + cursor_col >= (M.x86.R_EDX & 0xff)) { + debug("\n"); + } + cursor_row = (M.x86.R_EDX >> 8) & 0xff; + cursor_col = M.x86.R_EDX & 0xff; + res = 1; + break; + case 0x03: /* Get cursor position */ + M.x86.R_EAX &= 0x00ff; + M.x86.R_ECX = 0x0607; + M.x86.R_EDX = (cursor_row << 8) | cursor_col; + res = 1; + break; + case 0x06: /* Scroll up */ + debug("\n"); + res = 1; + break; + case 0x08: /* Get Character and Mode at Cursor Position */ + M.x86.R_EAX = 0x0f00 | 'A'; /* White on black 'A' */ + res = 1; + break; + case 0x09: /* Write Character and attribute */ + case 0x0e: /* Write Character */ + debug("%c", M.x86.R_EAX & 0xff); + res = 1; + break; + case 0x0f: /* Get video mode */ + M.x86.R_EAX = 0x5002; /*80 x 25 */ + M.x86.R_EBX &= 0x00ff; + res = 1; + break; + default: + printf("Unknown INT10 function %04x\n", M.x86.R_EAX & 0xffff); + break; + } + return res; +} + +int int12_handler(void) +{ + M.x86.R_EAX = 64 * 1024; + return 1; +} + +int int16_handler(void) +{ + int res = 0; + + switch ((M.x86.R_EAX & 0xff00) >> 8) { + case 0x00: /* Check for Keystroke */ + M.x86.R_EAX = 0x6120; /* Space Bar, Space */ + res = 1; + break; + case 0x01: /* Check for Keystroke */ + M.x86.R_EFLG |= 1 << 6; /* Zero Flag set (no key available) */ + res = 1; + break; + default: + printf("Unknown INT16 function %04x\n", M.x86.R_EAX & 0xffff); + +break; + } + return res; +} + +#define PCI_CONFIG_SPACE_TYPE1 (1 << 0) +#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4) + +int int1a_handler(void) +{ + unsigned short func = (unsigned short)M.x86.R_EAX; + int retval = 1; + unsigned short devid, vendorid, devfn; + /* Use short to get rid of gabage in upper half of 32-bit register */ + short devindex; + unsigned char bus; + pci_dev_t dev; + u32 dword; + u16 word; + u8 byte, reg; + + switch (func) { + case 0xb101: /* PCIBIOS Check */ + M.x86.R_EDX = 0x20494350; /* ' ICP' */ + M.x86.R_EAX &= 0xffff0000; /* Clear AH / AL */ + M.x86.R_EAX |= PCI_CONFIG_SPACE_TYPE1 | + PCI_SPECIAL_CYCLE_TYPE1; + /* + * last bus in the system. Hard code to 255 for now. + * dev_enumerate() does not seem to tell us (publically) + */ + M.x86.R_ECX = 0xff; + M.x86.R_EDI = 0x00000000; /* protected mode entry */ + retval = 1; + break; + case 0xb102: /* Find Device */ + devid = M.x86.R_ECX; + vendorid = M.x86.R_EDX; + devindex = M.x86.R_ESI; + dev = pci_find_device(vendorid, devid, devindex); + if (dev != -1) { + unsigned short busdevfn; + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_SUCCESSFUL; + /* + * busnum is an unsigned char; + * devfn is an int, so we mask it off. + */ + busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 | + PCI_FUNC(dev); + debug("0x%x: return 0x%x\n", func, busdevfn); + M.x86.R_EBX = busdevfn; + retval = 1; + } else { + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_NODEV; + retval = 0; + } + break; + case 0xb10a: /* Read Config Dword */ + case 0xb109: /* Read Config Word */ + case 0xb108: /* Read Config Byte */ + case 0xb10d: /* Write Config Dword */ + case 0xb10c: /* Write Config Word */ + case 0xb10b: /* Write Config Byte */ + devfn = M.x86.R_EBX & 0xff; + bus = M.x86.R_EBX >> 8; + reg = M.x86.R_EDI; + dev = PCI_BDF(bus, devfn >> 3, devfn & 7); + if (!dev) { + debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, + bus, devfn); + /* Or are we supposed to return PCIBIOS_NODEV? */ + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_BADREG; + retval = 0; + return retval; + } + switch (func) { + case 0xb108: /* Read Config Byte */ + byte = pci_read_config8(dev, reg); + M.x86.R_ECX = byte; + break; + case 0xb109: /* Read Config Word */ + word = pci_read_config16(dev, reg); + M.x86.R_ECX = word; + break; + case 0xb10a: /* Read Config Dword */ + dword = pci_read_config32(dev, reg); + M.x86.R_ECX = dword; + break; + case 0xb10b: /* Write Config Byte */ + byte = M.x86.R_ECX; + pci_write_config8(dev, reg, byte); + break; + case 0xb10c: /* Write Config Word */ + word = M.x86.R_ECX; + pci_write_config16(dev, reg, word); + break; + case 0xb10d: /* Write Config Dword */ + dword = M.x86.R_ECX; + pci_write_config32(dev, reg, dword); + break; + } + +#ifdef CONFIG_REALMODE_DEBUG + debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, + bus, devfn, reg, M.x86.R_ECX); +#endif + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_SUCCESSFUL; + retval = 1; + break; + default: + printf("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_UNSUPPORTED; + retval = 0; + break; + } + + return retval; +} -- cgit v1.1 From effcf067df5f986b8f9a2ca5101c74495be700ab Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 20:56:36 -0700 Subject: x86: Add initial video device init for Intel GMA Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 13 +- arch/x86/cpu/ivybridge/gma.c | 756 ++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/gma.h | 156 ++++++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 + 5 files changed, 927 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/ivybridge/gma.c create mode 100644 arch/x86/cpu/ivybridge/gma.h (limited to 'arch') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 1296a78..0c7efae 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -9,6 +9,7 @@ obj-y += car.o obj-y += cpu.o obj-y += early_init.o obj-y += early_me.o +obj-y += gma.o obj-y += lpc.o obj-y += me_status.o obj-y += model_206ax.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 739f979..65a17d3 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -91,7 +91,8 @@ int bd82x6x_init_pci_devices(void) const void *blob = gd->fdt_blob; struct pci_controller *hose; struct x86_cpu_priv *cpu; - int sata_node; + int sata_node, gma_node; + int ret; hose = pci_bus_to_hose(0); lpc_enable(PCH_LPC_DEV); @@ -111,6 +112,16 @@ int bd82x6x_init_pci_devices(void) return -ENOMEM; model_206ax_init(cpu); + gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); + if (gma_node < 0) { + debug("%s: Cannot find GMA node\n", __func__); + return -EINVAL; + } + ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob, + gma_node); + if (ret) + return ret; + return 0; } diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c new file mode 100644 index 0000000..3d7f740 --- /dev/null +++ b/arch/x86/cpu/ivybridge/gma.c @@ -0,0 +1,756 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2011 Chromium OS Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct gt_powermeter { + u16 reg; + u32 value; +}; + +static const struct gt_powermeter snb_pm_gt1[] = { + { 0xa200, 0xcc000000 }, + { 0xa204, 0x07000040 }, + { 0xa208, 0x0000fe00 }, + { 0xa20c, 0x00000000 }, + { 0xa210, 0x17000000 }, + { 0xa214, 0x00000021 }, + { 0xa218, 0x0817fe19 }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0xcc000000 }, + { 0xa228, 0x07000040 }, + { 0xa22c, 0x0000fe00 }, + { 0xa230, 0x00000000 }, + { 0xa234, 0x17000000 }, + { 0xa238, 0x00000021 }, + { 0xa23c, 0x0817fe19 }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +static const struct gt_powermeter snb_pm_gt2[] = { + { 0xa200, 0x330000a6 }, + { 0xa204, 0x402d0031 }, + { 0xa208, 0x00165f83 }, + { 0xa20c, 0xf1000000 }, + { 0xa210, 0x00000000 }, + { 0xa214, 0x00160016 }, + { 0xa218, 0x002a002b }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0x330000a6 }, + { 0xa228, 0x402d0031 }, + { 0xa22c, 0x00165f83 }, + { 0xa230, 0xf1000000 }, + { 0xa234, 0x00000000 }, + { 0xa238, 0x00160016 }, + { 0xa23c, 0x002a002b }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt1[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00021c00 }, + { 0xa808, 0x00000403 }, + { 0xa80c, 0x02001700 }, + { 0xa810, 0x05000200 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00690500 }, + { 0xa81c, 0x0000007f }, + { 0xa820, 0x01002501 }, + { 0xa824, 0x00000300 }, + { 0xa828, 0x01000331 }, + { 0xa82c, 0x0000000c }, + { 0xa830, 0x00010016 }, + { 0xa834, 0x01100101 }, + { 0xa838, 0x00010103 }, + { 0xa83c, 0x00041300 }, + { 0xa840, 0x00000b30 }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x7f000000 }, + { 0xa84c, 0x05000008 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000004 }, + { 0xa858, 0x00000007 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00010000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00001c00 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x06000000 }, + { 0xa910, 0x09000200 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00590000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x04002501 }, + { 0xa924, 0x00000100 }, + { 0xa928, 0x03000410 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00020000 }, + { 0xa934, 0x02070106 }, + { 0xa938, 0x00010100 }, + { 0xa93c, 0x00401c00 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x10000e00 }, + { 0xa94c, 0x02000004 }, + { 0xa950, 0x00000001 }, + { 0xa954, 0x00000004 }, + { 0xa960, 0x00060000 }, + { 0xaa3c, 0x00001c00 }, + { 0xaa54, 0x00000004 }, + { 0xaa60, 0x00060000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2[] = { + { 0xa800, 0x10000000 }, + { 0xa804, 0x00033800 }, + { 0xa808, 0x00000902 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x12000400 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20800 }, + { 0xa81c, 0x00000002 }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00010032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x0000151d }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x20001b00 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000000 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003500 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000500 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000200 }, + { 0xa928, 0x07000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x050f020d }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2_17w[] = { + { 0xa800, 0x20000000 }, + { 0xa804, 0x000e3800 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000800 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000002 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x0000000f }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000800 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x15150406 }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2_35w[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00030400 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000300 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000800 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x15150406 }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +/* + * Some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + */ + +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x80860102: /* GT1 Desktop */ + case 0x8086010a: /* GT1 Server */ + case 0x80860112: /* GT2 Desktop */ + case 0x80860116: /* GT2 Mobile */ + case 0x80860122: /* GT2 Desktop >=1.3GHz */ + case 0x80860126: /* GT2 Mobile >=1.3GHz */ + case 0x80860156: /* IVB */ + case 0x80860166: /* IVB */ + /* Set to GT1 Mobile */ + new_vendev = 0x80860106; + break; + } + + return new_vendev; +} + +static inline u32 gtt_read(void *bar, u32 reg) +{ + return readl(bar + reg); +} + +static inline void gtt_write(void *bar, u32 reg, u32 data) +{ + writel(data, bar + reg); +} + +static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm) +{ + for (; pm && pm->reg; pm++) + gtt_write(bar, pm->reg, pm->value); +} + +#define GTT_RETRY 1000 +static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value) +{ + unsigned try = GTT_RETRY; + u32 data; + + while (try--) { + data = gtt_read(bar, reg); + if ((data & mask) == value) + return 1; + udelay(10); + } + + printf("GT init timeout\n"); + return 0; +} + +static int gma_pm_init_pre_vbios(void *gtt_bar) +{ + u32 reg32; + + debug("GT Power Management Init, silicon = %#x\n", + bridge_silicon_revision()); + + if (bridge_silicon_revision() < IVB_STEP_C0) { + /* 1: Enable force wake */ + gtt_write(gtt_bar, 0xa18c, 0x00000001); + gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0)); + } else { + gtt_write(gtt_bar, 0xa180, 1 << 5); + gtt_write(gtt_bar, 0xa188, 0xffff0001); + gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0)); + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ + reg32 = gtt_read(gtt_bar, 0x42004); + reg32 |= (1 << 14) | (1 << 15); + gtt_write(gtt_bar, 0x42004, reg32); + } + + if (bridge_silicon_revision() >= IVB_STEP_A0) { + /* Display Reset Acknowledge Settings */ + reg32 = gtt_read(gtt_bar, 0x45010); + reg32 |= (1 << 1) | (1 << 0); + gtt_write(gtt_bar, 0x45010, reg32); + } + + /* 2: Get GT SKU from GTT+0x911c[13] */ + reg32 = gtt_read(gtt_bar, 0x911c); + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if (reg32 & (1 << 13)) { + debug("SNB GT1 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, snb_pm_gt1); + } else { + debug("SNB GT2 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, snb_pm_gt2); + } + } else { + u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf; + + if (reg32 & (1 << 13)) { + /* GT1 SKU */ + debug("IVB GT1 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt1); + } else { + /* GT2 SKU */ + u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff; + tdp /= (1 << unit); + + if (tdp <= 17) { + /* <=17W ULV */ + debug("IVB GT2 17W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w); + } else if ((tdp >= 25) && (tdp <= 35)) { + /* 25W-35W */ + debug("IVB GT2 25W-35W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); + } else { + /* All others */ + debug("IVB GT2 35W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); + } + } + } + + /* 3: Gear ratio map */ + gtt_write(gtt_bar, 0xa004, 0x00000010); + + /* 4: GFXPAUSE */ + gtt_write(gtt_bar, 0xa000, 0x00070020); + + /* 5: Dynamic EU trip control */ + gtt_write(gtt_bar, 0xa080, 0x00000004); + + /* 6: ECO bits */ + reg32 = gtt_read(gtt_bar, 0xa180); + reg32 |= (1 << 26) | (1 << 31); + /* (bit 20=1 for SNB step D1+ / IVB A0+) */ + if (bridge_silicon_revision() >= SNB_STEP_D1) + reg32 |= (1 << 20); + gtt_write(gtt_bar, 0xa180, reg32); + + /* 6a: for SnB step D2+ only */ + if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && + (bridge_silicon_revision() >= SNB_STEP_D2)) { + reg32 = gtt_read(gtt_bar, 0x9400); + reg32 |= (1 << 7); + gtt_write(gtt_bar, 0x9400, reg32); + + reg32 = gtt_read(gtt_bar, 0x941c); + reg32 &= 0xf; + reg32 |= (1 << 1); + gtt_write(gtt_bar, 0x941c, reg32); + gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1)); + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + reg32 = gtt_read(gtt_bar, 0x907c); + reg32 |= (1 << 16); + gtt_write(gtt_bar, 0x907c, reg32); + + /* 6b: Clocking reset controls */ + gtt_write(gtt_bar, 0x9424, 0x00000001); + } else { + /* 6b: Clocking reset controls */ + gtt_write(gtt_bar, 0x9424, 0x00000000); + } + + /* 7 */ + if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) { + gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */ + /* Mailbox Cmd for RC6 VID */ + gtt_write(gtt_bar, 0x138124, 0x80000004); + if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) + gtt_write(gtt_bar, 0x138124, 0x8000000a); + gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)); + } + + /* 8 */ + gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */ + gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ + gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ + gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ + gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */ + gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */ + + /* 9 */ + gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */ + gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */ + gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */ + + /* 10 */ + gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */ + gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */ + gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */ + gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */ + gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */ + + /* 11 */ + gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */ + gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */ + gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */ + gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */ + gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */ + gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */ + gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */ + + /* 11a: Enable Render Standby (RC6) */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* + * IvyBridge should also support DeepRenderStandby. + * + * Unfortunately it does not work reliably on all SKUs so + * disable it here and it can be enabled by the kernel. + */ + gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ + } else { + gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ + } + + /* 12: Normal Frequency Request */ + /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ + reg32 = readl(MCHBAR_REG(0x5998)); + reg32 >>= 16; + reg32 &= 0xef; + reg32 <<= 25; + gtt_write(gtt_bar, 0xa008, reg32); + + /* 13: RP Control */ + gtt_write(gtt_bar, 0xa024, 0x00000592); + + /* 14: Enable PM Interrupts */ + gtt_write(gtt_bar, 0x4402c, 0x03000076); + + /* Clear 0x6c024 [8:6] */ + reg32 = gtt_read(gtt_bar, 0x6c024); + reg32 &= ~0x000001c0; + gtt_write(gtt_bar, 0x6c024, reg32); + + return 0; +} + +int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node) +{ + u32 reg32, cycle_delay; + + debug("GT Power Management Init (post VBIOS)\n"); + + /* 15: Deassert Force Wake */ + if (bridge_silicon_revision() < IVB_STEP_C0) { + gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1); + gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0)); + } else { + gtt_write(gtt_bar, 0xa188, 0x1fffe); + if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) { + gtt_write(gtt_bar, 0xa188, + gtt_read(gtt_bar, 0xa188) | 1); + } + } + + /* 16: SW RC Control */ + gtt_write(gtt_bar, 0xa094, 0x00060000); + + /* Setup Digital Port Hotplug */ + reg32 = gtt_read(gtt_bar, 0xc4030); + if (!reg32) { + u32 dp_hotplug[3]; + + if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug", + dp_hotplug, ARRAY_SIZE(dp_hotplug))) + return -EINVAL; + + reg32 = (dp_hotplug[0] & 0x7) << 2; + reg32 |= (dp_hotplug[0] & 0x7) << 10; + reg32 |= (dp_hotplug[0] & 0x7) << 18; + gtt_write(gtt_bar, 0xc4030, reg32); + } + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(gtt_bar, 0xc7208); + if (!reg32) { + reg32 = (unsigned)fdtdec_get_int(blob, node, + "panel-port-select", 0) << 30; + reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0) + << 16; + reg32 |= fdtdec_get_int(blob, node, + "panel-power-backlight-on-delay", 0); + gtt_write(gtt_bar, 0xc7208, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(gtt_bar, 0xc720c); + if (!reg32) { + reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0) + << 16; + reg32 |= fdtdec_get_int(blob, node, + "panel-power-backlight-off-delay", 0); + gtt_write(gtt_bar, 0xc720c, reg32); + } + + /* Setup Panel Power Cycle Delay */ + cycle_delay = fdtdec_get_int(blob, node, + "intel,panel-power-cycle-delay", 0); + if (cycle_delay) { + reg32 = gtt_read(gtt_bar, 0xc7210); + reg32 &= ~0xff; + reg32 |= cycle_delay; + gtt_write(gtt_bar, 0xc7210, reg32); + } + + /* Enable Backlight if needed */ + reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0); + if (reg32) { + gtt_write(gtt_bar, 0x48250, (1 << 31)); + gtt_write(gtt_bar, 0x48254, reg32); + } + reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0); + if (reg32) { + gtt_write(gtt_bar, 0xc8250, (1 << 31)); + gtt_write(gtt_bar, 0xc8254, reg32); + } + + return 0; +} + +/* + * Some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + */ + +uint32_t board_map_oprom_vendev(uint32_t vendev) +{ + switch (vendev) { + case 0x80860102: /* GT1 Desktop */ + case 0x8086010a: /* GT1 Server */ + case 0x80860112: /* GT2 Desktop */ + case 0x80860116: /* GT2 Mobile */ + case 0x80860122: /* GT2 Desktop >=1.3GHz */ + case 0x80860126: /* GT2 Mobile >=1.3GHz */ + case 0x80860156: /* IVB */ + case 0x80860166: /* IVB */ + return 0x80860106; /* GT1 Mobile */ + } + + return vendev; +} + +static int int15_handler(void) +{ + int res = 0; + + debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX); + + switch (M.x86.R_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + M.x86.R_AX = 0x005f; + M.x86.R_CL = 0x00; /* Use video bios default */ + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; /* Use video bios default */ + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0003; /* eDP */ + res = 1; + break; + case 0x5f70: + switch (M.x86.R_CH) { + case 0: + /* Get Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + debug("Unknown INT15 5f70 function: 0x%02x\n", + M.x86.R_CH); + break; + } + break; + case 0x5fac: + res = 1; + break; + default: + debug("Unknown INT15 function %04x!\n", M.x86.R_AX); + break; + } + return res; +} + +int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, + const void *blob, int node) +{ + void *gtt_bar; + u32 reg32; + int ret; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0); + debug("GT bar %p\n", gtt_bar); + ret = gma_pm_init_pre_vbios(gtt_bar); + if (ret) + return ret; + + ret = pci_run_vga_bios(dev, int15_handler, false); + + /* Post VBIOS init */ + ret = gma_pm_init_post_vbios(gtt_bar, blob, node); + if (ret) + return ret; + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/gma.h b/arch/x86/cpu/ivybridge/gma.h new file mode 100644 index 0000000..e7ec649 --- /dev/null +++ b/arch/x86/cpu/ivybridge/gma.h @@ -0,0 +1,156 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2012 Chromium OS Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/* mailbox 0: header */ +__packed struct opregion_header { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +}; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +__packed struct opregion_mailbox1 { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +}; + +/* mailbox 2: software sci interface */ +__packed struct opregion_mailbox2 { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +}; + +/* mailbox 3: power conservation */ +__packed struct opregion_mailbox3 { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +}; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +__packed struct { + u8 gvd1[7168]; +} opregion_vbt_t; + +/* IGD OpRegion */ +__packed struct igd_opregion { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +}; + +/* Intel Video BIOS (Option ROM) */ +__packed struct optionrom_header { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +}; + +#define OPROM_SIGNATURE 0xaa55 + +__packed struct optionrom_pcir { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +}; + +__packed struct optionrom_vbt { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +}; + +#define VBT_SIGNATURE 0x54425624 diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index 96d51c2..e1d9a9b 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -13,6 +13,8 @@ void bd82x6x_pci_init(pci_dev_t dev); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int bd82x6x_init_pci_devices(void); +int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, + const void *blob, int node); int bd82x6x_init(void); struct x86_cpu_priv; -- cgit v1.1 From f3e56fe369ff80760955efb33abf316d4369955c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 20:56:37 -0700 Subject: x86: dts: Add video information to the device tree This provides panel timing information needed by the video driver. Signed-off-by: Simon Glass --- arch/x86/dts/link.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index d3c94e0..592af16 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -171,6 +171,19 @@ intel,sata-port0-gen3-tx = <0x00880a7f>; }; + gma { + compatible = "intel,gma"; + intel,dp_hotplug = <0 0 0x06>; + intel,panel-port-select = <1>; + intel,panel-power-cycle-delay = <6>; + intel,panel-power-up-delay = <2000>; + intel,panel-power-down-delay = <500>; + intel,panel-power-backlight-on-delay = <2000>; + intel,panel-power-backlight-off-delay = <2000>; + intel,cpu-backlight = <0x00000200>; + intel,pch-backlight = <0x04000000>; + }; + lpc { compatible = "intel,lpc"; #address-cells = <1>; -- cgit v1.1