From c415919d5790977b2d498105c5dc3475bb0895e6 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Sun, 4 Mar 2012 11:47:37 +0000 Subject: i.MX6: define CACHELINE_SIZE Signed-off-by: Eric Nelson Acked-by: Marek Vasut --- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index cad957a..1033d05 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -19,6 +19,8 @@ #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ #define __ASM_ARCH_MX6_IMX_REGS_H__ +#define CONFIG_SYS_CACHELINE_SIZE 32 + #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF #define CAAM_ARB_BASE_ADDR 0x00100000 -- cgit v1.1 From 4d422fe2dce90d1052c9ab133fe0059ff2e92394 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Sun, 4 Mar 2012 11:47:38 +0000 Subject: i.MX6: implement enable_caches() disabled by default until drivers are fixed Signed-off-by: Eric Nelson Acked-by: Marek Vasut --- arch/arm/cpu/armv7/mx6/soc.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index a81e2bc..543b2cc 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -85,6 +85,14 @@ int arch_cpu_init(void) } #endif +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + #if defined(CONFIG_FEC_MXC) void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { -- cgit v1.1 From 219872c8fe890cd280cf54f27df86504bb17d277 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Mon, 2 Apr 2012 06:18:00 +0000 Subject: ARM1136: add cache flush and invalidate operations Since commit 5c1ad3e6f8ae578bbe30e09652f1531e9bc22031 (net: fec_mxc: allow use with cache enabled) the FEC_MXC driver uses flush_dcache_range() and invalidate_dcache_range() functions. This driver is also configured for ARM1136 based 'flea3' and 'mx35pdk' boards which currently do not build as there are no ARM1136 specific flush_dcache_range() and invalidate_dcache_range() functions. Add various ARM1136 cache functions to fix building for 'flea3' and 'mx35pdk'. Signed-off-by: Anatolij Gustschin Signed-off-by: Stefano Babic Cc: Fabio Estevam CC: Mike Frysinger CC: Marek Vasut Acked-by: Marek Vasut --- arch/arm/cpu/arm1136/cpu.c | 95 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c index 2b91631..f2e30b5 100644 --- a/arch/arm/cpu/arm1136/cpu.c +++ b/arch/arm/cpu/arm1136/cpu.c @@ -75,3 +75,98 @@ static void cache_flush(void) asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ } + +#ifndef CONFIG_SYS_DCACHE_OFF + +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE 32 +#endif + +void invalidate_dcache_all(void) +{ + asm ("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); +} + +void flush_dcache_all(void) +{ + asm ("mcr p15, 0, %0, c7, c10, 0" : : "r" (0)); + asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +} + +static inline int bad_cache_range(unsigned long start, unsigned long stop) +{ + int ok = 1; + + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (!ok) + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + start, stop); + + return ok; +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + if (bad_cache_range(start, stop)) + return; + + while (start < stop) { + asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); + start += CONFIG_SYS_CACHELINE_SIZE; + } +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + if (bad_cache_range(start, stop)) + return; + + while (start < stop) { + asm ("mcr p15, 0, %0, c7, c14, 1" : : "r" (start)); + start += CONFIG_SYS_CACHELINE_SIZE; + } + + asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +void invalidate_dcache_all(void) +{ +} + +void flush_dcache_all(void) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_cache(unsigned long start, unsigned long size) +{ +} +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ -- cgit v1.1 From c8d9ceaf061c5ea5c17ee9e95dbff563e41904c0 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 2 Apr 2012 06:18:49 +0000 Subject: ARM: 926ejs: use debug() for misaligned addresses Misaligned warnings are useful to debug faulty drivers. A misaligned warning is printed also when the driver is correct - use debug() instead of printf(). Signed-off-by: Stefano Babic CC: Albert Aribaud CC: Mike Frysinger CC: Marek Vasut Acked-by: Marek Vasut --- arch/arm/cpu/arm926ejs/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 5b23e3a..4430578 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -55,7 +55,7 @@ static int check_cache_range(unsigned long start, unsigned long stop) ok = 0; if (!ok) - printf("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", start, stop); return ok; -- cgit v1.1 From a9407f2bc51ed118c47a2e60396466bba78c57a6 Mon Sep 17 00:00:00 2001 From: Vikram Narayanan Date: Tue, 10 Apr 2012 04:25:57 +0000 Subject: imx: Remove unneeded/repititive definitions from imx headers Remove gpio related unused/repititive definitions from imx headers. Signed-off-by: Vikram Narayanan Acked-by: Stefano Babic --- arch/arm/include/asm/arch-mx35/mx35_pins.h | 2 -- arch/arm/include/asm/arch-mx5/mx5x_pins.h | 2 -- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 -- 3 files changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h index 3676e33..8c38139 100644 --- a/arch/arm/include/asm/arch-mx35/mx35_pins.h +++ b/arch/arm/include/asm/arch-mx35/mx35_pins.h @@ -84,8 +84,6 @@ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) #define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) -#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) -#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) #define NON_GPIO_I 0x7 #define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h index 4e3a31b..122fbee 100644 --- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h +++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h @@ -78,8 +78,6 @@ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) #define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) -#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) -#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) #define NON_GPIO_PORT 0x7 #define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 1033d05..6d25c8d 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -170,8 +170,6 @@ #define FEC_QUIRK_ENET_MAC #define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31)) -#define GPIO_TO_PORT(number) (((number)/32)+1) -#define GPIO_TO_INDEX(number) ((number)&31) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include -- cgit v1.1 From 96666a39aed47c8c643dc7c6a6e15e314e63f42b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 8 Apr 2012 17:34:46 +0000 Subject: DMA: Split the APBH DMA init into block and channel init This fixes the issue where mxs_dma_init() was called either twice or never, without introducing any new init hooks. The idea is to allow each and every device using the APBH DMA block to configure and request only the channels it uses, instead of making it call init for all the channels as is now. The common DMA block init part, which only configures the block, is then called from CPUs arch_cpu_init() call. NOTE: This patch depends on: http://patchwork.ozlabs.org/patch/150957/ Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Wolfgang Denk Cc: Detlev Zundel Cc: Fabio Estevam Tested-by: Fabio Estevam --- arch/arm/cpu/arm926ejs/mx28/mx28.c | 6 ++++++ arch/arm/include/asm/arch-mx28/dma.h | 4 +++- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index cf6d4e9..dc0338d 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -172,6 +173,11 @@ int arch_cpu_init(void) */ mxs_gpio_init(); +#ifdef CONFIG_APBH_DMA + /* Start APBH DMA */ + mxs_dma_init(); +#endif + return 0; } #endif diff --git a/arch/arm/include/asm/arch-mx28/dma.h b/arch/arm/include/asm/arch-mx28/dma.h index 52747e2..4a1820b 100644 --- a/arch/arm/include/asm/arch-mx28/dma.h +++ b/arch/arm/include/asm/arch-mx28/dma.h @@ -140,6 +140,8 @@ void mxs_dma_desc_free(struct mxs_dma_desc *); int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); int mxs_dma_go(int chan); -int mxs_dma_init(void); +void mxs_dma_init(void); +int mxs_dma_init_channel(int chan); +int mxs_dma_release(int chan); #endif /* __DMA_H__ */ -- cgit v1.1 From 38fcc71cc58b1c9a224b707b03eb6574cb2dc027 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 3 Apr 2012 04:32:56 +0000 Subject: ARM: add u-boot.imx as target for i.MX SOCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Freescale SOCs require an header to u-boot.bin The patch adds u-boot.imx to the default targets if the imx file is set (IMX_CONFIG). Signed-off-by: Stefano Babic Cc: Albert ARIBAUD CC: Loïc Minier CC: Mike Frysinger Acked-by: Mike Frysinger Acked-by: Dirk Behme Tested-by: Dirk Behme --- arch/arm/cpu/armv7/config.mk | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 83ddf10..f532d62 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -31,3 +31,6 @@ PLATFORM_CPPFLAGS += -march=armv5 # ========================================================================= PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) +ifneq ($(CONFIG_IMX_CONFIG),) +ALL-y += $(obj)u-boot.imx +endif -- cgit v1.1 From fbf4a074e0b7eb4864836084eff2a747617be0b4 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 9 Apr 2012 13:33:04 +0200 Subject: ARM1136: MX35: Make asm routines volatile in cache ops As well as pushed for ARM926EJS, we certainly don't want the compiler to reorganise the code for dcache flushing Fix checkpatch warnings as well. Signed-off-by: Stefano Babic CC: Marek Vasut CC: Albert Aribaud --- arch/arm/cpu/arm1136/cpu.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c index f2e30b5..f72bab6 100644 --- a/arch/arm/cpu/arm1136/cpu.c +++ b/arch/arm/cpu/arm1136/cpu.c @@ -70,10 +70,12 @@ int cleanup_before_linux (void) static void cache_flush(void) { unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */ - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ + /* clean entire data cache */ + asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i)); + /* invalidate both caches and flush btb */ + asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i)); + /* mem barrier to sync things */ + asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); } #ifndef CONFIG_SYS_DCACHE_OFF @@ -84,13 +86,13 @@ static void cache_flush(void) void invalidate_dcache_all(void) { - asm ("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); + asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); } void flush_dcache_all(void) { - asm ("mcr p15, 0, %0, c7, c10, 0" : : "r" (0)); - asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); + asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); } static inline int bad_cache_range(unsigned long start, unsigned long stop) @@ -116,7 +118,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) return; while (start < stop) { - asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); + asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); start += CONFIG_SYS_CACHELINE_SIZE; } } @@ -127,11 +129,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop) return; while (start < stop) { - asm ("mcr p15, 0, %0, c7, c14, 1" : : "r" (start)); + asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start)); start += CONFIG_SYS_CACHELINE_SIZE; } - asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); } void flush_cache(unsigned long start, unsigned long size) -- cgit v1.1 From c6201553ba73616eed0f416f66d28c39691692bd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 6 Apr 2012 03:25:06 +0000 Subject: ARM926EJS: Make asm routines volatile in cache ops We certainly don't want the compiler to reorganise the code for dcache flushing. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Albert ARIBAUD Acked-by: Mike Frysinger Acked-by: Stefano Babic --- arch/arm/cpu/arm926ejs/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 4430578..07f036f 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -82,7 +82,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) start += CONFIG_SYS_CACHELINE_SIZE; } - asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); } void flush_cache(unsigned long start, unsigned long size) -- cgit v1.1 From 2694bb9bcc8ca9636faf38c866dda7bf0529e35f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 6 Apr 2012 03:25:07 +0000 Subject: ARM926EJS: Fix cache.c to comply with checkpatch.pl Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Albert ARIBAUD --- arch/arm/cpu/arm926ejs/cache.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 07f036f..2740ad7 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -30,7 +30,7 @@ void invalidate_dcache_all(void) { - asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); } void flush_dcache_all(void) @@ -40,7 +40,7 @@ void flush_dcache_all(void) "mrc p15, 0, r15, c7, c14, 3\n" "bne 0b\n" "mcr p15, 0, %0, c7, c10, 4\n" - ::"r"(0):"memory" + : : "r"(0) : "memory" ); } @@ -67,7 +67,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) return; while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start)); + asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); start += CONFIG_SYS_CACHELINE_SIZE; } } @@ -78,11 +78,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop) return; while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start)); + asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start)); start += CONFIG_SYS_CACHELINE_SIZE; } - asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0)); } void flush_cache(unsigned long start, unsigned long size) @@ -114,8 +114,7 @@ void flush_cache(unsigned long start, unsigned long size) /* * Stub implementations for l2 cache operations */ -void __l2_cache_disable(void) -{ -} +void __l2_cache_disable(void) {} + void l2_cache_disable(void) - __attribute__((weak, alias("__l2_cache_disable"))); + __attribute__((weak, alias("__l2_cache_disable"))); -- cgit v1.1