From a8535c306c68eb050ad0835845ea87a856b192f1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 11 Aug 2015 00:49:09 +0200 Subject: arm: socfpga: Fix delay in freeze controller Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/freeze_controller.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 0be643c..2b16795 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -7,8 +7,8 @@ #include #include +#include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -112,6 +112,7 @@ void sys_mgr_frzctrl_thaw_req(void) u32 reg_cfg_mask; u32 reg_value; u32 channel_id; + unsigned long eosc1_freq; /* select software FSM */ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); @@ -162,12 +163,9 @@ void sys_mgr_frzctrl_thaw_req(void) setbits_le32(&freeze_controller_base->hioctrl, SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); - /* - * Delay 1000 intosc. intosc is based on eosc1 - * Use worst case which is fatest eosc1=50MHz, delay required - * is 1/50MHz * 1000 = 20us - */ - udelay(20); + /* Delay 1000 intosc cycles. The intosc is based on eosc1. */ + eosc1_freq = cm_get_osc_clk_hz(1) / 1000; /* kHz */ + udelay(DIV_ROUND_UP(1000000, eosc1_freq)); /* * de-assert active low bhniotri signals, -- cgit v1.1 From 7e4d2fa2ed2ddf80121372db0282315dc9850a1b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 11 Aug 2015 00:54:12 +0200 Subject: arm: socfpga: Fix delay in clock manager This code claims it needs to wait 7us, yet it uses get_timer() function which operates with millisecond granularity. Use timer_get_us() instead, which operates with microsecond granularity. Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/clock_manager.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 1341df4..aa71636 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -90,7 +90,7 @@ static void cm_write_with_phase(uint32_t value, void cm_basic_init(const struct cm_config * const cfg) { - uint32_t start, timeout; + unsigned long end; /* Start by being paranoid and gate all sw managed clocks */ @@ -159,12 +159,10 @@ void cm_basic_init(const struct cm_config * const cfg) writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); /* - * Time starts here - * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) + * Time starts here. Must wait 7 us from + * BGPWRDN_SET(0) to VCO_ENABLE_SET(1). */ - start = get_timer(0); - /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ - timeout = 7; + end = timer_get_us() + 7; /* main mpu */ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); @@ -204,7 +202,7 @@ void cm_basic_init(const struct cm_config * const cfg) writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); /* 7 us must have elapsed before we can enable the VCO */ - while (get_timer(start) < timeout) + while (timer_get_us() < end) ; /* Enable vco */ -- cgit v1.1 From afe139938a75402a4287634c4d46b25e07cf79c0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 2 Aug 2015 22:55:24 +0200 Subject: arm: socfpga: Make the DT mmc node consistent The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node. This makes aliases not very usable, so make everything into mmc0. Moreover, zap the useless mmc alias while at this. Signed-off-by: Marek Vasut --- arch/arm/dts/socfpga.dtsi | 3 +-- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index e17e9f4..ded3093 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -23,7 +23,6 @@ spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; - mmc = &mmc; }; cpus { @@ -621,7 +620,7 @@ arm,data-latency = <2 1 1>; }; - mmc: dwmmc0@ff704000 { + mmc0: dwmmc0@ff704000 { compatible = "altr,socfpga-dw-mshc"; reg = <0xff704000 0x1000>; interrupts = <0 139 4>; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 00b1830..3c98558 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -34,7 +34,7 @@ }; }; -&mmc { +&mmc0 { status = "okay"; }; -- cgit v1.1 From c2624240dd9321b0fd86dba5ecf75d7a73974796 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Aug 2015 15:32:37 +0200 Subject: arm: socfpga: Do not enable gmac1 in Cyclone V dtsi The GMAC which is enabled is purely board property, so do not enable arbitrary GMAC in DT include files. Same goes for PHY mode, which is again a board property. The CycloneV SoCDK does this correctly, but SoCrates doesn't. This bug never manifested itself though, since all the boards ever used the GMAC1 . This bug manifests itself only on boards that utilise GMAC0. Signed-off-by: Marek Vasut --- arch/arm/dts/socfpga_cyclone5.dtsi | 6 ------ arch/arm/dts/socfpga_cyclone5_socrates.dts | 1 + 2 files changed, 1 insertion(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index 234a901..de36209 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -27,12 +27,6 @@ cap-sd-highspeed; }; - ethernet@ff702000 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - status = "okay"; - }; - sysmgr@ffd08000 { cpu1-start-addr = <0xffd080c4>; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 3c98558..6782691 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -23,6 +23,7 @@ &gmac1 { status = "okay"; + phy-mode = "rgmii"; }; &i2c0 { -- cgit v1.1 From ca62d2e1fca4e89b1e15e6bdc634f6ef39a7360d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 2 Aug 2015 21:12:09 +0200 Subject: arm: socfpga: Move wrappers into platform directory Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable. Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/Makefile | 9 + arch/arm/mach-socfpga/wrap_iocsr_config.c | 41 ++++ arch/arm/mach-socfpga/wrap_pinmux_config.c | 35 ++++ arch/arm/mach-socfpga/wrap_pll_config.c | 144 +++++++++++++ arch/arm/mach-socfpga/wrap_sdram_config.c | 316 +++++++++++++++++++++++++++++ 5 files changed, 545 insertions(+) create mode 100644 arch/arm/mach-socfpga/wrap_iocsr_config.c create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config.c create mode 100644 arch/arm/mach-socfpga/wrap_pll_config.c create mode 100644 arch/arm/mach-socfpga/wrap_sdram_config.c (limited to 'arch') diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 8a745c9..316b326 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -10,3 +10,12 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o scan_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o + +# QTS-generated config file wrappers +obj-y += wrap_pll_config.o +obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ + wrap_sdram_config.o +CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) +CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR) +CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR) +CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c new file mode 100644 index 0000000..31b5426 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +/* + * Yes, dear reader, we're including a C file here, this is no mistake :-) + */ +#include + +int iocsr_get_config_table(const unsigned int chain_id, + const unsigned long **table, + unsigned int *table_len) +{ + switch (chain_id) { + case 0: + *table = iocsr_scan_chain0_table; + *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH; + break; + case 1: + *table = iocsr_scan_chain1_table; + *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH; + break; + case 2: + *table = iocsr_scan_chain2_table; + *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH; + break; + case 3: + *table = iocsr_scan_chain3_table; + *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH; + break; + default: + return -EINVAL; + } + + return 0; +} diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config.c b/arch/arm/mach-socfpga/wrap_pinmux_config.c new file mode 100644 index 0000000..688f1e4 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_pinmux_config.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +/* + * Yes, dear reader, we're including a C file here, this is no mistake. + * But this time around, we do even more perverse hacking here to be + * compatible with QTS headers and obtain reasonably nice results too. + * + * First, we define _PRELOADER_PINMUX_CONFIG_H_, which will neutralise + * the pinmux_config.h inclusion in pinmux_config.c . Since we are + * probing everything from DT, we do NOT want those macros from the + * pinmux_config.h to ooze into our build system, anywhere, ever. So + * we nip it at the bud. + * + * Next, pinmux_config.c needs CONFIG_HPS_PINMUX_NUM and uses it to + * specify sized array explicitly. Instead, we want to use ARRAY_SIZE + * to figure out the size of the array, so define this macro as an + * empty one, so that the preprocessor optimizes things such that the + * arrays are not sized by default. + */ +#define _PRELOADER_PINMUX_CONFIG_H_ +#define CONFIG_HPS_PINMUX_NUM +#include + +void sysmgr_get_pinmux_table(const unsigned long **table, + unsigned int *table_len) +{ + *table = sys_mgr_init_table; + *table_len = ARRAY_SIZE(sys_mgr_init_table); +} diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c new file mode 100644 index 0000000..8a0a0e6 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define MAIN_VCO_BASE ( \ + (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \ + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \ + ) + +#define PERI_VCO_BASE ( \ + (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \ + CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \ + (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \ + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \ + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \ + ) + +#define SDR_VCO_BASE ( \ + (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \ + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \ + (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \ + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \ + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ + ) + +static const struct cm_config cm_default_cfg = { + /* main group */ + MAIN_VCO_BASE, + (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT << + CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT << + CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT << + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT << + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT << + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT << + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK << + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK << + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK << + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP << + CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP << + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET), + + /* peripheral group */ + PERI_VCO_BASE, + (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT << + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT << + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT << + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT << + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT << + CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT << + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_DIV_USBCLK << + CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK << + CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK << + CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK << + CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET), + (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK << + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET), + (CONFIG_HPS_PERPLLGRP_SRC_QSPI << + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) | + (CONFIG_HPS_PERPLLGRP_SRC_NAND << + CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) | + (CONFIG_HPS_PERPLLGRP_SRC_SDMMC << + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET), + + /* sdram pll group */ + SDR_VCO_BASE, + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE << + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT << + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE << + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT << + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE << + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT << + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE << + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET), +}; + +const struct cm_config * const cm_get_default_config(void) +{ + return &cm_default_cfg; +} + +const unsigned int cm_get_osc_clk_hz(const int osc) +{ + if (osc == 1) + return CONFIG_HPS_CLK_OSC1_HZ; + else if (osc == 2) + return CONFIG_HPS_CLK_OSC2_HZ; + else + return 0; +} + +const unsigned int cm_get_f2s_per_ref_clk_hz(void) +{ + return CONFIG_HPS_CLK_F2S_PER_REF_HZ; +} + +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void) +{ + return CONFIG_HPS_CLK_F2S_SDR_REF_HZ; +} diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c new file mode 100644 index 0000000..72ce565 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -0,0 +1,316 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +/* QTS output file. */ +#include + +#include +#include +#include +#include + +static const struct socfpga_sdram_config sdram_config = { + .ctrl_cfg = + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB), + .dram_timing1 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB), + .dram_timing2 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB), + .dram_timing3 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB), + .dram_timing4 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB), + .lowpwr_timing = + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB), + .dram_odt = + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << + SDR_CTRLGRP_DRAMODT_READ_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << + SDR_CTRLGRP_DRAMODT_WRITE_LSB), + .dram_addrw = + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | + ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB), + .dram_if_width = + (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << + SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB), + .dram_dev_width = + (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << + SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB), + .dram_intr = + (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << + SDR_CTRLGRP_DRAMINTR_INTREN_LSB), + .lowpwr_eq = + (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << + SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB), + .static_cfg = + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << + SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << + SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB), + .ctrl_width = + (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << + SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB), + .cport_width = + (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << + SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB), + .cport_wmap = + (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << + SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB), + .cport_rmap = + (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << + SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB), + .rfifo_cmap = + (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << + SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB), + .wfifo_cmap = + (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << + SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB), + .cport_rdwr = + (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << + SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB), + .port_cfg = + (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << + SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB), + .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST, + .fifo_cfg = + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << + SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB), + .mp_priority = + (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << + SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB), + .mp_weight0 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB), + .mp_weight1 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB), + .mp_weight2 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB), + .mp_weight3 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB), + .mp_pacing0 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << + SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB), + .mp_pacing1 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB), + .mp_pacing2 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << + SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB), + .mp_pacing3 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << + SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB), + .mp_threshold0 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << + SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB), + .mp_threshold1 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << + SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB), + .mp_threshold2 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << + SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB), + .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0, +}; + +static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { + .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1, + .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1, + .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2, + .activate_1 = RW_MGR_ACTIVATE_1, + .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE, + .guaranteed_read = RW_MGR_GUARANTEED_READ, + .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT, + .guaranteed_write = RW_MGR_GUARANTEED_WRITE, + .guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0, + .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1, + .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2, + .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3, + .idle = RW_MGR_IDLE, + .idle_loop1 = RW_MGR_IDLE_LOOP1, + .idle_loop2 = RW_MGR_IDLE_LOOP2, + .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0, + .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0, + .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0, + .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA, + .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS, + .lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP, + .lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT, + .lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1, + .lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0, + .lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA, + .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS, + .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, + .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, + .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1, + .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET, + .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR, + .mrs0_user = RW_MGR_MRS0_USER, + .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR, + .mrs1 = RW_MGR_MRS1, + .mrs1_mirr = RW_MGR_MRS1_MIRR, + .mrs2 = RW_MGR_MRS2, + .mrs2_mirr = RW_MGR_MRS2_MIRR, + .mrs3 = RW_MGR_MRS3, + .mrs3_mirr = RW_MGR_MRS3_MIRR, + .precharge_all = RW_MGR_PRECHARGE_ALL, + .read_b2b = RW_MGR_READ_B2B, + .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1, + .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2, + .refresh_all = RW_MGR_REFRESH_ALL, + .rreturn = RW_MGR_RETURN, + .sgle_read = RW_MGR_SGLE_READ, + .zqcl = RW_MGR_ZQCL, + + .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH, + .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING, + .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH, + .mem_data_width = RW_MGR_MEM_DATA_WIDTH, + .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS, + .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS, + .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH, + .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH, + .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM, + .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS, + .mem_virtual_groups_per_read_dqs = + RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS, + .mem_virtual_groups_per_write_dqs = + RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS, +}; + +struct socfpga_sdram_io_config io_config = { + .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP, + .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP, + .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP, + .dll_chain_length = IO_DLL_CHAIN_LENGTH, + .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX, + .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX, + .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET, + .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX, + .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX, + .dqs_in_reserve = IO_DQS_IN_RESERVE, + .dqs_out_reserve = IO_DQS_OUT_RESERVE, + .io_in_delay_max = IO_IO_IN_DELAY_MAX, + .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX, + .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX, + .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS, +}; + +struct socfpga_sdram_misc_config misc_config = { + .afi_rate_ratio = AFI_RATE_RATIO, + .calib_lfifo_offset = CALIB_LFIFO_OFFSET, + .calib_vfifo_offset = CALIB_VFIFO_OFFSET, + .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION, + .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH, + .read_valid_fifo_size = READ_VALID_FIFO_SIZE, + .reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE, + .tinit_cntr0_val = TINIT_CNTR0_VAL, + .tinit_cntr1_val = TINIT_CNTR1_VAL, + .tinit_cntr2_val = TINIT_CNTR2_VAL, + .treset_cntr0_val = TRESET_CNTR0_VAL, + .treset_cntr1_val = TRESET_CNTR1_VAL, + .treset_cntr2_val = TRESET_CNTR2_VAL, +}; + +const struct socfpga_sdram_config *socfpga_get_sdram_config(void) +{ + return &sdram_config; +} + +void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem) +{ + *init = ac_rom_init; + *nelem = ARRAY_SIZE(ac_rom_init); +} + +void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem) +{ + *init = inst_rom_init; + *nelem = ARRAY_SIZE(inst_rom_init); +} + +const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void) +{ + return &rw_mgr_config; +} + +const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void) +{ + return &io_config; +} + +const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void) +{ + return &misc_config; +} -- cgit v1.1 From cd9b73177100598e7be0a9033a4a2ed4a7d24fbb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 2 Aug 2015 21:57:57 +0200 Subject: arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/Kconfig | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index e46c348..1a441ff 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,28 +1,38 @@ if ARCH_SOCFPGA +config TARGET_SOCFPGA_ARRIA5 + bool + +config TARGET_SOCFPGA_CYCLONE5 + bool + choice prompt "Altera SOCFPGA board select" optional -config TARGET_SOCFPGA_ARRIA5 - bool "Altera SOCFPGA Arria V" +config TARGET_SOCFPGA_ARRIA5_SOCDK + bool "Altera SOCFPGA SoCDK (Arria V)" + select TARGET_SOCFPGA_ARRIA5 -config TARGET_SOCFPGA_CYCLONE5 - bool "Altera SOCFPGA Cyclone V" +config TARGET_SOCFPGA_CYCLONE5_SOCDK + bool "Altera SOCFPGA SoCDK (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 endchoice config SYS_BOARD - default "socfpga" + default "socfpga" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga" if TARGET_SOCFPGA_CYCLONE5_SOCDK config SYS_VENDOR - default "altera" + default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK config SYS_SOC default "socfpga" config SYS_CONFIG_NAME - default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5 - default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5 + default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK endif -- cgit v1.1 From f089240128329fe6a49a5272aef732b47613c2f5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 10 Aug 2015 21:24:53 +0200 Subject: arm: socfpga: Split Altera socfpga into AV and CV SoCDK The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1a441ff..690e362 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -21,8 +21,8 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK endchoice config SYS_BOARD - default "socfpga" if TARGET_SOCFPGA_ARRIA5_SOCDK - default "socfpga" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK -- cgit v1.1 From e996b9362b26c62e7f1264c51714aade48727a0b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 10 Aug 2015 20:48:07 +0200 Subject: arm: socfpga: Add qts-filter.sh script Add script which loads the QTS-generated sources and headers and converts them into sensible format which can be used with much more easy in mainline U-Boot. The script also filters out macros which makes no sense anymore, so they don't pollute namespace and waste space. Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/qts-filter.sh | 205 ++++++++++++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100755 arch/arm/mach-socfpga/qts-filter.sh (limited to 'arch') diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh new file mode 100755 index 0000000..16d3a2a --- /dev/null +++ b/arch/arm/mach-socfpga/qts-filter.sh @@ -0,0 +1,205 @@ +#!/bin/sh + +# +# Process iocsr_config_*.[ch] +# $1: SoC type +# $2: Input directory +# $3: Output directory +# +process_iocsr_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +EOF + + # Retrieve the scan chain lengths + grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \ + ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()" + + echo "" + + # Retrieve the scan chain config and zap the ad-hoc length encoding + sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \ + ${in_dir}/generated/iocsr_config_${soc}.c + + cat << EOF + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ +EOF + ) > "${out_dir}/iocsr_config.h" +} + +# +# Process pinmux_config_*.c (and ignore pinmux_config.h) +# $1: SoC type +# $2: Input directory +# $3: Output directory +# +process_pinmux_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +EOF + + # Retrieve the pinmux config and zap the ad-hoc length encoding + sed -n '/^unsigned/ !b; :next {/^unsigned/ s/\[.*\]/[]/;p;n;b next}' \ + ${in_dir}/generated/pinmux_config_${soc}.c + + cat << EOF + +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ +EOF + ) > "${out_dir}/pinmux_config.h" +} + +# +# Process pll_config.h +# $1: SoC type (not used) +# $2: Input directory +# $3: Output directory +# +process_pll_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +EOF + + # Retrieve the pll config and zap parenthesis + sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \ + ${in_dir}/generated/pll_config.h + + cat << EOF + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ +EOF + ) > "${out_dir}/pll_config.h" +} + +# +# Filter out only the macros which are actually used by the code +# +grep_sdram_config() { + egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL)[[:space:]]" +} + +# +# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h +# $1: SoC type (not used) +# $2: Input directory +# $3: Output directory +# +process_sdram_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +EOF + + echo "/* SDRAM configuration */" + # Retrieve the sdram config, zap broken lines and zap parenthesis + sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" ${in_dir}/generated/sdram/sdram_config.h | + sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' | + sort -u | grep_sdram_config + + echo "" + echo "/* Sequencer auto configuration */" + sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ + ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u | grep_sdram_config + + echo "" + echo "/* Sequencer defines configuration */" + sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ + ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u | grep_sdram_config + + echo "" + echo "/* Sequencer ac_rom_init configuration */" + sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ + ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c + + echo "" + echo "/* Sequencer inst_rom_init configuration */" + sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ + ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c + + cat << EOF + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ +EOF + ) > "${out_dir}/sdram_config.h" +} + +usage() { + echo "$0 [soc_type] [input_dir] [output_dir]" + echo "Process QTS-generated headers into U-Boot compatible ones." + echo "" + echo " soc_type\t\tType of SoC, either 'cyclone5' or 'arria5'," + echo " input_dir\t\tDirectory with the QTS project." + echo " output_dir\t\tDirectory to store the U-Boot compatible headers." + echo "" +} + +soc="$1" +in_dir="$2" +out_dir="$3" + +if [ "$#" -ne 3 ] ; then + usage + exit 1 +fi + +if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then + usage + exit 3 +fi + +process_iocsr_config "${soc}" "${in_dir}" "${out_dir}" +process_pinmux_config "${soc}" "${in_dir}" "${out_dir}" +process_pll_config "${soc}" "${in_dir}" "${out_dir}" +process_sdram_config "${soc}" "${in_dir}" "${out_dir}" -- cgit v1.1 From f6badb0d89ae1221c8aa83138632613f91a48715 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 10 Aug 2015 21:21:07 +0200 Subject: arm: socfpga: Switch to filtered QTS files Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/wrap_iocsr_config.c | 7 +++---- arch/arm/mach-socfpga/wrap_pinmux_config.c | 23 +++-------------------- arch/arm/mach-socfpga/wrap_sdram_config.c | 8 ++------ 3 files changed, 8 insertions(+), 30 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c index 31b5426..5e3f057 100644 --- a/arch/arm/mach-socfpga/wrap_iocsr_config.c +++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c @@ -7,10 +7,9 @@ #include #include #include -/* - * Yes, dear reader, we're including a C file here, this is no mistake :-) - */ -#include + +/* Board-specific header. */ +#include int iocsr_get_config_table(const unsigned int chain_id, const unsigned long **table, diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config.c b/arch/arm/mach-socfpga/wrap_pinmux_config.c index 688f1e4..bcb7781 100644 --- a/arch/arm/mach-socfpga/wrap_pinmux_config.c +++ b/arch/arm/mach-socfpga/wrap_pinmux_config.c @@ -6,26 +6,9 @@ #include #include -/* - * Yes, dear reader, we're including a C file here, this is no mistake. - * But this time around, we do even more perverse hacking here to be - * compatible with QTS headers and obtain reasonably nice results too. - * - * First, we define _PRELOADER_PINMUX_CONFIG_H_, which will neutralise - * the pinmux_config.h inclusion in pinmux_config.c . Since we are - * probing everything from DT, we do NOT want those macros from the - * pinmux_config.h to ooze into our build system, anywhere, ever. So - * we nip it at the bud. - * - * Next, pinmux_config.c needs CONFIG_HPS_PINMUX_NUM and uses it to - * specify sized array explicitly. Instead, we want to use ARRAY_SIZE - * to figure out the size of the array, so define this macro as an - * empty one, so that the preprocessor optimizes things such that the - * arrays are not sized by default. - */ -#define _PRELOADER_PINMUX_CONFIG_H_ -#define CONFIG_HPS_PINMUX_NUM -#include + +/* Board-specific header. */ +#include void sysmgr_get_pinmux_table(const unsigned long **table, unsigned int *table_len) diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index 72ce565..31cc7de 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -7,13 +7,9 @@ #include #include #include -/* QTS output file. */ -#include -#include -#include -#include -#include +/* Board-specific header. */ +#include static const struct socfpga_sdram_config sdram_config = { .ctrl_cfg = -- cgit v1.1 From cc9429a5562489cf8a4eb0d722c36e1bdfde4907 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 10 Aug 2015 22:17:46 +0200 Subject: arm: socfpga: Make the pinmux table const u8 Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array. Signed-off-by: Marek Vasut --- arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +-- arch/arm/mach-socfpga/qts-filter.sh | 2 +- arch/arm/mach-socfpga/system_manager.c | 2 +- arch/arm/mach-socfpga/wrap_pinmux_config.c | 3 +-- 4 files changed, 4 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 46af30b..8712f8e 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -12,8 +12,7 @@ void sysmgr_pinmux_init(void); void sysmgr_config_warmrstcfgio(int enable); -void sysmgr_get_pinmux_table(const unsigned long **table, - unsigned int *table_len); +void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); #endif struct socfpga_system_manager { diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh index 16d3a2a..c1640bc 100755 --- a/arch/arm/mach-socfpga/qts-filter.sh +++ b/arch/arm/mach-socfpga/qts-filter.sh @@ -66,7 +66,7 @@ process_pinmux_config() { EOF # Retrieve the pinmux config and zap the ad-hoc length encoding - sed -n '/^unsigned/ !b; :next {/^unsigned/ s/\[.*\]/[]/;p;n;b next}' \ + sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \ ${in_dir}/generated/pinmux_config_${soc}.c cat << EOF diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 744ec32..75a65f3 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -57,7 +57,7 @@ static void populate_sysmgr_fpgaintf_module(void) void sysmgr_pinmux_init(void) { uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0]; - const unsigned long *sys_mgr_init_table; + const u8 *sys_mgr_init_table; unsigned int len; int i; diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config.c b/arch/arm/mach-socfpga/wrap_pinmux_config.c index bcb7781..a12f0b3 100644 --- a/arch/arm/mach-socfpga/wrap_pinmux_config.c +++ b/arch/arm/mach-socfpga/wrap_pinmux_config.c @@ -10,8 +10,7 @@ /* Board-specific header. */ #include -void sysmgr_get_pinmux_table(const unsigned long **table, - unsigned int *table_len) +void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len) { *table = sys_mgr_init_table; *table_len = ARRAY_SIZE(sys_mgr_init_table); -- cgit v1.1 From 660f53bc1af16064e2f65b8b6672c8d5a33b84f0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 10 Aug 2015 17:20:23 +0200 Subject: arm: socfpga: dts: Add bank-name property to each GPIO bank Add "bank-name" property to each GPIO bank to give it unique name. The approach here is exactly the same as with the "regulator-name" property for regulators. Signed-off-by: Marek Vasut --- arch/arm/dts/socfpga.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index ded3093..8588221 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -549,6 +549,7 @@ porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; + bank-name = "porta"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -569,6 +570,7 @@ portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; + bank-name = "portb"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -589,6 +591,7 @@ portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; + bank-name = "portc"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <27>; -- cgit v1.1 From 476a36032ddddca940db756da0a33a4245cc327d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Aug 2015 07:43:19 +0200 Subject: arm: socfpga: Fix SD/MMC boot on ArriaV SoCDK Add the missing DT nodes, so that ArriaV SoCDK can boot from SD card. The SD card must be in slot J5 and BSEL must be 0x5. Signed-off-by: Marek Vasut --- arch/arm/dts/socfpga_arria5_socdk.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index f2b5963..7d1836e 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -33,6 +33,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { @@ -67,6 +71,8 @@ &mmc0 { vmmc-supply = <®ulator_3_3v>; vqmmc-supply = <®ulator_3_3v>; + bus-width = <4>; + u-boot,dm-pre-reloc; }; &usb1 { -- cgit v1.1