From 2967af6816a2b5b549a3377edf41781a51d00003 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Fri, 18 Oct 2013 12:30:21 +0530 Subject: powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain [York Sun: fixed Makefiles] Acked-by: York Sun --- arch/powerpc/cpu/mpc85xx/Makefile | 10 ++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 3 ++- arch/powerpc/include/asm/immap_85xx.h | 3 ++- 3 files changed, 14 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 50ddb50..a34014f 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -70,6 +70,9 @@ obj-$(CONFIG_PPC_B4860) += ddr-gen3.o obj-$(CONFIG_BSC9131) += ddr-gen3.o obj-$(CONFIG_BSC9132) += ddr-gen3.o obj-$(CONFIG_PPC_T1040) += ddr-gen3.o +obj-$(CONFIG_PPC_T1042) += ddr-gen3.o +obj-$(CONFIG_PPC_T1020) += ddr-gen3.o +obj-$(CONFIG_PPC_T1022) += ddr-gen3.o obj-$(CONFIG_CPM2) += ether_fcc.o obj-$(CONFIG_OF_LIBFDT) += fdt.o @@ -89,6 +92,10 @@ obj-$(CONFIG_PPC_T4160) += t4240_ids.o obj-$(CONFIG_PPC_B4420) += b4860_ids.o obj-$(CONFIG_PPC_B4860) += b4860_ids.o obj-$(CONFIG_PPC_T1040) += t1040_ids.o +obj-$(CONFIG_PPC_T1042) += t1040_ids.o +obj-$(CONFIG_PPC_T1020) += t1040_ids.o +obj-$(CONFIG_PPC_T1022) += t1040_ids.o + obj-$(CONFIG_QE) += qe_io.o obj-$(CONFIG_CPM2) += serial_scc.o @@ -128,6 +135,9 @@ obj-$(CONFIG_PPC_B4420) += b4860_serdes.o obj-$(CONFIG_PPC_B4860) += b4860_serdes.o obj-$(CONFIG_BSC9132) += bsc9132_serdes.o obj-$(CONFIG_PPC_T1040) += t1040_serdes.o +obj-$(CONFIG_PPC_T1042) += t1040_serdes.o +obj-$(CONFIG_PPC_T1020) += t1040_serdes.o +obj-$(CONFIG_PPC_T1022) += t1040_serdes.o obj-y += cpu.o obj-y += cpu_init.o diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4cc12ee..d4cd27d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -674,7 +674,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #endif -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 060e0d7..3e76c54 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1847,7 +1847,8 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 -- cgit v1.1 From 4e2e0df94d606531927e411123ae5ce3d2aed49c Mon Sep 17 00:00:00 2001 From: ramneek mehresh Date: Sat, 19 Oct 2013 19:33:04 +0530 Subject: powerpc/83xx: Define USB1 and USB2 base addr for MPC834x Define base addresse for both MPH(USB1) and DR(USB2) controllers for MPC834x socs Signed-off-by: Ramneek Mehresh --- arch/powerpc/include/asm/immap_83xx.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 3c86ff6..289f7ca 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -763,6 +763,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; +#ifndef CONFIG_MPC834x #ifdef CONFIG_HAS_FSL_MPH_USB #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 @@ -770,6 +771,10 @@ typedef struct immap { #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ #endif +#else +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 +#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 +#endif #elif defined(CONFIG_MPC8313) typedef struct immap { -- cgit v1.1 From b4125a235e2c4a490765292a95b47008036a4e0d Mon Sep 17 00:00:00 2001 From: Laurentiu TUDOR Date: Wed, 23 Oct 2013 15:20:16 +0300 Subject: powerpc/t4240: set pcie liodn in the correct register The liodn for the T4240's PCIE controller is no longer set through a register in the guts register block but with one in the PCIE register block itself. Use the already existing SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor Cc: Scott Wood Cc: York Sun --- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 54c1cfd..f181315 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -86,10 +86,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 555), SET_SATA_LIODN(2, 556), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), SET_DMA_LIODN(1, 147), SET_DMA_LIODN(2, 227), -- cgit v1.1 From 8f9fe660fcf99af47dc0a28b80cd4e34d403f7c5 Mon Sep 17 00:00:00 2001 From: Laurentiu TUDOR Date: Wed, 23 Oct 2013 15:20:27 +0300 Subject: powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor Cc: Scott Wood Cc: York Sun --- arch/powerpc/cpu/mpc85xx/liodn.c | 25 +++++++++++++++++++++---- arch/powerpc/include/asm/immap_85xx.h | 4 +++- 2 files changed, 24 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 4b00da9..19e130e 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -239,9 +239,9 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) #endif #define CONFIG_SYS_MAX_PCI_EPS 8 -#define CONFIG_SYS_PCI_EP_LIODN_START 256 -static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat) +static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat, + int ep_liodn_start) { int off, pci_idx = 0, pci_cnt = 0, i, rc; const uint32_t *base_liodn; @@ -271,7 +271,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat) continue; } for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++) - liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START + + liodn_offs[i + 1] = ep_liodn_start + i * pci_cnt + pci_idx - *base_liodn; rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list", liodn_offs, sizeof(liodn_offs)); @@ -338,5 +338,22 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); #endif - fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4"); + ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR; + int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0; + + if (pci_ver >= 0x0204) { + if (pci_ver >= 0x0300) + liodn_base = 1024; + else + liodn_base = 256; + } + + if (liodn_base) { + char compat[32]; + + sprintf(compat, "fsl,qoriq-pcie-v%d.%d", + (pci_ver & 0xff00) >> 8, pci_ver & 0xff); + fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base); + fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base); + } } diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3e76c54..6312618 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -282,7 +282,9 @@ typedef struct ccsr_pcix { u32 int_ack; /* PCIX IRQ Acknowledge */ u8 res000c[52]; u32 liodn_base; /* PCIX LIODN base register */ - u8 res0044[3004]; + u8 res0044[2996]; + u32 ipver1; /* PCIX IP block revision register 1 */ + u32 ipver2; /* PCIX IP block revision register 2 */ u32 potar0; /* PCIX Outbound Transaction Addr 0 */ u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ -- cgit v1.1 From 51abee64eee0186634858d1e6f91a65969c90125 Mon Sep 17 00:00:00 2001 From: Laurentiu TUDOR Date: Wed, 23 Oct 2013 15:20:45 +0300 Subject: powerpc/85xx: fix broken cpu "clock-frequency" property When indexing freqProcessor[] we use the first value in the cpu's "reg" property, which on new e6500 cores IDs the threads. But freqProcessor[] should be indexed with a core index so, when fixing "the clock-frequency" cpu node property, access the freqProcessor[] with the core index derived from the "reg' property. If we don't do this, last half of the "cpu" nodes will have broken "clock-frequency" values. Signed-off-by: Laurentiu Tudor Cc: York Sun --- arch/powerpc/cpu/mpc85xx/fdt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 2ccd9c7..33bc900 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -586,6 +586,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) { int off; int val; + int len; sys_info_t sysinfo; /* delete crypto node if not on an E-processor */ @@ -615,8 +616,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) get_sys_info(&sysinfo); off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { - u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); - val = cpu_to_fdt32(sysinfo.freq_processor[*reg]); + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); + val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]); fdt_setprop(blob, off, "clock-frequency", &val, 4); off = fdt_node_offset_by_prop_value(blob, off, "device_type", "cpu", 4); -- cgit v1.1