From bc647958047cd03193e19cd8c08a6771fea828b7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 21 Feb 2017 23:00:35 +0900 Subject: ARM: uniphier: set up charge pump current for MPLL of LD11 SoC Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-base-ld20.c | 21 +++++++++++++++++++++ arch/arm/mach-uniphier/clk/pll-ld11.c | 2 ++ arch/arm/mach-uniphier/clk/pll.h | 1 + 3 files changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index c66f083..697eb7a 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -18,6 +18,8 @@ #define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) +#define SC_PLLCTRL3_REGI_SHIFT 16 +#define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16) /* PLL type: VPLL27 */ #define SC_VPLL27CTRL_WP BIT(0) @@ -77,6 +79,25 @@ int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) return 0; } +int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) +{ + void __iomem *base; + u32 tmp; + + base = ioremap(reg_base, SZ_16); + if (!base) + return -ENOMEM; + + tmp = readl(base + 8); /* SSCPLLCTRL */ + tmp &= ~SC_PLLCTRL3_REGI_MASK; + tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; + writel(tmp, base + 8); + + iounmap(base); + + return 0; +} + int uniphier_ld20_vpll27_init(unsigned long reg_base) { void __iomem *base; diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index 7746deb..02befa2 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -18,6 +18,8 @@ void uniphier_ld11_pll_init(void) uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */ uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5); + mdelay(1); uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); diff --git a/arch/arm/mach-uniphier/clk/pll.h b/arch/arm/mach-uniphier/clk/pll.h index d7e9303..5eefc4e 100644 --- a/arch/arm/mach-uniphier/clk/pll.h +++ b/arch/arm/mach-uniphier/clk/pll.h @@ -15,6 +15,7 @@ void uniphier_ld4_dpll_ssc_en(void); int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, unsigned int ssc_rate, unsigned int divn); int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base); +int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi); int uniphier_ld20_vpll27_init(unsigned long reg_base); int uniphier_ld20_dspll_init(unsigned long reg_base); -- cgit v1.1