From 7e611272ddb3b41985ad881f549f4258e1469f65 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 18 May 2015 13:37:25 +0800 Subject: imx: mx6sx enable SION for i2c pin mux Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise we will get erros when doing i2c operations. error log like the following: " wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0xb retry=1 " Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 40 +++++++++++++++--------------- 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h index 7c6c1e8..5dd9a50 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -146,7 +146,7 @@ enum { MX6_PAD_CSI_DATA00__CSI1_DATA_2 = IOMUX_PAD(0x0394, 0x004C, 0, 0x06A8, 0, 0), MX6_PAD_CSI_DATA00__ESAI_TX_CLK = IOMUX_PAD(0x0394, 0x004C, 1, 0x078C, 1, 0), MX6_PAD_CSI_DATA00__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0394, 0x004C, 2, 0x0684, 1, 0), - MX6_PAD_CSI_DATA00__I2C1_SCL = IOMUX_PAD(0x0394, 0x004C, 3, 0x07A8, 0, 0), + MX6_PAD_CSI_DATA00__I2C1_SCL = IOMUX_PAD(0x0394, 0x004C, IOMUX_CONFIG_SION | 3, 0x07A8, 0, 0), MX6_PAD_CSI_DATA00__UART6_RI_B = IOMUX_PAD(0x0394, 0x004C, 4, 0x0000, 0, 0), MX6_PAD_CSI_DATA00__GPIO1_IO_14 = IOMUX_PAD(0x0394, 0x004C, 5, 0x0000, 0, 0), MX6_PAD_CSI_DATA00__WEIM_DATA_23 = IOMUX_PAD(0x0394, 0x004C, 6, 0x0000, 0, 0), @@ -157,7 +157,7 @@ enum { MX6_PAD_CSI_DATA01__CSI1_DATA_3 = IOMUX_PAD(0x0398, 0x0050, 0, 0x06AC, 0, 0), MX6_PAD_CSI_DATA01__ESAI_TX_FS = IOMUX_PAD(0x0398, 0x0050, 1, 0x077C, 1, 0), MX6_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0398, 0x0050, 2, 0x0688, 1, 0), - MX6_PAD_CSI_DATA01__I2C1_SDA = IOMUX_PAD(0x0398, 0x0050, 3, 0x07AC, 0, 0), + MX6_PAD_CSI_DATA01__I2C1_SDA = IOMUX_PAD(0x0398, 0x0050, IOMUX_CONFIG_SION | 3, 0x07AC, 0, 0), MX6_PAD_CSI_DATA01__UART6_DSR_B = IOMUX_PAD(0x0398, 0x0050, 4, 0x0000, 0, 0), MX6_PAD_CSI_DATA01__GPIO1_IO_15 = IOMUX_PAD(0x0398, 0x0050, 5, 0x0000, 0, 0), MX6_PAD_CSI_DATA01__WEIM_DATA_22 = IOMUX_PAD(0x0398, 0x0050, 6, 0x0000, 0, 0), @@ -211,7 +211,7 @@ enum { MX6_PAD_CSI_DATA06__CSI1_DATA_8 = IOMUX_PAD(0x03AC, 0x0064, 0, 0x06C0, 0, 0), MX6_PAD_CSI_DATA06__ESAI_TX2_RX3 = IOMUX_PAD(0x03AC, 0x0064, 1, 0x0798, 1, 0), - MX6_PAD_CSI_DATA06__I2C4_SCL = IOMUX_PAD(0x03AC, 0x0064, 2, 0x07C0, 2, 0), + MX6_PAD_CSI_DATA06__I2C4_SCL = IOMUX_PAD(0x03AC, 0x0064, IOMUX_CONFIG_SION | 2, 0x07C0, 2, 0), MX6_PAD_CSI_DATA06__KPP_COL_7 = IOMUX_PAD(0x03AC, 0x0064, 3, 0x07D0, 0, 0), MX6_PAD_CSI_DATA06__UART6_RTS_B = IOMUX_PAD(0x03AC, 0x0064, 4, 0x0854, 0, 0), MX6_PAD_CSI_DATA06__GPIO1_IO_20 = IOMUX_PAD(0x03AC, 0x0064, 5, 0x0000, 0, 0), @@ -222,7 +222,7 @@ enum { MX6_PAD_CSI_DATA07__CSI1_DATA_9 = IOMUX_PAD(0x03B0, 0x0068, 0, 0x06C4, 0, 0), MX6_PAD_CSI_DATA07__ESAI_TX3_RX2 = IOMUX_PAD(0x03B0, 0x0068, 1, 0x079C, 1, 0), - MX6_PAD_CSI_DATA07__I2C4_SDA = IOMUX_PAD(0x03B0, 0x0068, 2, 0x07C4, 2, 0), + MX6_PAD_CSI_DATA07__I2C4_SDA = IOMUX_PAD(0x03B0, 0x0068, IOMUX_CONFIG_SION | 2, 0x07C4, 2, 0), MX6_PAD_CSI_DATA07__KPP_ROW_7 = IOMUX_PAD(0x03B0, 0x0068, 3, 0x07DC, 0, 0), MX6_PAD_CSI_DATA07__UART6_CTS_B = IOMUX_PAD(0x03B0, 0x0068, 4, 0x0854, 1, 0), MX6_PAD_CSI_DATA07__GPIO1_IO_21 = IOMUX_PAD(0x03B0, 0x0068, 5, 0x0000, 0, 0), @@ -361,7 +361,7 @@ enum { MX6_PAD_ENET2_RX_CLK__ENET2_RX_CLK = IOMUX_PAD(0x03E4, 0x009C, 0, 0x0774, 0, 0), MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M = IOMUX_PAD(0x03E4, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_CLK__I2C3_SCL = IOMUX_PAD(0x03E4, 0x009C, 2, 0x07B8, 1, 0), + MX6_PAD_ENET2_RX_CLK__I2C3_SCL = IOMUX_PAD(0x03E4, 0x009C, IOMUX_CONFIG_SION | 2, 0x07B8, 1, 0), MX6_PAD_ENET2_RX_CLK__UART1_RTS_B = IOMUX_PAD(0x03E4, 0x009C, 3, 0x082C, 2, 0), MX6_PAD_ENET2_RX_CLK__MLB_DATA = IOMUX_PAD(0x03E4, 0x009C, 4, 0x07EC, 1, 0), MX6_PAD_ENET2_RX_CLK__GPIO2_IO_8 = IOMUX_PAD(0x03E4, 0x009C, 5, 0x0000, 0, 0), @@ -372,7 +372,7 @@ enum { MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x03E8, 0x00A0, 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x03E8, 0x00A0, 1, 0x076C, 1, 0), - MX6_PAD_ENET2_TX_CLK__I2C3_SDA = IOMUX_PAD(0x03E8, 0x00A0, 2, 0x07BC, 1, 0), + MX6_PAD_ENET2_TX_CLK__I2C3_SDA = IOMUX_PAD(0x03E8, 0x00A0, IOMUX_CONFIG_SION | 2, 0x07BC, 1, 0), MX6_PAD_ENET2_TX_CLK__UART1_CTS_B = IOMUX_PAD(0x03E8, 0x00A0, 3, 0x082C, 3, 0), MX6_PAD_ENET2_TX_CLK__MLB_CLK = IOMUX_PAD(0x03E8, 0x00A0, 4, 0x07E8, 1, 0), MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 = IOMUX_PAD(0x03E8, 0x00A0, 5, 0x0000, 0, 0), @@ -420,7 +420,7 @@ enum { MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0), + MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0), MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), @@ -467,7 +467,7 @@ enum { MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0), - MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0), + MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0), MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0), @@ -780,7 +780,7 @@ enum { MX6_PAD_LCD1_VSYNC__MMDC_DEBUG_3 = IOMUX_PAD(0x0484, 0x013C, 9, 0x0000, 0, 0), MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0488, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__I2C3_SDA = IOMUX_PAD(0x0488, 0x0140, 1, 0x07BC, 0, 0), + MX6_PAD_NAND_ALE__I2C3_SDA = IOMUX_PAD(0x0488, 0x0140, IOMUX_CONFIG_SION | 1, 0x07BC, 0, 0), MX6_PAD_NAND_ALE__QSPI2_A_SS0_B = IOMUX_PAD(0x0488, 0x0140, 2, 0x0000, 0, 0), MX6_PAD_NAND_ALE__ECSPI2_SS0 = IOMUX_PAD(0x0488, 0x0140, 3, 0x072C, 0, 0), MX6_PAD_NAND_ALE__ESAI_TX3_RX2 = IOMUX_PAD(0x0488, 0x0140, 4, 0x079C, 0, 0), @@ -813,7 +813,7 @@ enum { MX6_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0490, 0x0148, 9, 0x0000, 0, 0), MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0494, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__I2C3_SCL = IOMUX_PAD(0x0494, 0x014C, 1, 0x07B8, 0, 0), + MX6_PAD_NAND_CLE__I2C3_SCL = IOMUX_PAD(0x0494, 0x014C, IOMUX_CONFIG_SION | 1, 0x07B8, 0, 0), MX6_PAD_NAND_CLE__QSPI2_A_SCLK = IOMUX_PAD(0x0494, 0x014C, 2, 0x0000, 0, 0), MX6_PAD_NAND_CLE__ECSPI2_SCLK = IOMUX_PAD(0x0494, 0x014C, 3, 0x0720, 0, 0), MX6_PAD_NAND_CLE__ESAI_TX2_RX3 = IOMUX_PAD(0x0494, 0x014C, 4, 0x0798, 0, 0), @@ -1054,7 +1054,7 @@ enum { MX6_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 = IOMUX_PAD(0x04EC, 0x01A4, 7, 0x0000, 0, 0), MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 = IOMUX_PAD(0x04F0, 0x01A8, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA2__I2C2_SDA = IOMUX_PAD(0x04F0, 0x01A8, 1, 0x07B4, 2, 0), + MX6_PAD_QSPI1B_DATA2__I2C2_SDA = IOMUX_PAD(0x04F0, 0x01A8, IOMUX_CONFIG_SION | 1, 0x07B4, 2, 0), MX6_PAD_QSPI1B_DATA2__ECSPI5_RDY = IOMUX_PAD(0x04F0, 0x01A8, 2, 0x0000, 0, 0), MX6_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 = IOMUX_PAD(0x04F0, 0x01A8, 3, 0x07A4, 2, 0), MX6_PAD_QSPI1B_DATA2__CSI1_DATA_20 = IOMUX_PAD(0x04F0, 0x01A8, 4, 0x06EC, 1, 0), @@ -1063,7 +1063,7 @@ enum { MX6_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 = IOMUX_PAD(0x04F0, 0x01A8, 7, 0x0000, 0, 0), MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 = IOMUX_PAD(0x04F4, 0x01AC, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA3__I2C2_SCL = IOMUX_PAD(0x04F4, 0x01AC, 1, 0x07B0, 2, 0), + MX6_PAD_QSPI1B_DATA3__I2C2_SCL = IOMUX_PAD(0x04F4, 0x01AC, IOMUX_CONFIG_SION | 1, 0x07B0, 2, 0), MX6_PAD_QSPI1B_DATA3__ECSPI5_SS3 = IOMUX_PAD(0x04F4, 0x01AC, 2, 0x0000, 0, 0), MX6_PAD_QSPI1B_DATA3__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01AC, 3, 0x077C, 2, 0), MX6_PAD_QSPI1B_DATA3__CSI1_DATA_19 = IOMUX_PAD(0x04F4, 0x01AC, 4, 0x06E8, 1, 0), @@ -1389,7 +1389,7 @@ enum { MX6_PAD_SD2_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0588, 0x0240, 1, 0x0674, 2, 0), MX6_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x0588, 0x0240, 2, 0x07DC, 1, 0), MX6_PAD_SD2_DATA0__PWM1_OUT = IOMUX_PAD(0x0588, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0588, 0x0240, 4, 0x07C4, 3, 0), + MX6_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0588, 0x0240, IOMUX_CONFIG_SION | 4, 0x07C4, 3, 0), MX6_PAD_SD2_DATA0__GPIO6_IO_8 = IOMUX_PAD(0x0588, 0x0240, 5, 0x0000, 0, 0), MX6_PAD_SD2_DATA0__ECSPI4_SS3 = IOMUX_PAD(0x0588, 0x0240, 6, 0x0000, 0, 0), MX6_PAD_SD2_DATA0__UART4_RX = IOMUX_PAD(0x0588, 0x0240, 7, 0x0848, 4, 0), @@ -1400,7 +1400,7 @@ enum { MX6_PAD_SD2_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x058C, 0x0244, 1, 0x0684, 2, 0), MX6_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x058C, 0x0244, 2, 0x07D0, 1, 0), MX6_PAD_SD2_DATA1__PWM2_OUT = IOMUX_PAD(0x058C, 0x0244, 3, 0x0000, 0, 0), - MX6_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x058C, 0x0244, 4, 0x07C0, 3, 0), + MX6_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x058C, 0x0244, IOMUX_CONFIG_SION | 4, 0x07C0, 3, 0), MX6_PAD_SD2_DATA1__GPIO6_IO_9 = IOMUX_PAD(0x058C, 0x0244, 5, 0x0000, 0, 0), MX6_PAD_SD2_DATA1__ECSPI4_SS2 = IOMUX_PAD(0x058C, 0x0244, 6, 0x0000, 0, 0), MX6_PAD_SD2_DATA1__UART4_TX = IOMUX_PAD(0x058C, 0x0244, 7, 0x0848, 5, 0), @@ -1450,7 +1450,7 @@ enum { MX6_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x059C, 0x0254, 9, 0x0000, 0, 0), MX6_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x05A0, 0x0258, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA0__I2C4_SCL = IOMUX_PAD(0x05A0, 0x0258, 1, 0x07C0, 0, 0), + MX6_PAD_SD3_DATA0__I2C4_SCL = IOMUX_PAD(0x05A0, 0x0258, IOMUX_CONFIG_SION | 1, 0x07C0, 0, 0), MX6_PAD_SD3_DATA0__ECSPI2_SS1 = IOMUX_PAD(0x05A0, 0x0258, 2, 0x0000, 0, 0), MX6_PAD_SD3_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x05A0, 0x0258, 3, 0x0674, 0, 0), MX6_PAD_SD3_DATA0__LCDIF2_DATA_1 = IOMUX_PAD(0x05A0, 0x0258, 4, 0x0000, 0, 0), @@ -1461,7 +1461,7 @@ enum { MX6_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x05A0, 0x0258, 9, 0x0000, 0, 0), MX6_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x05A4, 0x025C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__I2C4_SDA = IOMUX_PAD(0x05A4, 0x025C, 1, 0x07C4, 0, 0), + MX6_PAD_SD3_DATA1__I2C4_SDA = IOMUX_PAD(0x05A4, 0x025C, IOMUX_CONFIG_SION | 1, 0x07C4, 0, 0), MX6_PAD_SD3_DATA1__ECSPI2_SS2 = IOMUX_PAD(0x05A4, 0x025C, 2, 0x0000, 0, 0), MX6_PAD_SD3_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x05A4, 0x025C, 3, 0x0684, 0, 0), MX6_PAD_SD3_DATA1__LCDIF2_DATA_0 = IOMUX_PAD(0x05A4, 0x025C, 4, 0x0000, 0, 0), @@ -1583,7 +1583,7 @@ enum { MX6_PAD_SD4_DATA2__USDHC4_DATA2 = IOMUX_PAD(0x05D0, 0x0288, 0, 0x0000, 0, 0), MX6_PAD_SD4_DATA2__RAWNAND_DATA12 = IOMUX_PAD(0x05D0, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA2__I2C2_SDA = IOMUX_PAD(0x05D0, 0x0288, 2, 0x07B4, 0, 0), + MX6_PAD_SD4_DATA2__I2C2_SDA = IOMUX_PAD(0x05D0, 0x0288, IOMUX_CONFIG_SION | 2, 0x07B4, 0, 0), MX6_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x05D0, 0x0288, 3, 0x0640, 0, 0), MX6_PAD_SD4_DATA2__LCDIF2_DATA_10 = IOMUX_PAD(0x05D0, 0x0288, 4, 0x0000, 0, 0), MX6_PAD_SD4_DATA2__GPIO6_IO_16 = IOMUX_PAD(0x05D0, 0x0288, 5, 0x0000, 0, 0), @@ -1594,7 +1594,7 @@ enum { MX6_PAD_SD4_DATA3__USDHC4_DATA3 = IOMUX_PAD(0x05D4, 0x028C, 0, 0x0000, 0, 0), MX6_PAD_SD4_DATA3__RAWNAND_DATA13 = IOMUX_PAD(0x05D4, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA3__I2C2_SCL = IOMUX_PAD(0x05D4, 0x028C, 2, 0x07B0, 0, 0), + MX6_PAD_SD4_DATA3__I2C2_SCL = IOMUX_PAD(0x05D4, 0x028C, IOMUX_CONFIG_SION | 2, 0x07B0, 0, 0), MX6_PAD_SD4_DATA3__AUDMUX_AUD3_TXD = IOMUX_PAD(0x05D4, 0x028C, 3, 0x0630, 0, 0), MX6_PAD_SD4_DATA3__LCDIF2_DATA_9 = IOMUX_PAD(0x05D4, 0x028C, 4, 0x0000, 0, 0), MX6_PAD_SD4_DATA3__GPIO6_IO_17 = IOMUX_PAD(0x05D4, 0x028C, 5, 0x0000, 0, 0), @@ -1661,14 +1661,14 @@ enum { MX6_PAD_USB_H_DATA__USB_H_DATA = IOMUX_PAD(0x05EC, 0x02A4, 0, 0x0000, 0, 0), MX6_PAD_USB_H_DATA__PWM2_OUT = IOMUX_PAD(0x05EC, 0x02A4, 1, 0x0000, 0, 0), MX6_PAD_USB_H_DATA__ANATOP_24M_OUT = IOMUX_PAD(0x05EC, 0x02A4, 2, 0x0000, 0, 0), - MX6_PAD_USB_H_DATA__I2C4_SDA = IOMUX_PAD(0x05EC, 0x02A4, 3, 0x07C4, 1, 0), + MX6_PAD_USB_H_DATA__I2C4_SDA = IOMUX_PAD(0x05EC, 0x02A4, IOMUX_CONFIG_SION | 3, 0x07C4, 1, 0), MX6_PAD_USB_H_DATA__WDOG3_WDOG_B = IOMUX_PAD(0x05EC, 0x02A4, 4, 0x0000, 0, 0), MX6_PAD_USB_H_DATA__GPIO7_IO_10 = IOMUX_PAD(0x05EC, 0x02A4, 5, 0x0000, 0, 0), MX6_PAD_USB_H_STROBE__USB_H_STROBE = IOMUX_PAD(0x05F0, 0x02A8, 0, 0x0000, 0, 0), MX6_PAD_USB_H_STROBE__PWM1_OUT = IOMUX_PAD(0x05F0, 0x02A8, 1, 0x0000, 0, 0), MX6_PAD_USB_H_STROBE__ANATOP_32K_OUT = IOMUX_PAD(0x05F0, 0x02A8, 2, 0x0000, 0, 0), - MX6_PAD_USB_H_STROBE__I2C4_SCL = IOMUX_PAD(0x05F0, 0x02A8, 3, 0x07C0, 1, 0), + MX6_PAD_USB_H_STROBE__I2C4_SCL = IOMUX_PAD(0x05F0, 0x02A8, IOMUX_CONFIG_SION | 3, 0x07C0, 1, 0), MX6_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x05F0, 0x02A8, 4, 0x0000, 0, 0), MX6_PAD_USB_H_STROBE__GPIO7_IO_11 = IOMUX_PAD(0x05F0, 0x02A8, 5, 0x0000, 0, 0), }; -- cgit v1.1 From 28420e780ab5b1bf4bd76ed04313b86ffc4ea17e Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 18 May 2015 17:13:52 +0530 Subject: arm/imx-common: Fix warning 'get_reset_cause' defined but not used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix below warning arch/arm/imx-common/cpu.c:29:14: warning: ‘get_reset_cause’ defined but not used static char *get_reset_cause(void) Signed-off-by: Prabhakar Kushwaha Reviewed-by: Eric Nelson Acked-by: Stefano Babic --- arch/arm/imx-common/cpu.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 067d08f..0cd08cb 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -24,6 +24,7 @@ #include #endif +#if defined(CONFIG_DISPLAY_CPUINFO) static u32 reset_cause = -1; static char *get_reset_cause(void) @@ -60,6 +61,7 @@ u32 get_imx_reset_cause(void) { return reset_cause; } +#endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6) #if defined(CONFIG_MX53) -- cgit v1.1 From 3625fd64ef929af4d158027aa5beee703f1294fc Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 18 May 2015 07:07:02 -0700 Subject: arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specified Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support to the MMDC however enabling it on the DDR3 got missed. Make sure we enable it on the DDR3 as well. Gateworks uses Micron memory as well as Winbond in MX6. We have found in testing that we need to enable fast-exit for Winbond stability. Gateworks boards are currently the only boards using the MX6 SPL and enabling fast-exit mode. Signed-off-by: Tim Harvey --- arch/arm/cpu/armv7/mx6/ddr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 5d5bd0f..86c8354 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -521,7 +521,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, /* MR0 */ val = ((tcl - 1) << 4) | /* CAS */ (1 << 8) | /* DLL Reset */ - ((twr - 3) << 9); /* Write Recovery */ + ((twr - 3) << 9) | /* Write Recovery */ + (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */ debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs)); mmdc0->mdscr = MR(val, 0, 3, cs); /* ZQ calibration */ -- cgit v1.1 From d43e0ab42d1ad853a51272050e2c0c452db48949 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 18 May 2015 06:56:44 -0700 Subject: mx6: add OTP bank1 registers Signed-off-by: Tim Harvey --- arch/arm/include/asm/arch-mx6/imx-regs.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 9a4ad8b..35bb005 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -640,6 +640,25 @@ struct fuse_bank0_regs { u32 rsvd7[3]; }; +struct fuse_bank1_regs { + u32 mem0; + u32 rsvd0[3]; + u32 mem1; + u32 rsvd1[3]; + u32 mem2; + u32 rsvd2[3]; + u32 mem3; + u32 rsvd3[3]; + u32 mem4; + u32 rsvd4[3]; + u32 ana0; + u32 rsvd5[3]; + u32 ana1; + u32 rsvd6[3]; + u32 ana2; + u32 rsvd7[3]; +}; + #ifdef CONFIG_MX6SX struct fuse_bank4_regs { u32 sjc_resp_low; -- cgit v1.1 From 9b9449c3e2809994d260f4f783b98652e7b6353b Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 18 May 2015 07:02:24 -0700 Subject: imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTP The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description Table. Return this frequency so that it can be used elsewhere. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades. Signed-off-by: Tim Harvey --- arch/arm/cpu/armv7/mx6/soc.c | 41 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + 2 files changed, 42 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 21ef9d0..f91b725 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -83,6 +83,47 @@ u32 get_cpu_rev(void) return (type << 12) | (reg + 0x10); } +/* + * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440) + * defines a 2-bit SPEED_GRADING + */ +#define OCOTP_CFG3_SPEED_SHIFT 16 +#define OCOTP_CFG3_SPEED_800MHZ 0 +#define OCOTP_CFG3_SPEED_850MHZ 1 +#define OCOTP_CFG3_SPEED_1GHZ 2 +#define OCOTP_CFG3_SPEED_1P2GHZ 3 + +u32 get_cpu_speed_grade_hz(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + uint32_t val; + + val = readl(&fuse->cfg3); + val >>= OCOTP_CFG3_SPEED_SHIFT; + val &= 0x3; + + switch (val) { + /* Valid for IMX6DQ */ + case OCOTP_CFG3_SPEED_1P2GHZ: + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + return 1200000000; + /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ + case OCOTP_CFG3_SPEED_1GHZ: + return 996000000; + /* Valid for IMX6DQ */ + case OCOTP_CFG3_SPEED_850MHZ: + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + return 852000000; + /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ + case OCOTP_CFG3_SPEED_800MHZ: + return 792000000; + } + return 0; +} + #ifdef CONFIG_REVISION_TAG u32 __weak get_board_rev(void) { diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 28ba844..a2cd0a9 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -16,6 +16,7 @@ u32 get_nr_cpus(void); u32 get_cpu_rev(void); +u32 get_cpu_speed_grade_hz(void); /* returns MXC_CPU_ value */ #define cpu_type(rev) (((rev) >> 12)&0xff) -- cgit v1.1 From b83ddac80553ae001b4daa412e386e00d45d0bbb Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 18 May 2015 07:02:25 -0700 Subject: imx: mx6: display max cpu frequency in print_cpuinfo() Display the max CPU frequency as well as the current running CPU frequency if the max CPU frequency is available and differs from the current CPU frequency. Before: CPU: Freescale i.MX6Q rev1.2 at 792 MHz After - using an 800MHz IMX6DL (running at its max) CPU: Freescale i.MX6DL rev1.1 at 792 MHz After - using a 1GHz IMX6Q (not running at its max): CPU: Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz) Cc: Stefan Roese Cc: Eric Nelson Cc: Heiko Schocher Cc: Nikita Kiryanov Cc: Jon Nettleton Cc: Jason Liu Cc: Ye Li Cc: Fabio Estevam Cc: Christian Gmeiner Cc: Markus Niebel Cc: Peng Fan Tested-by: Nikolay Dimitrov Signed-off-by: Tim Harvey --- arch/arm/imx-common/cpu.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 0cd08cb..37472ea 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -144,7 +144,7 @@ const char *get_imx_type(u32 imxtype) int print_cpuinfo(void) { - u32 cpurev; + u32 cpurev, max_freq; #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) struct udevice *thermal_dev; @@ -153,11 +153,25 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); +#if defined(CONFIG_MX6) + printf("CPU: Freescale i.MX%s rev%d.%d", + get_imx_type((cpurev & 0xFF000) >> 12), + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0); + max_freq = get_cpu_speed_grade_hz(); + if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) { + printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + } else { + printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + } +#else printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", get_imx_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); +#endif #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); -- cgit v1.1 From f0e8e8944dc9bdddd0e3e3b7dbd8ac76008b32a4 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 18 May 2015 06:56:45 -0700 Subject: imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480 in the Fusemap Description Table in the reference manual. Return this value as well as min/max temperature based on the value. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. This has been tested with IMX6 Automative and Industrial parts. Signed-off-by: Tim Harvey --- arch/arm/cpu/armv7/mx6/soc.c | 38 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + 2 files changed, 39 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index f91b725..b21bd03 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -124,6 +124,44 @@ u32 get_cpu_speed_grade_hz(void) return 0; } +/* + * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480) + * defines a 2-bit Temperature Grade + * + * return temperature grade and min/max temperature in celcius + */ +#define OCOTP_MEM0_TEMP_SHIFT 6 + +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + uint32_t val; + + val = readl(&fuse->mem0); + val >>= OCOTP_MEM0_TEMP_SHIFT; + val &= 0x3; + + if (minc && maxc) { + if (val == TEMP_AUTOMOTIVE) { + *minc = -40; + *maxc = 125; + } else if (val == TEMP_INDUSTRIAL) { + *minc = -40; + *maxc = 105; + } else if (val == TEMP_EXTCOMMERCIAL) { + *minc = -20; + *maxc = 105; + } else { + *minc = 0; + *maxc = 95; + } + } + return val; +} + #ifdef CONFIG_REVISION_TAG u32 __weak get_board_rev(void) { diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index a2cd0a9..c583291 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -17,6 +17,7 @@ u32 get_nr_cpus(void); u32 get_cpu_rev(void); u32 get_cpu_speed_grade_hz(void); +u32 get_cpu_temp_grade(int *minc, int *maxc); /* returns MXC_CPU_ value */ #define cpu_type(rev) (((rev) >> 12)&0xff) -- cgit v1.1 From 70caa8e21d3e2393571981631f9b87c253e2ac29 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 18 May 2015 06:56:46 -0700 Subject: imx: mx6: add display of CPU temperature grade in print_cpuinfo() When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info along with the current temperature. Before: CPU: Temperature 42 C After: CPU: Automotive temperature grade (-40C to 125C) at 42C CPU: Industrial temperature grade (-40C to 105C) at 42C CPU: Extended Commercial temperature grade (-20C to 105C) at 42C Cc: Stefan Roese Cc: Eric Nelson Cc: Heiko Schocher Cc: Nikita Kiryanov Cc: Jon Nettleton Cc: Jason Liu Cc: Ye Li Cc: Fabio Estevam Cc: Christian Gmeiner Cc: Markus Niebel Cc: Peng Fan Tested-by: Nikolay Dimitrov Signed-off-by: Tim Harvey --- arch/arm/imx-common/cpu.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 37472ea..275befd 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -148,7 +149,7 @@ int print_cpuinfo(void) #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) struct udevice *thermal_dev; - int cpu_tmp, ret; + int cpu_tmp, minc, maxc, ret; #endif cpurev = get_cpu_rev(); @@ -174,16 +175,32 @@ int print_cpuinfo(void) #endif #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) + puts("CPU: "); + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_AUTOMOTIVE: + puts("Automotive temperature grade "); + break; + case TEMP_INDUSTRIAL: + puts("Industrial temperature grade "); + break; + case TEMP_EXTCOMMERCIAL: + puts("Extended Commercial temperature grade "); + break; + default: + puts("Commercial temperature grade "); + break; + } + printf("(%dC to %dC)", minc, maxc); ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); if (!ret) { ret = thermal_get_temp(thermal_dev, &cpu_tmp); if (!ret) - printf("CPU: Temperature %d C\n", cpu_tmp); + printf(" at %dC\n", cpu_tmp); else - printf("CPU: Temperature: invalid sensor data\n"); + puts(" - invalid sensor data\n"); } else { - printf("CPU: Temperature: Can't find sensor device\n"); + puts(" - invalid sensor device\n"); } #endif -- cgit v1.1 From 0d1ea05210f3221667f8085cf167f23f336ca0c0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 11 May 2015 20:50:22 -0300 Subject: wandboard: Switch to SPL support Currently we need to build one U-boot image for each of the wandboard variants: quad, dual-lite and solo. By switching to SPL we can support all these variants with a single binary, which is very convenient. Based on the work from Richard Hu. Tested kernel booting on the three boards. Signed-off-by: Richard Hu Signed-off-by: Fabio Estevam Tested-by: Vagrant Cascadian Reviewed-by: Stefano Babic --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6727423..2f2c0eb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -499,6 +499,7 @@ config TARGET_UDOO config TARGET_WANDBOARD bool "Support wandboard" select CPU_V7 + select SUPPORT_SPL config TARGET_WARP bool "Support WaRP" -- cgit v1.1 From ab87fc6bbd80f4e702e7dde102b1c74f0f4678b3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 20 May 2015 10:28:48 +0800 Subject: imx: dma: correct MXS_DMA_ALIGNMENT We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes. If on chips whose cache line size is 64 bytes, error occurs: " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined. Signed-off-by: Peng Fan Acked-by: Marek Vasut --- arch/arm/include/asm/imx-common/dma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h index d5c1f7f..7d421b3 100644 --- a/arch/arm/include/asm/imx-common/dma.h +++ b/arch/arm/include/asm/imx-common/dma.h @@ -22,7 +22,7 @@ #define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS #endif -#define MXS_DMA_ALIGNMENT 32 +#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN /* * MXS DMA channels -- cgit v1.1 From 21a26940f9048e668f9a79f64b802406b2e8d18c Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 18 May 2015 10:56:24 +0200 Subject: arm, imx6, i2c: add I2C4 for MX6DL add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher --- arch/arm/cpu/armv7/mx6/clock.c | 33 +++++++++++++++++++++----------- arch/arm/imx-common/i2c-mxv7.c | 5 ++++- arch/arm/include/asm/arch-mx6/crm_regs.h | 2 ++ arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + 4 files changed, 29 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 055f44e..ae99945 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -140,23 +140,34 @@ int enable_usdhc_clk(unsigned char enable, unsigned bus_num) #endif #ifdef CONFIG_SYS_I2C_MXC -/* i2c_num can be from 0 - 2 */ +/* i2c_num can be from 0 - 3 */ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { u32 reg; u32 mask; - if (i2c_num > 2) + if (i2c_num > 3) return -EINVAL; - - mask = MXC_CCM_CCGR_CG_MASK - << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1)); - reg = __raw_readl(&imx_ccm->CCGR2); - if (enable) - reg |= mask; - else - reg &= ~mask; - __raw_writel(reg, &imx_ccm->CCGR2); + if (i2c_num < 3) { + mask = MXC_CCM_CCGR_CG_MASK + << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + + (i2c_num << 1)); + reg = __raw_readl(&imx_ccm->CCGR2); + if (enable) + reg |= mask; + else + reg &= ~mask; + __raw_writel(reg, &imx_ccm->CCGR2); + } else { + mask = MXC_CCM_CCGR_CG_MASK + << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET); + reg = __raw_readl(&imx_ccm->CCGR1); + if (enable) + reg |= mask; + else + reg &= ~mask; + __raw_writel(reg, &imx_ccm->CCGR1); + } return 0; } #endif diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c index f3a5c3f..ff72b1a 100644 --- a/arch/arm/imx-common/i2c-mxv7.c +++ b/arch/arm/imx-common/i2c-mxv7.c @@ -67,9 +67,12 @@ static void * const i2c_bases[] = { #ifdef I2C3_BASE_ADDR (void *)I2C3_BASE_ADDR, #endif +#ifdef I2C4_BASE_ADDR + (void *)I2C4_BASE_ADDR, +#endif }; -/* i2c_index can be from 0 - 2 */ +/* i2c_index can be from 0 - 3 */ int setup_i2c(unsigned i2c_index, int speed, int slave_addr, struct i2c_pads_info *p) { diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 0592ce0..887d048 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -592,6 +592,8 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) +#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 +#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 35bb005..0d38d45 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -277,6 +277,7 @@ #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) +#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) -- cgit v1.1 From e6c8b716c7035fd2b80d0b938e736176053b9ef6 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 18 May 2015 10:58:12 +0200 Subject: i2c, mxc: rework i2c base address names for different SoCs rework and unify i2c address names for different SoCs, which use the mxc_i2c driver. Signed-off-by: Heiko Schocher --- arch/arm/include/asm/arch-imx/imx-regs.h | 2 +- arch/arm/include/asm/arch-mx25/imx-regs.h | 6 +++--- arch/arm/include/asm/arch-mx27/imx-regs.h | 4 ++-- arch/arm/include/asm/arch-vf610/imx-regs.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h index 4de0779..93e3369 100644 --- a/arch/arm/include/asm/arch-imx/imx-regs.h +++ b/arch/arm/include/asm/arch-imx/imx-regs.h @@ -42,7 +42,7 @@ #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) -#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) +#define I2C1_BASE_ADDR (0x17000 + IMX_IO_BASE) #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 3dffa4a..78c4e9b 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -293,13 +293,13 @@ struct cspi_regs { #define IMX_ETB_SLOT4_BASE (0x43F0C000) #define IMX_ETB_SLOT5_BASE (0x43F10000) #define IMX_ECT_CTIO_BASE (0x43F18000) -#define IMX_I2C_BASE (0x43F80000) -#define IMX_I2C3_BASE (0x43F84000) +#define I2C1_BASE_ADDR (0x43F80000) +#define I2C3_BASE_ADDR (0x43F84000) #define IMX_CAN1_BASE (0x43F88000) #define IMX_CAN2_BASE (0x43F8C000) #define UART1_BASE (0x43F90000) #define UART2_BASE (0x43F94000) -#define IMX_I2C2_BASE (0x43F98000) +#define I2C2_BASE_ADDR (0x43F98000) #define IMX_OWIRE_BASE (0x43F9C000) #define IMX_CSPI1_BASE (0x43FA4000) #define IMX_KPP_BASE (0x43FA8000) diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 7402e31..baf1d29 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -184,13 +184,13 @@ struct fuse_bank0_regs { #define UART2_BASE (0x0b000 + IMX_IO_BASE) #define UART3_BASE (0x0c000 + IMX_IO_BASE) #define UART4_BASE (0x0d000 + IMX_IO_BASE) -#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) +#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) #define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) #define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) #define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) -#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE) +#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE) #define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) #define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) #define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index a7d765a..2021981 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -74,7 +74,7 @@ #define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) #define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) #define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000) -#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) +#define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) #define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000) #define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000) #define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) -- cgit v1.1 From 7254d92ebcedf9dc8dfe76a8d310faf46f46274f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 18 May 2015 13:32:31 +0200 Subject: arm, imx6: add support for aristainetos2 board add support for imx6dl based aristainetos2 board U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27) CPU: Freescale i.MX6DL rev1.1 at 792 MHz Reset cause: WDOG Board: aristaitenos2 Watchdog enabled I2C: ready DRAM: 1 GiB NAND: 1024 MiB MMC: FSL_SDHC: 0 SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB Display: lg4573 (480x800) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => Signed-off-by: Heiko Schocher --- arch/arm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2f2c0eb..b62842f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -525,6 +525,10 @@ config TARGET_ARISTAINETOS bool "Support aristainetos" select CPU_V7 +config TARGET_ARISTAINETOS2 + bool "Support aristainetos2" + select CPU_V7 + config TARGET_MX6QARM2 bool "Support mx6qarm2" select CPU_V7 -- cgit v1.1