From 36d0a42b682e4d8493e8c080425bc9fb6f188cd2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Aug 2012 16:53:35 +0200 Subject: dm: mips: Fix lb60 WDT control Write the TSCR register via 32bit write instead of 16bit one. The register is 32bit wide and bit 16 is being set, triggering gcc overflow error and making the code broken. Signed-off-by: Marek Vasut Cc: Daniel Cc: Shinya Kuribayashi Cc: Xiangfu Liu --- arch/mips/cpu/xburst/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c index e976341..ddcbfaa 100644 --- a/arch/mips/cpu/xburst/cpu.c +++ b/arch/mips/cpu/xburst/cpu.c @@ -62,7 +62,7 @@ void __attribute__((weak)) _machine_restart(void) writew(100, &wdt->tdr); /* wdt_set_data(100) */ writew(0, &wdt->tcnt); /* wdt_set_count(0); */ - writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */ + writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */ writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */ while (1) -- cgit v1.1 From 8b82cefbfc88d12cdffa0970f03047b74d08487e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Aug 2012 16:53:35 +0200 Subject: dm: mips: Fix lb60 timer code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The timer code contains more halfword writes which trigger gcc errors. The registers are again 32bit, yet written by 16bit writes, fix this: timer.c: In function ‘reset_timer_masked’: timer.c:37:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘get_timer_masked’: timer.c:43:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘timer_init’: timer.c:86:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:88:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:89:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:90:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut Cc: Daniel Cc: Shinya Kuribayashi Cc: Xiangfu Liu --- arch/mips/cpu/xburst/timer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/xburst/timer.c b/arch/mips/cpu/xburst/timer.c index de6f5da..b6b3855 100644 --- a/arch/mips/cpu/xburst/timer.c +++ b/arch/mips/cpu/xburst/timer.c @@ -34,13 +34,13 @@ static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE; void reset_timer_masked(void) { /* reset time */ - gd->lastinc = readw(&tcu->tcnt0); + gd->lastinc = readl(&tcu->tcnt0); gd->tbl = 0; } ulong get_timer_masked(void) { - ulong now = readw(&tcu->tcnt0); + ulong now = readl(&tcu->tcnt0); if (gd->lastinc <= now) gd->tbl += now - gd->lastinc; /* normal mode */ @@ -83,11 +83,11 @@ void udelay_masked(unsigned long usec) int timer_init(void) { - writew(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0); + writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0); - writew(0, &tcu->tcnt0); - writew(0, &tcu->tdhr0); - writew(TIMER_FDATA, &tcu->tdfr0); + writel(0, &tcu->tcnt0); + writel(0, &tcu->tdhr0); + writel(TIMER_FDATA, &tcu->tdfr0); /* mask irqs */ writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr); -- cgit v1.1 From d2aa5dca74fcf8cbe7fa1f27606a5663bb52d3e6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Aug 2012 16:53:35 +0200 Subject: dm: mips: Import libgcc components from Linux Import ashldr3, ashrdi3 and lshrdi3 to squash possible libgcc fp mismatch, resulting in the following warning: mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_lshrdi3.o) uses hard float, u-boot uses soft float mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_ashldi3.o) uses hard float, u-boot uses soft float Imported from Linux (linux-next 20120723) as of commit: commit 72fbfb260197a52c2bc2583f3e8f15d261d0f924 Author: Ralf Baechle Date: Wed Jun 7 13:25:37 2006 +0100 [MIPS] Fix optimization for size build. It took a while longer than on other architectures but gcc has finally started to strike us as well ... This also fixes the damage by 6edfba1b33c701108717f4e036320fc39abe1912. Signed-off-by: Ralf Baechle Signed-off-by: Marek Vasut Cc: Daniel Schwierzeck [: removed USE_PRIVATE_LIBGCC = yes] Signed-off-by: Daniel Schwierzeck --- arch/mips/lib/Makefile | 20 ++++++++++++++++++++ arch/mips/lib/ashldi3.c | 25 +++++++++++++++++++++++++ arch/mips/lib/ashrdi3.c | 27 +++++++++++++++++++++++++++ arch/mips/lib/libgcc.h | 25 +++++++++++++++++++++++++ arch/mips/lib/lshrdi3.c | 25 +++++++++++++++++++++++++ 5 files changed, 122 insertions(+) create mode 100644 arch/mips/lib/ashldi3.c create mode 100644 arch/mips/lib/ashrdi3.c create mode 100644 arch/mips/lib/libgcc.h create mode 100644 arch/mips/lib/lshrdi3.c (limited to 'arch') diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 9244f31..967e98a 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -25,6 +25,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o +## Build a couple of necessary functions into a private libgcc +LIBGCC = $(obj)libgcc.o +GLSOBJS += ashldi3.o +GLSOBJS += ashrdi3.o +GLSOBJS += lshrdi3.o +LGOBJS := $(addprefix $(obj),$(GLSOBJS)) + SOBJS-y += COBJS-y += board.o @@ -37,9 +44,22 @@ endif SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +# Always build libmips.o +TARGETS := $(LIB) + +# Build private libgcc only when asked for +ifdef USE_PRIVATE_LIBGCC +TARGETS += $(LIBGCC) +endif + +all: $(TARGETS) + $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(LIBGCC): $(obj).depend $(LGOBJS) + $(call cmd_link_o_target, $(LGOBJS)) + ######################################################################### # defines $(obj).depend target diff --git a/arch/mips/lib/ashldi3.c b/arch/mips/lib/ashldi3.c new file mode 100644 index 0000000..9b50d86 --- /dev/null +++ b/arch/mips/lib/ashldi3.c @@ -0,0 +1,25 @@ +#include "libgcc.h" + +long long __ashldi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.low = 0; + w.s.high = (unsigned int) uu.s.low << -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.low >> bm; + + w.s.low = (unsigned int) uu.s.low << b; + w.s.high = ((unsigned int) uu.s.high << b) | carries; + } + + return w.ll; +} diff --git a/arch/mips/lib/ashrdi3.c b/arch/mips/lib/ashrdi3.c new file mode 100644 index 0000000..f30359b --- /dev/null +++ b/arch/mips/lib/ashrdi3.c @@ -0,0 +1,27 @@ +#include "libgcc.h" + +long long __ashrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + /* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >> 31; + w.s.low = uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} diff --git a/arch/mips/lib/libgcc.h b/arch/mips/lib/libgcc.h new file mode 100644 index 0000000..05909d5 --- /dev/null +++ b/arch/mips/lib/libgcc.h @@ -0,0 +1,25 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include + +typedef int word_type __attribute__ ((mode (__word__))); + +#ifdef __BIG_ENDIAN +struct DWstruct { + int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { + int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { + struct DWstruct s; + long long ll; +} DWunion; + +#endif /* __ASM_LIBGCC_H */ diff --git a/arch/mips/lib/lshrdi3.c b/arch/mips/lib/lshrdi3.c new file mode 100644 index 0000000..bb340ac --- /dev/null +++ b/arch/mips/lib/lshrdi3.c @@ -0,0 +1,25 @@ +#include "libgcc.h" + +long long __lshrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.high = 0; + w.s.low = (unsigned int) uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = (unsigned int) uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} -- cgit v1.1 From 2c0e3de384f6a3323a1ffbf5db390b3081c3e102 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Tue, 21 Aug 2012 23:27:37 +0200 Subject: MIPS: factor out endianess flag handling to arch config.mk This is CPU independent and should be configured architecture-wide. Signed-off-by: Daniel Schwierzeck --- arch/mips/config.mk | 20 ++++++++++++++++++-- arch/mips/cpu/mips32/config.mk | 19 +------------------ arch/mips/cpu/xburst/config.mk | 3 +-- 3 files changed, 20 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 6ab8acd..b680256 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,6 +23,22 @@ CROSS_COMPILE ?= mips_4KC- +# Handle special prefix in ELDK 4.0 toolchain +ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) +ENDIANNESS := -EL +endif + +ifdef CONFIG_SYS_LITTLE_ENDIAN +ENDIANNESS := -EL +endif + +ifdef CONFIG_SYS_BIG_ENDIAN +ENDIANNESS := -EB +endif + +# Default to EB if no endianess is configured +ENDIANNESS ?= -EB + CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ @@ -47,8 +63,8 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # On the other hand, we want PIC in the U-Boot code to relocate it from ROM # to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic +PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS) PLATFORM_CPPFLAGS += -msoft-float -PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib +PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS) PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index a1cd590..a0e4de5 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -29,21 +29,4 @@ # MIPSFLAGS := -march=mips32r2 -# Handle special prefix in ELDK 4.0 toolchain -ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) -ENDIANNESS := -EL -endif - -ifdef CONFIG_SYS_LITTLE_ENDIAN -ENDIANNESS := -EL -endif - -ifdef CONFIG_SYS_BIG_ENDIAN -ENDIANNESS := -EB -endif - -# Default to EB if no endianess is configured -ENDIANNESS ?= -EB - -PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANNESS) -PLATFORM_LDFLAGS += $(ENDIANNESS) +PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk index bce0c1b..18d49ab 100644 --- a/arch/mips/cpu/xburst/config.mk +++ b/arch/mips/cpu/xburst/config.mk @@ -20,5 +20,4 @@ # MA 02111-1307 USA # -PLATFORM_CPPFLAGS += -march=mips32 -EL -PLATFORM_LDFLAGS += -EL +PLATFORM_CPPFLAGS += -march=mips32 -- cgit v1.1 From 0efcdb15f991386fea9e8de614b058bce759d557 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Tue, 21 Aug 2012 23:38:25 +0200 Subject: MIPS: move CONFIG_STANDALONE_LOAD_ADDR to CPU config makefiles Prepare for upcoming MIPS64 CPU support. Signed-off-by: Daniel Schwierzeck --- arch/mips/config.mk | 2 -- arch/mips/cpu/mips32/config.mk | 2 ++ arch/mips/cpu/xburst/config.mk | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/config.mk b/arch/mips/config.mk index b680256..de9140b 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -39,8 +39,6 @@ endif # Default to EB if no endianess is configured ENDIANNESS ?= -EB -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds - PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index a0e4de5..481e984 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -30,3 +30,5 @@ MIPSFLAGS := -march=mips32r2 PLATFORM_CPPFLAGS += $(MIPSFLAGS) + +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk index 18d49ab..1536746 100644 --- a/arch/mips/cpu/xburst/config.mk +++ b/arch/mips/cpu/xburst/config.mk @@ -21,3 +21,5 @@ # PLATFORM_CPPFLAGS += -march=mips32 + +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds -- cgit v1.1