From 262f08d6ea18a62f827b8ccb60f355ca2eaf6e2b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 22 Aug 2013 14:52:02 +0200 Subject: zynq: Use arch_cpu_init() instead of lowlevel_init() Zynq lowlevel_init() was implemented in C but stack pointer is setup after function call in _main(). Move architecture setup to arch_cpu_init() which is call as the first function in board_init_f() which already have correct stack pointer. Reported-by: Sven Schwermer Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 4914986..2bb3843 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -11,6 +11,10 @@ void lowlevel_init(void) { +} + +int arch_cpu_init(void) +{ zynq_slcr_unlock(); /* remap DDR to zero, FILTERSTART */ writel(0, &scu_base->filter_start); @@ -31,6 +35,8 @@ void lowlevel_init(void) writel(0xC, &slcr_base->ddr_urgent); zynq_slcr_lock(); + + return 0; } void reset_cpu(ulong addr) -- cgit v1.1 From 762a88ccf8540948fbf8c31b40a29d1e0684a25b Mon Sep 17 00:00:00 2001 From: Pierre Aubert Date: Thu, 19 Sep 2013 17:48:59 +0200 Subject: mx6: compute PLL PFD frequencies rather than using defines Signed-off-by: Pierre Aubert CC: Stefano Babic --- arch/arm/cpu/armv7/mx6/clock.c | 56 ++++++++++++++++++++++++-------- arch/arm/include/asm/arch-mx6/crm_regs.h | 11 ------- 2 files changed, 42 insertions(+), 25 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index df11678..3bf80e2 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -100,6 +100,32 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) } /* NOTREACHED */ } +static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) +{ + u32 div; + u64 freq; + + switch (pll) { + case PLL_BUS: + if (pfd_num == 3) { + /* No PFD3 on PPL2 */ + return 0; + } + div = __raw_readl(&imx_ccm->analog_pfd_528); + freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); + break; + case PLL_USBOTG: + div = __raw_readl(&imx_ccm->analog_pfd_480); + freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); + break; + default: + /* No PFD on other PLL */ + return 0; + } + + return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> + ANATOP_PFD_FRAC_SHIFT(pfd_num)); +} static u32 get_mcu_main_clk(void) { @@ -144,13 +170,14 @@ u32 get_periph_clk(void) freq = decode_pll(PLL_BUS, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; break; default: break; @@ -184,7 +211,7 @@ static u32 get_ipg_per_clk(void) static u32 get_uart_clk(void) { u32 reg, uart_podf; - u32 freq = PLL3_80M; + u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); #ifdef CONFIG_MX6SL if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) @@ -204,7 +231,7 @@ static u32 get_cspi_clk(void) reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; - return PLL3_60M / (cspi_podf + 1); + return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); } static u32 get_axi_clk(void) @@ -217,9 +244,9 @@ static u32 get_axi_clk(void) if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); else - root_freq = PLL3_PFD1_FREQ; + root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); } else root_freq = get_periph_clk(); @@ -244,10 +271,10 @@ static u32 get_emi_slow_clk(void) root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); break; case 2: - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 3: - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 0); break; } @@ -270,13 +297,14 @@ static u32 get_mmdc_ch0_clk(void) freq = decode_pll(PLL_BUS, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; } return freq / (podf + 1); @@ -359,9 +387,9 @@ static u32 get_usdhc_clk(u32 port) } if (clk_sel) - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 0); else - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); return root_freq / (usdhc_podf + 1); } diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 2813593..7202073 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -890,15 +890,4 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) -#define PLL2_PFD0_FREQ 352000000 -#define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 396000000 -#define PLL2_PFD2_DIV_FREQ 200000000 -#define PLL3_PFD0_FREQ 720000000 -#define PLL3_PFD1_FREQ 540000000 -#define PLL3_PFD2_FREQ 508200000 -#define PLL3_PFD3_FREQ 454700000 -#define PLL3_80M 80000000 -#define PLL3_60M 60000000 - #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ -- cgit v1.1 From 6654f33c9b520bd4073c7f82a13044e79bc14898 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 24 Sep 2013 17:39:17 +0200 Subject: ARM: mxs: tools: Use mkimage for BootStream generation Now that mkimage can generate an BootStream for i.MX23 and i.MX28, use the mkimage as a default tool to generate the BootStreams instead of the elftosb tool. This cuts out another obscure dependency. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic --- arch/arm/cpu/arm926ejs/mxs/Makefile | 11 ++++++----- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 4 ++-- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg | 4 ++-- 3 files changed, 10 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 3d66892..ea397c7 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -25,14 +25,15 @@ $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) # Specify the target for use in elftosb call -ELFTOSB_TARGET-$(CONFIG_MX23) = imx23 -ELFTOSB_TARGET-$(CONFIG_MX28) = imx28 +MKIMAGE_TARGET-$(CONFIG_MX23) = mx23 +MKIMAGE_TARGET-$(CONFIG_MX28) = mx28 -$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd +$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@ -$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd - elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb +$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg + $(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@ + ######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index 8118767..c9cf4b3 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,6 +1,6 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin + LOAD 0x0 OBJTREE/spl/u-boot-spl.bin CALL 0x14 0x0 - LOAD 0x40000100 u-boot.bin + LOAD 0x40000100 OBJTREE/u-boot.bin CALL 0x40000100 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index ea772f0..676f5c8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,8 +1,8 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin + LOAD 0x0 OBJTREE/spl/u-boot-spl.bin LOAD IVT 0x8000 0x14 CALL HAB 0x8000 0x0 - LOAD 0x40000100 u-boot.bin + LOAD 0x40000100 OBJTREE/u-boot.bin LOAD IVT 0x8000 0x40000100 CALL HAB 0x8000 0x0 -- cgit v1.1 From 77b0e2239a13fa83a745ea9b03994bf780a9738a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 20 Sep 2013 01:36:44 +0200 Subject: ARM: mxs: Setup stack in JTAG mode In case the MX23/MX28 is switched into JTAG mode via the BootMode select switches, the BootROM bypasses the CPU core registers initialization. This in turn means that the Stack Pointer (SP) register is not set as it is in every other mode of operation, but instead is only zeroed out. To prevent U-Boot SPL from crashing in this obscure JTAG mode, configure the SP to point at the CONFIG_SYS_INIT_SP_ADDR if the SP is zeroed out. Note that in case the SP is already configured, we must preserve that exact SP value and must not modify it. This is important since in every other mode but the JTAG mode, the SPL returns into the BootROM and BootROM in turn loads U-Boot itself. If the SP were to be corrupted, the BootROM won't be able to continue it's operation after returned from SPL and the system would crash. Finally, add the JTAG mode switch identifier, so it's not recognised as Unknown mode. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Fabio Estevam Cc: Otavio Salvador --- arch/arm/cpu/arm926ejs/mxs/start.S | 9 +++++++++ arch/arm/include/asm/arch-mxs/sys_proto.h | 2 ++ 2 files changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 3e454ae..5de2bad 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -150,6 +150,15 @@ IRQ_STACK_START_IN: _reset: /* + * If the CPU is configured in "Wait JTAG connection mode", the stack + * pointer is not configured and is zero. This will cause crash when + * trying to push data onto stack right below here. Load the SP and make + * it point to the end of OCRAM if the SP is zero. + */ + cmp sp, #0x00000000 + ldreq sp, =CONFIG_SYS_INIT_SP_ADDR + + /* * Store all registers on old stack pointer, this will allow us later to * return to the BootROM and let the BootROM load U-Boot into RAM. * diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 43c7dd6..09dfc90 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -46,6 +46,7 @@ static const struct mxs_pair mxs_boot_modes[] = { { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, { 0x04, 0x1f, "NAND" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0" }, { 0x0a, 0x1f, "SSP SD/MMC #1" }, @@ -60,6 +61,7 @@ static const struct mxs_pair mxs_boot_modes[] = { { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, { 0x04, 0x1f, "NAND, 3V3" }, { 0x14, 0x1f, "NAND, 1V8" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, -- cgit v1.1 From 4867b634b7c0e5ede258b4998fa4b2710e7daacf Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 30 Sep 2013 13:16:52 -0300 Subject: ARM: mx5: Enable L2 cache Enable L2 cache for improving the system performance. Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 25fadf6..97077fd 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,12 @@ #endif mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #2 + mcr 15, 0, r0, c1, c0, 1 + .endm /* init_l2cc */ /* AIPS setup - Only setup MPROTx registers. -- cgit v1.1 From 357efe69e9d70bd510d7a1720bf2d0084ec5e91e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 30 Sep 2013 18:28:54 -0300 Subject: mx5: lowlevel_init: Remove unused macro setup_wdog macro is not used anywhere, so just remove it. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 97077fd..f5bc672 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -375,12 +375,6 @@ setup_pll_func: #endif /* CONFIG_MX53 */ .endm -.macro setup_wdog - ldr r0, =WDOG1_BASE_ADDR - mov r1, #0x30 - strh r1, [r0] -.endm - ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ -- cgit v1.1 From 0029bc47ad7bb2e61121335052fed88b0be1824d Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 21 Oct 2013 21:34:57 -0200 Subject: mx6: Remove PAD_CTL_DSE_120ohm from i.MX6DL's IPU1_DI0_PIN4 pin This removes the PAD_CTL_DSE_120ohm as done for i.MX6Q's IPU1_DI0_PIN4 pin definition and makes it aligned with 3.0.35-4.1.0 and 3.12 mainline kernel. Signed-off-by: Otavio Salvador --- arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index b5df68a..7373407 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -210,7 +210,7 @@ enum { MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__LCDIF_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__LCDIF_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), -- cgit v1.1 From a0f97610757d6370fc58849032b36a94b4167fdc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Oct 2013 12:29:30 +0100 Subject: ARM: mxs: Enable DCDC converter for battery boot In case the board detected sufficient voltage for battery boot, make sure the DCDC converter is ON and the board is not running only from linregs, otherwise an instability will be observed. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 8ea45be..d25019a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -654,6 +654,8 @@ static void mxs_batt_boot(void) clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + + mxs_power_enable_4p2(); } /** -- cgit v1.1 From 155d424a9a0228e2f38ce21a92b20c31896d61d2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 28 Aug 2013 09:00:28 -0400 Subject: am33xx, davinci: Create and use Create a common header file for the RTC IP block that is shared between davinci and am33xx. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 7 ++-- arch/arm/include/asm/arch-am33xx/cpu.h | 9 ----- arch/arm/include/asm/arch-davinci/hardware.h | 38 -------------------- arch/arm/include/asm/davinci_rtc.h | 52 ++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 50 deletions(-) create mode 100644 arch/arm/include/asm/davinci_rtc.h (limited to 'arch') diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index a31bf40..453effa 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -32,6 +32,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -150,15 +151,15 @@ __weak void am33xx_spl_board_init(void) static void rtc32k_enable(void) { - struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; + struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; /* * Unlock the RTC's registers. For more details please see the * RTC_SS section of the TRM. In order to unlock we need to * write these specific values (keys) in this order. */ - writel(0x83e70b13, &rtc->kick0r); - writel(0x95a4f1e0, &rtc->kick1r); + writel(RTC_KICK0R_WE, &rtc->kick0r); + writel(RTC_KICK1R_WE, &rtc->kick1r); /* Enable the RTC 32K OSC by setting bits 3 and 6. */ writel((1 << 3) | (1 << 6), &rtc->osc); diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 52fa128..05752ce 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -457,15 +457,6 @@ struct gptimer { unsigned int tcar2; /* offset 0x58 */ }; -/* RTC Registers */ -struct rtc_regs { - unsigned int res[21]; - unsigned int osc; /* offset 0x54 */ - unsigned int res2[5]; - unsigned int kick0r; /* offset 0x6c */ - unsigned int kick1r; /* offset 0x70 */ -}; - /* UART Registers */ struct uart_sys { unsigned int resv1[21]; diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 05ecc78..7aaf4bf 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -613,42 +613,4 @@ static inline enum davinci_clk_ids get_async3_src(void) #endif -struct davinci_rtc { - dv_reg second; - dv_reg minutes; - dv_reg hours; - dv_reg day; - dv_reg month; /* 0x10 */ - dv_reg year; - dv_reg dotw; - dv_reg resv1; - dv_reg alarmsecond; /* 0x20 */ - dv_reg alarmminute; - dv_reg alarmhour; - dv_reg alarmday; - dv_reg alarmmonth; /* 0x30 */ - dv_reg alarmyear; - dv_reg resv2[2]; - dv_reg ctrl; /* 0x40 */ - dv_reg status; - dv_reg irq; - dv_reg complsb; - dv_reg compmsb; /* 0x50 */ - dv_reg osc; - dv_reg resv3[2]; - dv_reg scratch0; /* 0x60 */ - dv_reg scratch1; - dv_reg scratch2; - dv_reg kick0r; - dv_reg kick1r; /* 0x70 */ -}; - -#define RTC_STATE_BUSY 0x01 -#define RTC_STATE_RUN 0x02 - -#define RTC_KICK0R_WE 0x83e70b13 -#define RTC_KICK1R_WE 0x95a4f1e0 - -#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) - #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/davinci_rtc.h b/arch/arm/include/asm/davinci_rtc.h new file mode 100644 index 0000000..575b590 --- /dev/null +++ b/arch/arm/include/asm/davinci_rtc.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ------------------------------------------------------------------------- + * + * linux/include/asm-arm/arch-davinci/hardware.h + * + * Copyright (C) 2006 Texas Instruments. + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_DAVINCI_RTC_H +#define __ASM_DAVINCI_RTC_H + +struct davinci_rtc { + unsigned int second; + unsigned int minutes; + unsigned int hours; + unsigned int day; + unsigned int month; /* 0x10 */ + unsigned int year; + unsigned int dotw; + unsigned int resv1; + unsigned int alarmsecond; /* 0x20 */ + unsigned int alarmminute; + unsigned int alarmhour; + unsigned int alarmday; + unsigned int alarmmonth; /* 0x30 */ + unsigned int alarmyear; + unsigned int resv2[2]; + unsigned int ctrl; /* 0x40 */ + unsigned int status; + unsigned int irq; + unsigned int complsb; + unsigned int compmsb; /* 0x50 */ + unsigned int osc; + unsigned int resv3[2]; + unsigned int scratch0; /* 0x60 */ + unsigned int scratch1; + unsigned int scratch2; + unsigned int kick0r; + unsigned int kick1r; /* 0x70 */ +}; + +#define RTC_STATE_BUSY 0x01 +#define RTC_STATE_RUN 0x02 + +#define RTC_KICK0R_WE 0x83e70b13 +#define RTC_KICK1R_WE 0x95a4f1e0 +#endif -- cgit v1.1 From 6843918e0035bf06cb65ad2b4c98b38e86e43bd5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 1 Oct 2013 12:32:04 -0400 Subject: am335x: Enable CONFIG_OMAP_WATCHDOG support There is a board-specific portion for calling watchdog enable itself, in main U-Boot. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap-common/boot-common.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 0ffa03a..69fff32 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -14,6 +14,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -76,6 +77,9 @@ void spl_board_init(void) #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif #ifdef CONFIG_AM33XX am33xx_spl_board_init(); #endif -- cgit v1.1 From a13cbf5f208b59797d08199604f2701b6c3b9f64 Mon Sep 17 00:00:00 2001 From: Minal Shah Date: Fri, 4 Oct 2013 14:52:02 -0400 Subject: dra7xx_evm: Enabled UART-boot mode and add dra7xx_evm_uart3 build UART booting is supported on this SoC, but via UART3 rather than UART1. Because of this we must change the board to use UART3 for all console access (only one UART is exposed on this board and a slight HW mod is required to switch UARTs). Signed-off-by: Minal Shah [trini: Make apply to mainline, reword commit] Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap5/spl.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index 57f0de5..2d5a62e 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -16,6 +16,7 @@ #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 #define BOOT_DEVICE_SPI 10 +#define BOOT_DEVICE_UART 0x43 #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 -- cgit v1.1 From 42d4f37b790307987bd2f7cc569238b6b515149d Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Thu, 17 Oct 2013 16:35:38 +0530 Subject: ARM: OMAP5: DDR3: Change io settings The change from 0x64656465 to 0x64646464 is to remove the weak pull enabled on DQS, nDQS lines. This pulls the differential signals in the same direction which is not intended. So disabling the weak pulls improves signal integrity. On the uEVM there are 4 DDR3 devices. The VREF for 2 of the devices is powered by the OMAP's VREF_CA_OUT pins. The VREF on the other 2 devices is powered by the OMAP's VREF_DQ_OUT pins. So the net effect here is that only half of the DDR3 devices were being supplied a VREF! This was clearly a mistake. The second change improves the robustness of the interface and was specifically seen to cure corruption observed at high temperatures on some boards. With the above two changes better memory stability was observed with extended temperature ranges around 100C. Signed-off-by: Sricharan R --- arch/arm/include/asm/arch-omap5/omap.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 414d37a..3c2306f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -145,9 +145,9 @@ struct s32ktimer { #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 #define EFUSE_1 0x45145100 -- cgit v1.1 From d9bef0ad2daa2f6f0b635be12518da755ddcbdc1 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 21 Oct 2013 16:13:59 +0800 Subject: arm: atmel: at91sam9n12ek: add usb host support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add usb host support for at91sam9n12ek board. Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- arch/arm/include/asm/arch-at91/at91_pmc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h index 003920c..7b36f74 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -233,6 +233,8 @@ typedef struct at91_pmc { #endif #define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */ #define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */ +#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */ +#define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */ #define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */ #define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */ -- cgit v1.1 From c12f941bece9ed79efccfe9e4a9fd977da6975f9 Mon Sep 17 00:00:00 2001 From: Roger Meier Date: Mon, 4 Nov 2013 07:40:44 +0100 Subject: at91: add defines for reset type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Roger Meier Acked-by: Bo Shen Reviewed-by: Heiko Schocher Cc: Andreas Bießmann Signed-off-by: Andreas Bießmann --- arch/arm/include/asm/arch-at91/at91_rstc.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h index 423cf51..a942342 100644 --- a/arch/arm/include/asm/arch-at91/at91_rstc.h +++ b/arch/arm/include/asm/arch-at91/at91_rstc.h @@ -38,4 +38,11 @@ typedef struct at91_rstc { #define AT91_RSTC_SR_NRSTL 0x00010000 +#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ +#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) +#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) +#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) +#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) +#define AT91_RSTC_RSTTYP_USER (4 << 8) + #endif -- cgit v1.1