From 7ba0261810dd8924f0aeeb4cf2f12253106170b3 Mon Sep 17 00:00:00 2001
From: Yao Yuan <yao.yuan@freescale.com>
Date: Sat, 5 Dec 2015 14:59:10 +0800
Subject: arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---
 arch/arm/cpu/armv7/ls102xa/Makefile             |  1 +
 arch/arm/cpu/armv7/ls102xa/soc.c                | 66 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++
 3 files changed, 79 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h

(limited to 'arch')

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2311468..0228300 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -8,6 +8,7 @@ obj-y	+= cpu.o
 obj-y	+= clock.o
 obj-y	+= timer.o
 obj-y	+= fsl_epu.o
+obj-y	+= soc.o
 
 obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
new file mode 100644
index 0000000..0fdd6d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ls102xa_soc.h>
+
+unsigned int get_soc_major_rev(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	unsigned int svr, major;
+
+	svr = in_be32(&gur->svr);
+	major = SVR_MAJ(svr);
+
+	return major;
+}
+
+int arch_soc_init(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	unsigned int major;
+
+#ifdef CONFIG_FSL_QSPI
+	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
+#ifdef CONFIG_FSL_DCU_FB
+	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+	/* Configure Little endian for SAI, ASRC and SPDIF */
+	out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
+
+	/*
+	 * Enable snoop requests and DVM message requests for
+	 * Slave insterface S4 (A7 core cluster)
+	 */
+	out_le32(&cci->slave[4].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+	major = get_soc_major_rev();
+	if (major == SOC_MAJOR_VER_1_0) {
+		/*
+		 * Set CCI-400 Slave interface S1, S2 Shareable Override
+		 * Register All transactions are treated as non-shareable
+		 */
+		out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+		out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+		/* Workaround for the issue that DDR could not respond to
+		 * barrier transaction which is generated by executing DSB/ISB
+		 * instruction. Set CCI-400 control override register to
+		 * terminate the barrier transaction. After DDR is initialized,
+		 * allow barrier transaction to DDR again */
+		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+	}
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
new file mode 100644
index 0000000..f10cb91
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_SOC_H
+#define __FSL_LS102XA_SOC_H
+
+unsigned int get_soc_major_rev(void);
+int arch_soc_init(void);
+#endif /* __FSL_LS102XA_SOC_H */
-- 
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