From 7b804c3041690acc1d1242ec3f109c82a77ed9da Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Wed, 11 Jun 2014 14:34:22 +0800 Subject: ENGR00315894-54 iMX6SX/SL: Modify SOC to support two ENET iMX6SX has different enet system clocks with iMX6SL, and has two ENET controllers. So update clocks and soc APIs accordingly to support this features. 1. Modify the clock API "enable_enet_clock" to enable enet system clock for enet controllers. 2. Enet RGMII TX clock source may come from external or internal PLL. By default, use the external phy CLK_25M output as TX clock source. When using internal PLL as source, the function enable_fec_anatop_clock must be called to enable clock for each enet controller. 3. Modify the MAC address function "imx_get_mac_from_fuse" to get either ENET MAC address. 4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz reference clock. 5. Modify imx6slevk BSP to fit the new APIs. Signed-off-by: Fugang Duan Signed-off-by: Ye.Li --- arch/arm/cpu/armv7/mx6/clock.c | 43 +++++++++++++++++++++++++++++--- arch/arm/cpu/armv7/mx6/soc.c | 25 ++++++++++++++++++- arch/arm/include/asm/arch-mx6/clock.h | 5 +++- arch/arm/include/asm/arch-mx6/imx-regs.h | 17 +++++++++++++ arch/arm/include/asm/arch-mx6/iomux.h | 11 ++++++++ 5 files changed, 96 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index e3ca4f6..effe457 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -362,10 +362,34 @@ void enable_qspi_clk(int qspi_num) } } + +void enable_enet_clock(void) +{ + u32 reg = 0; + + /* set enet ahb clock 200Mhz + * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB + */ + reg = __raw_readl(&imx_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK + | MXC_CCM_CHSCCDR_ENET_PODF_MASK | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK); + /* PLL2 PFD2 */ + reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET); + /* Div = 2*/ + reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET); + reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET); + writel(reg, &imx_ccm->chsccdr); + + /* Enable enet system clock */ + reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_ENET_MASK; + writel(reg, &imx_ccm->CCGR3); +} + #endif #ifdef CONFIG_FEC_MXC -int enable_fec_anatop_clock(enum enet_freq freq) +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) { u32 reg = 0; s32 timeout = 100000; @@ -378,7 +402,14 @@ int enable_fec_anatop_clock(enum enet_freq freq) reg = readl(&anatop->pll_enet); reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; - reg |= freq; + + if (0 == fec_id) { + reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); + } else { + reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); + } if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { @@ -393,8 +424,14 @@ int enable_fec_anatop_clock(enum enet_freq freq) } /* Enable FEC clock */ - reg |= BM_ANADIG_PLL_ENET_ENABLE; + if (0 == fec_id) + reg |= BM_ANADIG_PLL_ENET_ENABLE; + else + reg |= BM_ANADIG_PLL_ENET2_ENABLE; reg &= ~BM_ANADIG_PLL_ENET_BYPASS; +#ifdef CONFIG_FEC_MXC_25M_REF_CLK + reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; +#endif writel(reg, &anatop->pll_enet); return 0; diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 88cb2bb..b31ad04 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -480,6 +480,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs; +#ifdef CONFIG_MX6SX + if (0 == dev_id) { + u32 value = readl(&fuse->mac_addr1); + mac[0] = (value >> 8); + mac[1] = value ; + + value = readl(&fuse->mac_addr0); + mac[2] = value >> 24 ; + mac[3] = value >> 16 ; + mac[4] = value >> 8 ; + mac[5] = value ; + } else { + u32 value = readl(&fuse->mac_addr2); + mac[0] = value >> 24 ; + mac[1] = value >> 16 ; + mac[2] = value >> 8 ; + mac[3] = value ; + + value = readl(&fuse->mac_addr1); + mac[4] = value >> 24 ; + mac[5] = value >> 16 ; + } +#else u32 value = readl(&fuse->mac_addr_high); mac[0] = (value >> 8); mac[1] = value ; @@ -489,7 +512,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) mac[3] = value >> 16 ; mac[4] = value >> 8 ; mac[5] = value ; - +#endif } #endif diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 3bfbc9c..cf21fb9 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -58,12 +58,15 @@ int enable_sata_clock(void); int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); -int enable_fec_anatop_clock(enum enet_freq freq); +#ifdef CONFIG_FEC_MXC +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); +#endif #ifdef CONFIG_SECURE_BOOT void hab_caam_clock_enable(void); void hab_caam_clock_disable(void); #endif #if (defined(CONFIG_MX6SX)) void enable_qspi_clk(int qspi_num); +void enable_enet_clock(void); #endif #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 39df1fd..30b750e 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -591,6 +591,22 @@ struct fuse_bank1_regs { u32 ana2; }; +#ifdef CONFIG_MX6SX +struct fuse_bank4_regs { + u32 sjc_resp_low; + u32 rsvd0[3]; + u32 sjc_resp_high; + u32 rsvd1[3]; + u32 mac_addr0; + u32 rsvd2[3]; + u32 mac_addr1; + u32 rsvd3[3]; + u32 mac_addr2; + u32 rsvd4[7]; + u32 gp1; + u32 rsvd5[7]; +}; +#else struct fuse_bank4_regs { u32 sjc_resp_low; u32 rsvd0[3]; @@ -605,6 +621,7 @@ struct fuse_bank4_regs { u32 gp2; u32 rsvd5[3]; }; +#endif struct aipstz_regs { u32 mprot0; diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index f9ee0d9..c3003c1 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -65,6 +65,16 @@ #define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \ | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK) +#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17) +#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13) +#define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \ + | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK) + +#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18) +#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14) +#define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \ + | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK) + #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) @@ -157,4 +167,5 @@ |IOMUXC_GPR13_SATA_PHY_3_MASK \ |IOMUXC_GPR13_SATA_PHY_2_MASK \ |IOMUXC_GPR13_SATA_PHY_1_MASK) + #endif /* __ASM_ARCH_IOMUX_H__ */ -- cgit v1.1