From ff7e9700eda14ccf8ebe399d3831ef266e743c2d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 02:44:36 +0200 Subject: arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/include/asm/system.h | 1 + arch/arm/lib/cache-cp15.c | 2 ++ 2 files changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index d51ba66..ca2d44f 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -185,6 +185,7 @@ enum dcache_option { DCACHE_OFF = 0x12, DCACHE_WRITETHROUGH = 0x1a, DCACHE_WRITEBACK = 0x1e, + DCACHE_WRITEALLOC = 0x16, }; /* Size of an MMU section */ diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 3e62d58..2155fe8 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank) i++) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) set_section_dcache(i, DCACHE_WRITETHROUGH); +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) + set_section_dcache(i, DCACHE_WRITEALLOC); #else set_section_dcache(i, DCACHE_WRITEBACK); #endif -- cgit v1.1 From e1f006f4384769d284530d71988d4c6dd17db4f4 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Tue, 9 Sep 2014 14:05:39 +0200 Subject: arm: socfpga: Complete the list of base addresses Add base addresses for all subsystems as documented in the Cyclone V HPS documentation. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Chin Liang See --- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 2d3152d..cb062ac 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,16 +7,56 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 #define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 #define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 #define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #define SOCFPGA_EMAC0_ADDRESS 0xff700000 #define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ -- cgit v1.1 From be324354eebcd809bf539d2414c7c0a370847f26 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:44:39 +0200 Subject: arm: socfpga: Clean up base address file Sort the list of functional block addresses and fix indentation. No functional change. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek Acked-by: Chin Liang See --- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 102 ++++++++++----------- 1 file changed, 51 insertions(+), 51 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index cb062ac..6534283 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,56 +7,56 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ -#define SOCFPGA_SDMMC_ADDRESS 0xff704000 -#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 -#define SOCFPGA_L3REGS_ADDRESS 0xff800000 -#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc03000 -#define SOCFPGA_SDR_ADDRESS 0xffc20000 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 -#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 -#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 -#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 -#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 -#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 -#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 -#define SOCFPGA_EMAC0_ADDRESS 0xff700000 -#define SOCFPGA_EMAC1_ADDRESS 0xff702000 -#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 -#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 -#define SOCFPGA_STM_ADDRESS 0xfc000000 -#define SOCFPGA_DAP_ADDRESS 0xff000000 -#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 -#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 -#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 -#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 -#define SOCFPGA_QSPI_ADDRESS 0xff705000 -#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 -#define SOCFPGA_GPIO0_ADDRESS 0xff708000 -#define SOCFPGA_GPIO1_ADDRESS 0xff709000 -#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 -#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 -#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 -#define SOCFPGA_USB0_ADDRESS 0xffb00000 -#define SOCFPGA_USB1_ADDRESS 0xffb40000 -#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 -#define SOCFPGA_CAN0_ADDRESS 0xffc00000 -#define SOCFPGA_CAN1_ADDRESS 0xffc01000 -#define SOCFPGA_I2C0_ADDRESS 0xffc04000 -#define SOCFPGA_I2C1_ADDRESS 0xffc05000 -#define SOCFPGA_I2C2_ADDRESS 0xffc06000 -#define SOCFPGA_I2C3_ADDRESS 0xffc07000 -#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 -#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 -#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 -#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 -#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 -#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 -#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 -#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 -#define SOCFPGA_ROM_ADDRESS 0xfffd0000 -#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_EMAC0_ADDRESS 0xff700000 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ -- cgit v1.1 From de6da9255ac4017e6bf6c98f533829a6eb67f3f6 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Tue, 9 Sep 2014 14:03:28 +0200 Subject: arm: socfpga: Add watchdog disable for socfpga This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default) --- arch/arm/cpu/armv7/socfpga/misc.c | 14 ++++++++++++++ arch/arm/cpu/armv7/socfpga/reset_manager.c | 12 ++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 4 ++++ 3 files changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index ecae393..b633615 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -36,6 +37,19 @@ int overwrite_console(void) } #endif +int arch_cpu_init(void) +{ + /* + * If the HW watchdog is NOT enabled, make sure it is not running, + * for example because it was enabled in the preloader. This might + * trigger a watchdog-triggered reboot of Linux kernel later. + */ +#ifndef CONFIG_HW_WATCHDOG + socfpga_watchdog_reset(); +#endif + return 0; +} + int misc_init_r(void) { return 0; diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index e320c01..5d7aba4 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; +/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */ +void socfpga_watchdog_reset(void) +{ + /* assert reset for watchdog */ + setbits_le32(&reset_manager_base->per_mod_reset, + 1 << RSTMGR_PERMODRST_L4WD0_LSB); + + /* deassert watchdog from reset (watchdog in not running state) */ + clrbits_le32(&reset_manager_base->per_mod_reset, + 1 << RSTMGR_PERMODRST_L4WD0_LSB); +} + /* * Write the reset manager register to cause reset */ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 3e95476..18506e6 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,8 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +void socfpga_watchdog_reset(void); + struct socfpga_reset_manager { u32 status; u32 ctrl; @@ -27,4 +29,6 @@ struct socfpga_reset_manager { #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 #endif +#define RSTMGR_PERMODRST_L4WD0_LSB 6 + #endif /* _RESET_MANAGER_H_ */ -- cgit v1.1 From 665e4caf02e4e835c5ec50d616512c6c7d99f1c0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: sysmgr: Clean up system manager Clean up the system manager register definition and add the missing register definitions in place. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/system_manager.c | 18 ++-- arch/arm/include/asm/arch-socfpga/system_manager.h | 102 +++++++++++++++------ 2 files changed, 86 insertions(+), 34 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c index d96521b..07c72e4 100644 --- a/arch/arm/cpu/armv7/socfpga/system_manager.c +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013 Altera Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,21 +7,23 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + /* * Configure all the pin muxes */ void sysmgr_pinmux_init(void) { - unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET; - - const unsigned long *pval = sys_mgr_init_table; - unsigned long i; + uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0]; + int i; - for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); - i++, offset += sizeof(unsigned long)) { - writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset)); + for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) { + writel(sys_mgr_init_table[i], regs); + regs += sizeof(regs); } } diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index 838d210..90d2720 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013 Altera Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,72 +16,122 @@ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; #endif - -#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400) - -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) - struct socfpga_system_manager { - u32 siliconid1; + /* System Manager Module */ + u32 siliconid1; /* 0x00 */ u32 siliconid2; u32 _pad_0x8_0xf[2]; - u32 wddbg; + u32 wddbg; /* 0x10 */ u32 bootinfo; u32 hpsinfo; u32 parityinj; - u32 fpgaintfgrp_gbl; + /* FPGA Interface Group */ + u32 fpgaintfgrp_gbl; /* 0x20 */ u32 fpgaintfgrp_indiv; u32 fpgaintfgrp_module; u32 _pad_0x2c_0x2f; - u32 scanmgrgrp_ctrl; + /* Scan Manager Group */ + u32 scanmgrgrp_ctrl; /* 0x30 */ u32 _pad_0x34_0x3f[3]; - u32 frzctrl_vioctrl; + /* Freeze Control Group */ + u32 frzctrl_vioctrl; /* 0x40 */ u32 _pad_0x44_0x4f[3]; - u32 frzctrl_hioctrl; + u32 frzctrl_hioctrl; /* 0x50 */ u32 frzctrl_src; u32 frzctrl_hwctrl; u32 _pad_0x5c_0x5f; - u32 emacgrp_ctrl; + /* EMAC Group */ + u32 emacgrp_ctrl; /* 0x60 */ u32 emacgrp_l3master; u32 _pad_0x68_0x6f[2]; - u32 dmagrp_ctrl; + /* DMA Controller Group */ + u32 dmagrp_ctrl; /* 0x70 */ u32 dmagrp_persecurity; u32 _pad_0x78_0x7f[2]; - u32 iswgrp_handoff[8]; - u32 _pad_0xa0_0xbf[8]; - u32 romcodegrp_ctrl; + /* Preloader (initial software) Group */ + u32 iswgrp_handoff[8]; /* 0x80 */ + u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ + /* Boot ROM Code Register Group */ + u32 romcodegrp_ctrl; /* 0xc0 */ u32 romcodegrp_cpu1startaddr; u32 romcodegrp_initswstate; u32 romcodegrp_initswlastld; - u32 romcodegrp_bootromswstate; + u32 romcodegrp_bootromswstate; /* 0xd0 */ u32 __pad_0xd4_0xdf[3]; - u32 romcodegrp_warmramgrp_enable; + /* Warm Boot from On-Chip RAM Group */ + u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ u32 romcodegrp_warmramgrp_datastart; u32 romcodegrp_warmramgrp_length; u32 romcodegrp_warmramgrp_execution; - u32 romcodegrp_warmramgrp_crc; + u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ u32 __pad_0xf4_0xff[3]; - u32 romhwgrp_ctrl; + /* Boot ROM Hardware Register Group */ + u32 romhwgrp_ctrl; /* 0x100 */ u32 _pad_0x104_0x107; + /* SDMMC Controller Group */ u32 sdmmcgrp_ctrl; u32 sdmmcgrp_l3master; - u32 nandgrp_bootstrap; + /* NAND Flash Controller Register Group */ + u32 nandgrp_bootstrap; /* 0x110 */ u32 nandgrp_l3master; + /* USB Controller Group */ u32 usbgrp_l3master; u32 _pad_0x11c_0x13f[9]; - u32 eccgrp_l2; + /* ECC Management Register Group */ + u32 eccgrp_l2; /* 0x140 */ u32 eccgrp_ocram; u32 eccgrp_usb0; u32 eccgrp_usb1; - u32 eccgrp_emac0; + u32 eccgrp_emac0; /* 0x150 */ u32 eccgrp_emac1; u32 eccgrp_dma; u32 eccgrp_can0; - u32 eccgrp_can1; + u32 eccgrp_can1; /* 0x160 */ u32 eccgrp_nand; u32 eccgrp_qspi; u32 eccgrp_sdmmc; + u32 _pad_0x170_0x3ff[164]; + /* Pin Mux Control Group */ + u32 emacio[20]; /* 0x400 */ + u32 flashio[12]; /* 0x450 */ + u32 generalio[28]; /* 0x480 */ + u32 _pad_0x4f0_0x4ff[4]; + u32 mixed1io[22]; /* 0x500 */ + u32 mixed2io[8]; /* 0x558 */ + u32 gplinmux[23]; /* 0x578 */ + u32 gplmux[71]; /* 0x5d4 */ + u32 nandusefpga; /* 0x6f0 */ + u32 _pad_0x6f4; + u32 rgmii1usefpga; /* 0x6f8 */ + u32 _pad_0x6fc_0x700[2]; + u32 i2c0usefpga; /* 0x704 */ + u32 sdmmcusefpga; /* 0x708 */ + u32 _pad_0x70c_0x710[2]; + u32 rgmii0usefpga; /* 0x714 */ + u32 _pad_0x718_0x720[3]; + u32 i2c3usefpga; /* 0x724 */ + u32 i2c2usefpga; /* 0x728 */ + u32 i2c1usefpga; /* 0x72c */ + u32 spim1usefpga; /* 0x730 */ + u32 _pad_0x734; + u32 spim0usefpga; /* 0x738 */ }; +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) +#define SYSMGR_ECC_OCRAM_EN (1 << 0) +#define SYSMGR_ECC_OCRAM_SERR (1 << 3) +#define SYSMGR_ECC_OCRAM_DERR (1 << 4) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 +#define SYSMGR_FPGAINTF_SPIM0 (1 << 0) +#define SYSMGR_FPGAINTF_SPIM1 (1 << 1) +#define SYSMGR_FPGAINTF_EMAC0 (1 << 2) +#define SYSMGR_FPGAINTF_EMAC1 (1 << 3) +#define SYSMGR_FPGAINTF_NAND (1 << 4) +#define SYSMGR_FPGAINTF_SDMMC (1 << 5) + +/* FIXME: This is questionable macro. */ +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) + #endif /* _SYSTEM_MANAGER_H_ */ -- cgit v1.1 From 09f7e314e4d5eef939f97fa85424c9a31fc38119 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Sep 2014 07:21:16 +0200 Subject: arm: socfpga: clock: Implant order into bit definitions The bit definitions for clock manager are complete chaos. Implement some basic logical order into them. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/include/asm/arch-socfpga/clock_manager.h | 166 +++++++++++++--------- 1 file changed, 99 insertions(+), 67 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index babac0e..dea171e 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -103,96 +103,128 @@ struct socfpga_clock_manager { u32 _pad_0xe0_0x200[72]; }; -#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 +#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 +#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) + +#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) +#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) +#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) +#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 + +/* Main PLL */ +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d + +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 -#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 -#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 -#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 + +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) + +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) + +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) + #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) -#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) -#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 + +/* Per PLL */ #define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) #define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) -#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \ - (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d + #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \ - (((x) << 0) & 0x000001ff) + +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) -#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007) -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) + +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 + #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0) #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 -#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 -#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007) + #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) -#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) -#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) + +#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 -#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 -#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) + +/* SDR PLL */ +#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) + #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) + #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) + #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) + #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) #define MAIN_VCO_BASE \ (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \ -- cgit v1.1 From 4425e6285679a22522638bd4bb5281611635a30e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: clock: Drop nonsense inlining from clock manager code The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Scrub this hint. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/clock_manager.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index 158501a..d032bbd 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -30,7 +30,7 @@ static const struct socfpga_clock_manager *clock_manager_base = CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) -static inline void cm_wait_for_lock(uint32_t mask) +static void cm_wait_for_lock(uint32_t mask) { register uint32_t inter_val; do { @@ -39,7 +39,7 @@ static inline void cm_wait_for_lock(uint32_t mask) } /* function to poll in the fsm busy bit */ -static inline void cm_wait_for_fsm(void) +static void cm_wait_for_fsm(void) { while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) ; @@ -49,22 +49,22 @@ static inline void cm_wait_for_fsm(void) * function to write the bypass register which requires a poll of the * busy bit */ -static inline void cm_write_bypass(uint32_t val) +static void cm_write_bypass(uint32_t val) { writel(val, &clock_manager_base->bypass); cm_wait_for_fsm(); } /* function to write the ctrl register which requires a poll of the busy bit */ -static inline void cm_write_ctrl(uint32_t val) +static void cm_write_ctrl(uint32_t val) { writel(val, &clock_manager_base->ctrl); cm_wait_for_fsm(); } /* function to write a clock register that has phase information */ -static inline void cm_write_with_phase(uint32_t value, - uint32_t reg_address, uint32_t mask) +static void cm_write_with_phase(uint32_t value, + uint32_t reg_address, uint32_t mask) { /* poll until phase is zero */ while (readl(reg_address) & mask) -- cgit v1.1 From a832ddba55f79801b6f75b79e96c3f5e1469335a Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: clock: Add code to read clock configuration Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out) --- arch/arm/cpu/armv7/socfpga/clock_manager.c | 226 +++++++++++++++++++++- arch/arm/include/asm/arch-socfpga/clock_manager.h | 43 +++- 2 files changed, 266 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index d032bbd..7a6b3b1 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -8,8 +8,10 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static const struct socfpga_clock_manager *clock_manager_base = - (void *)SOCFPGA_CLKMGR_ADDRESS; + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; #define CLKMGR_BYPASS_ENABLE 1 #define CLKMGR_BYPASS_DISABLE 0 @@ -358,3 +360,225 @@ void cm_basic_init(const cm_config_t *cfg) writel(~0, &clock_manager_base->per_pll.en); writel(~0, &clock_manager_base->sdr_pll.en); } + +unsigned long cm_get_mpu_clk_hz(void) +{ + uint32_t reg, clock; + + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the MPU clock */ + reg = readl(&clock_manager_base->altera.mpuclk); + clock /= (reg + 1); + reg = readl(&clock_manager_base->main_pll.mpuclk); + clock /= (reg + 1); + return clock; +} + +unsigned long cm_get_sdram_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify SDRAM PLL clock source */ + reg = readl(&clock_manager_base->sdr_pll.vco); + reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ; + + /* get the SDRAM VCO clock */ + reg = readl(&clock_manager_base->sdr_pll.vco); + clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the SDRAM (DDR_DQS) clock */ + reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); + reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg); + clock /= (reg + 1); + + return clock; +} + +unsigned int cm_get_l4_sp_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify the source of L4 SP clock */ + reg = readl(&clock_manager_base->main_pll.l4src); + reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg); + + if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the clock prior L4 SP divider (main clk) */ + reg = readl(&clock_manager_base->altera.mainclk); + clock /= (reg + 1); + reg = readl(&clock_manager_base->main_pll.mainclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + } + + /* get the L4 SP clock which supplied to UART */ + reg = readl(&clock_manager_base->main_pll.maindiv); + reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg); + clock = clock / (1 << reg); + + return clock; +} + +unsigned int cm_get_mmc_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify the source of MMC clock */ + reg = readl(&clock_manager_base->per_pll.src); + reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg); + + if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the SDMMC clock */ + reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the SDMMC clock */ + reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); + clock /= (reg + 1); + } + + /* further divide by 4 as we have fixed divider at wrapper */ + clock /= 4; + return clock; +} + +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify the source of QSPI clock */ + reg = readl(&clock_manager_base->per_pll.src); + reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg); + + if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) { + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the qspi clock */ + reg = readl(&clock_manager_base->main_pll.mainqspiclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the qspi clock */ + reg = readl(&clock_manager_base->per_pll.perqspiclk); + clock /= (reg + 1); + } + + return clock; +} + +static void cm_print_clock_quick_summary(void) +{ + printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); + printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000); + printf("EOSC1 %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000); + printf("EOSC2 %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000); + printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000); + printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000); + printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); + printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); + printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); +} + +int set_cpu_clk_info(void) +{ + /* Calculate the clock frequencies required for drivers */ + cm_get_l4_sp_clk_hz(); + cm_get_mmc_controller_clk_hz(); + + gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; + gd->bd->bi_dsp_freq = 0; + gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; + + return 0; +} + +int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cm_print_clock_quick_summary(); + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks, + "display clocks", + "" +); diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index dea171e..d2a9b48 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -7,6 +7,15 @@ #ifndef _CLOCK_MANAGER_H_ #define _CLOCK_MANAGER_H_ +#ifndef __ASSEMBLER__ +/* Clock speed accessors */ +unsigned long cm_get_mpu_clk_hz(void); +unsigned long cm_get_sdram_clk_hz(void); +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +#endif + typedef struct { /* main group */ uint32_t main_vco_base; @@ -89,6 +98,11 @@ struct socfpga_clock_manager_sdr_pll { u32 stat; }; +struct socfpga_clock_manager_altera { + u32 mpuclk; + u32 mainclk; +}; + struct socfpga_clock_manager { u32 ctrl; u32 bypass; @@ -100,7 +114,8 @@ struct socfpga_clock_manager { struct socfpga_clock_manager_main_pll main_pll; struct socfpga_clock_manager_per_pll per_pll; struct socfpga_clock_manager_sdr_pll sdr_pll; - u32 _pad_0xe0_0x200[72]; + struct socfpga_clock_manager_altera altera; + u32 _pad_0xe8_0x200[70]; }; #define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 @@ -118,8 +133,10 @@ struct socfpga_clock_manager { /* Main PLL */ #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) #define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) #define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) #define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) @@ -148,7 +165,8 @@ struct socfpga_clock_manager { #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7) +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) @@ -156,16 +174,25 @@ struct socfpga_clock_manager { #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1) #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 +#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 +#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 /* Per PLL */ +#define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) #define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) #define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 #define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) +#define CLKMGR_VCO_SSRC_EOSC1 0x0 +#define CLKMGR_VCO_SSRC_EOSC2 0x1 +#define CLKMGR_VCO_SSRC_F2S 0x2 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) @@ -191,12 +218,22 @@ struct socfpga_clock_manager { #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) #define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4) #define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0) #define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 +#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 +#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 +#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 +#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 +#define CLKMGR_QSPI_CLK_SRC_PER 0x2 /* SDR PLL */ +#define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) #define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) #define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) @@ -204,8 +241,10 @@ struct socfpga_clock_manager { #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) #define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0) #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 -- cgit v1.1 From 5d8ad0cd3a472f9eaa3b8c63b6ad5d889fce6183 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Sep 2014 08:27:16 +0200 Subject: arm: socfpga: clock: Trim down code duplication Pull out functions to read frequency of Main clock VCO and PLL clock VCO as the code is duplicated multiple times. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/clock_manager.c | 96 ++++++++++++------------------ 1 file changed, 38 insertions(+), 58 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index 7a6b3b1..ed2b419 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -361,7 +361,7 @@ void cm_basic_init(const cm_config_t *cfg) writel(~0, &clock_manager_base->sdr_pll.en); } -unsigned long cm_get_mpu_clk_hz(void) +static unsigned int cm_get_main_vco_clk_hz(void) { uint32_t reg, clock; @@ -371,6 +371,37 @@ unsigned long cm_get_mpu_clk_hz(void) (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + return clock; +} + +static unsigned int cm_get_per_vco_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + + return clock; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + uint32_t reg, clock; + + clock = cm_get_main_vco_clk_hz(); + /* get the MPU clock */ reg = readl(&clock_manager_base->altera.mpuclk); clock /= (reg + 1); @@ -415,11 +446,7 @@ unsigned int cm_get_l4_sp_clk_hz(void) reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg); if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { - /* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); - clock = CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_main_vco_clk_hz(); /* get the clock prior L4 SP divider (main clk) */ reg = readl(&clock_manager_base->altera.mainclk); @@ -427,20 +454,7 @@ unsigned int cm_get_l4_sp_clk_hz(void) reg = readl(&clock_manager_base->main_pll.mainclk); clock /= (reg + 1); } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { - /* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); - reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); - if (reg == CLKMGR_VCO_SSRC_EOSC1) - clock = CONFIG_HPS_CLK_OSC1_HZ; - else if (reg == CLKMGR_VCO_SSRC_EOSC2) - clock = CONFIG_HPS_CLK_OSC2_HZ; - else if (reg == CLKMGR_VCO_SSRC_F2S) - clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; - - /* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_per_vco_clk_hz(); /* get the clock prior L4 SP divider (periph_base_clk) */ reg = readl(&clock_manager_base->per_pll.perbaseclk); @@ -466,30 +480,13 @@ unsigned int cm_get_mmc_controller_clk_hz(void) if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { - /* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); - clock = CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_main_vco_clk_hz(); /* get the SDMMC clock */ reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); clock /= (reg + 1); } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { - /* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); - reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); - if (reg == CLKMGR_VCO_SSRC_EOSC1) - clock = CONFIG_HPS_CLK_OSC1_HZ; - else if (reg == CLKMGR_VCO_SSRC_EOSC2) - clock = CONFIG_HPS_CLK_OSC2_HZ; - else if (reg == CLKMGR_VCO_SSRC_F2S) - clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; - - /* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_per_vco_clk_hz(); /* get the SDMMC clock */ reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); @@ -512,30 +509,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void) if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) { - /* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); - clock = CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_main_vco_clk_hz(); /* get the qspi clock */ reg = readl(&clock_manager_base->main_pll.mainqspiclk); clock /= (reg + 1); } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { - /* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); - reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); - if (reg == CLKMGR_VCO_SSRC_EOSC1) - clock = CONFIG_HPS_CLK_OSC1_HZ; - else if (reg == CLKMGR_VCO_SSRC_EOSC2) - clock = CONFIG_HPS_CLK_OSC2_HZ; - else if (reg == CLKMGR_VCO_SSRC_F2S) - clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; - - /* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_per_vco_clk_hz(); /* get the qspi clock */ reg = readl(&clock_manager_base->per_pll.perqspiclk); -- cgit v1.1 From 44428ab6abbba58aa90b982d4d41b39cbcbec966 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 17:21:00 +0200 Subject: arm: socfpga: clock: Clean up bit definitions Clean up the clock code definitions so they are aligned with mainline standards. There are no functional changes in this patch. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/clock_manager.c | 122 +++----- arch/arm/cpu/armv7/socfpga/spl.c | 174 +++++++----- arch/arm/include/asm/arch-socfpga/clock_manager.h | 330 ++++++++++++---------- 3 files changed, 323 insertions(+), 303 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index ed2b419..1cf0d77 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -13,25 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; -#define CLKMGR_BYPASS_ENABLE 1 -#define CLKMGR_BYPASS_DISABLE 0 -#define CLKMGR_STAT_IDLE 0 -#define CLKMGR_STAT_BUSY 1 -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0 -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1 -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0 -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1 - -#define CLEAR_BGP_EN_PWRDN \ - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) - -#define VCO_EN_BASE \ - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) - static void cm_wait_for_lock(uint32_t mask) { register uint32_t inter_val; @@ -130,14 +111,8 @@ void cm_basic_init(const cm_config_t *cfg) writel(0, &clock_manager_base->per_pll.en); /* Put all plls in bypass */ - cm_write_bypass( - CLKMGR_BYPASS_PERPLLSRC_SET( - CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_SDRPLLSRC_SET( - CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) | - CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) | - CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE)); + cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | + CLKMGR_BYPASS_MAINPLL); /* * Put all plls VCO registers back to reset value. @@ -172,19 +147,14 @@ void cm_basic_init(const cm_config_t *cfg) * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. */ - writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN | - CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->main_pll.vco); - - writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN | - CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->per_pll.vco); - - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | - cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN | - CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->sdr_pll.vco); + writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->main_pll.vco); + + writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->per_pll.vco); + + writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->sdr_pll.vco); /* * Time starts here @@ -234,18 +204,16 @@ void cm_basic_init(const cm_config_t *cfg) /* Enable vco */ /* main pll vco */ - writel(cfg->main_vco_base | VCO_EN_BASE, + writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, &clock_manager_base->main_pll.vco); /* periferal pll */ - writel(cfg->peri_vco_base | VCO_EN_BASE, + writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, &clock_manager_base->per_pll.vco); /* sdram pll vco */ - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | - cfg->sdram_vco_base | VCO_EN_BASE, - &clock_manager_base->sdr_pll.vco); + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->sdr_pll.vco); /* L3 MP and L3 SP */ writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); @@ -296,8 +264,8 @@ void cm_basic_init(const cm_config_t *cfg) &clock_manager_base->per_pll.vco); /* assert sdram outresetall */ - writel(cfg->sdram_vco_base | VCO_EN_BASE| - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1), + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, &clock_manager_base->sdr_pll.vco); /* deassert main outresetall */ @@ -309,9 +277,8 @@ void cm_basic_init(const cm_config_t *cfg) &clock_manager_base->per_pll.vco); /* deassert sdram outresetall */ - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | - cfg->sdram_vco_base | VCO_EN_BASE, - &clock_manager_base->sdr_pll.vco); + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->sdr_pll.vco); /* * now that we've toggled outreset all, all the clocks @@ -335,18 +302,10 @@ void cm_basic_init(const cm_config_t *cfg) CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); /* Take all three PLLs out of bypass when safe mode is cleared. */ - cm_write_bypass( - CLKMGR_BYPASS_PERPLLSRC_SET( - CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_SDRPLLSRC_SET( - CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) | - CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) | - CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE)); + cm_write_bypass(0); /* clear safe mode */ - cm_write_ctrl(readl(&clock_manager_base->ctrl) | - CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK)); + cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); /* * now that safe mode is clear with clocks gated @@ -367,9 +326,11 @@ static unsigned int cm_get_main_vco_clk_hz(void) /* get the main VCO clock */ reg = readl(&clock_manager_base->main_pll.vco); - clock = CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = CONFIG_HPS_CLK_OSC1_HZ; + clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1; return clock; } @@ -380,7 +341,8 @@ static unsigned int cm_get_per_vco_clk_hz(void) /* identify PER PLL clock source */ reg = readl(&clock_manager_base->per_pll.vco); - reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> + CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; if (reg == CLKMGR_VCO_SSRC_EOSC1) clock = CONFIG_HPS_CLK_OSC1_HZ; else if (reg == CLKMGR_VCO_SSRC_EOSC2) @@ -390,8 +352,10 @@ static unsigned int cm_get_per_vco_clk_hz(void) /* get the PER VCO clock */ reg = readl(&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1; return clock; } @@ -416,7 +380,8 @@ unsigned long cm_get_sdram_clk_hz(void) /* identify SDRAM PLL clock source */ reg = readl(&clock_manager_base->sdr_pll.vco); - reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg); + reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET; if (reg == CLKMGR_VCO_SSRC_EOSC1) clock = CONFIG_HPS_CLK_OSC1_HZ; else if (reg == CLKMGR_VCO_SSRC_EOSC2) @@ -426,12 +391,15 @@ unsigned long cm_get_sdram_clk_hz(void) /* get the SDRAM VCO clock */ reg = readl(&clock_manager_base->sdr_pll.vco); - clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1); + clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1; /* get the SDRAM (DDR_DQS) clock */ reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); - reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg); + reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; clock /= (reg + 1); return clock; @@ -443,7 +411,8 @@ unsigned int cm_get_l4_sp_clk_hz(void) /* identify the source of L4 SP clock */ reg = readl(&clock_manager_base->main_pll.l4src); - reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg); + reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { clock = cm_get_main_vco_clk_hz(); @@ -463,7 +432,8 @@ unsigned int cm_get_l4_sp_clk_hz(void) /* get the L4 SP clock which supplied to UART */ reg = readl(&clock_manager_base->main_pll.maindiv); - reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg); + reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET; clock = clock / (1 << reg); return clock; @@ -475,7 +445,8 @@ unsigned int cm_get_mmc_controller_clk_hz(void) /* identify the source of MMC clock */ reg = readl(&clock_manager_base->per_pll.src); - reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg); + reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET; if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; @@ -504,7 +475,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void) /* identify the source of QSPI clock */ reg = readl(&clock_manager_base->per_pll.src); - reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg); + reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >> + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET; if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 27efde6..bd9f338 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -19,6 +19,31 @@ DECLARE_GLOBAL_DATA_PTR; +#define MAIN_VCO_BASE ( \ + (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \ + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \ + ) + +#define PERI_VCO_BASE ( \ + (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \ + CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \ + (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \ + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \ + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \ + ) + +#define SDR_VCO_BASE ( \ + (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \ + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \ + (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \ + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \ + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ + ) + u32 spl_boot_device(void) { return BOOT_DEVICE_RAM; @@ -33,86 +58,87 @@ void spl_board_init(void) cm_config_t cm_default_cfg = { /* main group */ MAIN_VCO_BASE, - CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT), - CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT), - CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT), - CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT), - CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT), - CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT), - CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) | - CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) | - CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) | - CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK), - CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET( - CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) | - CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET( - CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK), - CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET( - CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK), - CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET( - CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) | - CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET( - CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP), + (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT << + CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT << + CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT << + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT << + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT << + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT << + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK << + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK << + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK << + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP << + CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP << + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET), /* peripheral group */ PERI_VCO_BASE, - CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT), - CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT), - CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT), - CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT), - CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT), - CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT), - CLKMGR_PERPLLGRP_DIV_USBCLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_USBCLK) | - CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) | - CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) | - CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK), - CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET( - CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK), - CLKMGR_PERPLLGRP_SRC_QSPI_SET( - CONFIG_HPS_PERPLLGRP_SRC_QSPI) | - CLKMGR_PERPLLGRP_SRC_NAND_SET( - CONFIG_HPS_PERPLLGRP_SRC_NAND) | - CLKMGR_PERPLLGRP_SRC_SDMMC_SET( - CONFIG_HPS_PERPLLGRP_SRC_SDMMC), + (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT << + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT << + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT << + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT << + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT << + CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT << + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_DIV_USBCLK << + CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK << + CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK << + CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK << + CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET), + (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK << + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET), + (CONFIG_HPS_PERPLLGRP_SRC_QSPI << + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) | + (CONFIG_HPS_PERPLLGRP_SRC_NAND << + CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) | + (CONFIG_HPS_PERPLLGRP_SRC_SDMMC << + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET), /* sdram pll group */ SDR_VCO_BASE, - CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) | - CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT), - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) | - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT), - CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) | - CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT), - CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) | - CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT), + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE << + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT << + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE << + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT << + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE << + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT << + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE << + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET), + }; debug("Freezing all I/O banks\n"); diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index d2a9b48..bc91662 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -118,165 +118,187 @@ struct socfpga_clock_manager { u32 _pad_0xe8_0x200[70]; }; -#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 -#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) - -#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) -#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) -#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) -#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) - -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 -#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 +#define CLKMGR_CTRL_SAFEMODE (1 << 0) +#define CLKMGR_CTRL_SAFEMODE_OFFSET 0 + +#define CLKMGR_BYPASS_PERPLLSRC (1 << 4) +#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 +#define CLKMGR_BYPASS_PERPLL (1 << 3) +#define CLKMGR_BYPASS_PERPLL_OFFSET 3 +#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2) +#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 +#define CLKMGR_BYPASS_SDRPLL (1 << 1) +#define CLKMGR_BYPASS_SDRPLL_OFFSET 1 +#define CLKMGR_BYPASS_MAINPLL (1 << 0) +#define CLKMGR_BYPASS_MAINPLL_OFFSET 0 + +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 + +#define CLKMGR_STAT_BUSY (1 << 0) /* Main PLL */ -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) -#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) -#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) -#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d - -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 -#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 -#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 -#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 -#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 -#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 - -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7) -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) - -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) - -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) - -#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1) -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 -#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 -#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0) +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1) +#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2) +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d + +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 +#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 +#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 + +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 + +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c + +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 + +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0) +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 +#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 +#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 /* Per PLL */ -#define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) -#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) -#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) -#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) -#define CLKMGR_VCO_SSRC_EOSC1 0x0 -#define CLKMGR_VCO_SSRC_EOSC2 0x1 -#define CLKMGR_VCO_SSRC_F2S 0x2 - -#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 -#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 - -#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0) -#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) -#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007) - -#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) - -#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4) -#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) -#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 -#define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0) -#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 -#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 -#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 -#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 -#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 -#define CLKMGR_QSPI_CLK_SRC_PER 0x2 +#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_VCO_SSRC_EOSC1 0x0 +#define CLKMGR_VCO_SSRC_EOSC2 0x1 +#define CLKMGR_VCO_SSRC_F2S 0x2 + +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 + +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 + +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff + +#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 +#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c +#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 +#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 +#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 +#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 +#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 +#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 +#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 +#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 +#define CLKMGR_QSPI_CLK_SRC_PER 0x2 /* SDR PLL */ -#define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) -#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) -#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) -#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) -#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) - -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) - -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) - -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) - -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) - -#define MAIN_VCO_BASE \ - (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \ - CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER)) - -#define PERI_VCO_BASE \ - (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \ - CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \ - CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER)) - -#define SDR_VCO_BASE \ - (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \ - CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \ - CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER)) +#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 #endif /* _CLOCK_MANAGER_H_ */ -- cgit v1.1 From 036ba54f5b713f60c17c4a28e4ad4d59fa913db9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 19:54:32 +0200 Subject: arm: socfpga: clock: Sync with reference code Add the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/clock_manager.c | 42 ++++++++++++++--------- arch/arm/include/asm/arch-socfpga/clock_manager.h | 3 ++ 2 files changed, 29 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index 1cf0d77..d869f47 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -16,9 +16,16 @@ static const struct socfpga_clock_manager *clock_manager_base = static void cm_wait_for_lock(uint32_t mask) { register uint32_t inter_val; + uint32_t retry = 0; do { inter_val = readl(&clock_manager_base->inter) & mask; - } while (inter_val != mask); + if (inter_val == mask) + retry++; + else + retry = 0; + if (retry >= 10) + break; + } while (1); } /* function to poll in the fsm busy bit */ @@ -114,15 +121,15 @@ void cm_basic_init(const cm_config_t *cfg) cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | CLKMGR_BYPASS_MAINPLL); - /* - * Put all plls VCO registers back to reset value. - * Some code might have messed with them. - */ - writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE, + /* Put all plls VCO registers back to reset value. */ + writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, &clock_manager_base->main_pll.vco); - writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE, + writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, &clock_manager_base->per_pll.vco); - writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE, + writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, &clock_manager_base->sdr_pll.vco); /* @@ -147,14 +154,9 @@ void cm_basic_init(const cm_config_t *cfg) * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. */ - writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->main_pll.vco); - - writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->per_pll.vco); - - writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->sdr_pll.vco); + writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); + writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); + writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); /* * Time starts here @@ -189,6 +191,9 @@ void cm_basic_init(const cm_config_t *cfg) writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); /* Peri pernandsdmmcclk */ + writel(cfg->mainnandsdmmcclk, + &clock_manager_base->main_pll.mainnandsdmmcclk); + writel(cfg->pernandsdmmcclk, &clock_manager_base->per_pll.pernandsdmmcclk); @@ -318,6 +323,11 @@ void cm_basic_init(const cm_config_t *cfg) writel(~0, &clock_manager_base->main_pll.en); writel(~0, &clock_manager_base->per_pll.en); writel(~0, &clock_manager_base->sdr_pll.en); + + /* Clear the loss of lock bits (write 1 to clear) */ + writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK, + &clock_manager_base->inter); } static unsigned int cm_get_main_vco_clk_hz(void) diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index bc91662..fa49f6a 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -135,6 +135,9 @@ struct socfpga_clock_manager { #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010 +#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008 #define CLKMGR_STAT_BUSY (1 << 0) -- cgit v1.1 From 2110eeaf0fdf9b3b200076554d266459ca7ac26d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: timer: Pull the timer reload value from config file The timer reload value is a property of the timer hardware and there is no reason for this to be configurable. Place this into the timer driver just like on the other hardware. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/timer.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c index 58fc789..253cde3 100644 --- a/arch/arm/cpu/armv7/socfpga/timer.c +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -8,6 +8,8 @@ #include #include +#define TIMER_LOAD_VAL 0xFFFFFFFF + static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; /* -- cgit v1.1 From e9d6a20034788258bc5008dc2665aabe9ce28b1c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: reset: Add EMAC reset functions Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/reset_manager.c | 17 +++++++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 3 +++ 2 files changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 5d7aba4..badc569 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -49,3 +49,20 @@ void reset_deassert_peripherals_handoff(void) { writel(0, &reset_manager_base->per_mod_reset); } + +/* Change the reset state for EMAC 0 and EMAC 1 */ +void socfpga_emac_reset(int enable) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + if (enable) { + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); + } else { +#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS) + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); +#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS) + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); +#endif + } +} diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 18506e6..3c5ab40 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,7 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); struct socfpga_reset_manager { @@ -29,6 +30,8 @@ struct socfpga_reset_manager { #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 #endif +#define RSTMGR_PERMODRST_EMAC0_LSB 0 +#define RSTMGR_PERMODRST_EMAC1_LSB 1 #define RSTMGR_PERMODRST_L4WD0_LSB 6 #endif /* _RESET_MANAGER_H_ */ -- cgit v1.1 From 45d6e677106703139d2e3c10fa2d1168fb25309e Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: misc: Add proper ethernet initialization Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek --- arch/arm/cpu/armv7/socfpga/misc.c | 58 ++++++++++++++++------ arch/arm/include/asm/arch-socfpga/system_manager.h | 9 ++++ 2 files changed, 52 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index b633615..872ea59 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -9,15 +9,58 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_DESIGNWARE_ETH +int cpu_eth_init(bd_t *bis) +{ +#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS + const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; +#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS + const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; +#else +#error "Incorrect CONFIG_EMAC_BASE value!" +#endif + + /* Initialize EMAC. This needs to be done at least once per boot. */ + + /* + * Putting the EMAC controller to reset when configuring the PHY + * interface select at System Manager + */ + socfpga_emac_reset(1); + + /* Clearing emac0 PHY interface select to 0 */ + clrbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); + + /* configure to PHY interface select choosed */ + setbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); + + /* Release the EMAC controller from reset */ + socfpga_emac_reset(0); + + /* initialize and register the emac */ + return designware_initialize(CONFIG_EMAC_BASE, + CONFIG_PHY_INTERFACE_MODE); +} +#endif + #if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information @@ -54,18 +97,3 @@ int misc_init_r(void) { return 0; } - - -/* - * DesignWare Ethernet initialization - */ -int cpu_eth_init(bd_t *bis) -{ -#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD) - /* initialize and register the emac */ - return designware_initialize(CONFIG_EMAC_BASE, - CONFIG_PHY_INTERFACE_MODE); -#else - return 0; -#endif -} diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index 90d2720..071ec4f 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -134,4 +134,13 @@ struct socfpga_system_manager { #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) +/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 + #endif /* _SYSTEM_MANAGER_H_ */ -- cgit v1.1 From 4e736869c6e0df7a955fd000681d6ceea636928c Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: misc: Add SD controller init Add CPU function to register and initialize the dw_mmc SD controller. This allows us to use the HPS SDMMC block. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek --- arch/arm/cpu/armv7/socfpga/misc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 872ea59..bf5c668 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -10,6 +10,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -61,6 +62,18 @@ int cpu_eth_init(bd_t *bis) } #endif +#ifdef CONFIG_DWMMC +/* + * Initializes MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ + return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, + CONFIG_HPS_SDMMC_BUSWIDTH, 0); +} +#endif + #if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information -- cgit v1.1 From d5a3d3c9efc2738139b8b8a7c191b8b0d533aaa8 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: misc: Align print_cpuinfo() output Cosmetic change to the print_cpuinfo() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek --- arch/arm/cpu/armv7/socfpga/misc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index bf5c668..f41c329 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -80,7 +80,7 @@ int cpu_mmc_init(bd_t *bis) */ int print_cpuinfo(void) { - puts("CPU : Altera SOCFPGA Platform\n"); + puts("CPU: Altera SoCFPGA Platform\n"); return 0; } #endif -- cgit v1.1 From 230fe9b202ff0ca396ad9a564816cc87d42daa6e Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: fpga: Add SoCFPGA FPGA programming interface Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support. --- arch/arm/cpu/armv7/socfpga/Makefile | 3 +- arch/arm/cpu/armv7/socfpga/fpga_manager.c | 78 ++++++++++++++++++++++++ arch/arm/cpu/armv7/socfpga/misc.c | 36 +++++++++++ arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 +++++++++++++++++++++++ 4 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/fpga_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/fpga_manager.h (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index eb33f2c..8b6e108 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -8,5 +8,6 @@ # obj-y := lowlevel_init.o -obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o +obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ + fpga_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/fpga_manager.c b/arch/arm/cpu/armv7/socfpga/fpga_manager.c new file mode 100644 index 0000000..43fd2fe --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/fpga_manager.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * This file contains only support functions used also by the SoCFPGA + * platform code, the real meat is located in drivers/fpga/socfpga.c . + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Timeout count */ +#define FPGA_TIMEOUT_CNT 0x1000000 + +static struct socfpga_fpga_manager *fpgamgr_regs = + (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; + +/* Check whether FPGA Init_Done signal is high */ +static int is_fpgamgr_initdone_high(void) +{ + unsigned long val; + + val = readl(&fpgamgr_regs->gpio_ext_porta); + return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK; +} + +/* Get the FPGA mode */ +int fpgamgr_get_mode(void) +{ + unsigned long val; + + val = readl(&fpgamgr_regs->stat); + return val & FPGAMGRREGS_STAT_MODE_MASK; +} + +/* Check whether FPGA is ready to be accessed */ +int fpgamgr_test_fpga_ready(void) +{ + /* Check for init done signal */ + if (!is_fpgamgr_initdone_high()) + return 0; + + /* Check again to avoid false glitches */ + if (!is_fpgamgr_initdone_high()) + return 0; + + if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE) + return 0; + + return 1; +} + +/* Poll until FPGA is ready to be accessed or timeout occurred */ +int fpgamgr_poll_fpga_ready(void) +{ + unsigned long i; + + /* If FPGA is blank, wait till WD invoke warm reset */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + /* check for init done signal */ + if (!is_fpgamgr_initdone_high()) + continue; + /* check again to avoid false glitches */ + if (!is_fpgamgr_initdone_high()) + continue; + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index f41c329..b07d97e 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -93,6 +94,39 @@ int overwrite_console(void) } #endif +#ifdef CONFIG_FPGA +/* + * FPGA programming support for SoC FPGA Cyclone V + */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Altera_SoCFPGA, + /* Interface type */ + fast_passive_parallel, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + +/* add device descriptor to FPGA device table */ +static void socfpga_fpga_add(void) +{ + int i; + fpga_init(); + for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) + fpga_add(fpga_altera, &altera_fpga[i]); +} +#else +static inline void socfpga_fpga_add(void) {} +#endif + int arch_cpu_init(void) { /* @@ -108,5 +142,7 @@ int arch_cpu_init(void) int misc_init_r(void) { + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); return 0; } diff --git a/arch/arm/include/asm/arch-socfpga/fpga_manager.h b/arch/arm/include/asm/arch-socfpga/fpga_manager.h new file mode 100644 index 0000000..a077e22 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/fpga_manager.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FPGA_MANAGER_H_ +#define _FPGA_MANAGER_H_ + +#include + +struct socfpga_fpga_manager { + /* FPGA Manager Module */ + u32 stat; /* 0x00 */ + u32 ctrl; + u32 dclkcnt; + u32 dclkstat; + u32 gpo; /* 0x10 */ + u32 gpi; + u32 misci; /* 0x18 */ + u32 _pad_0x1c_0x82c[517]; + + /* Configuration Monitor (MON) Registers */ + u32 gpio_inten; /* 0x830 */ + u32 gpio_intmask; + u32 gpio_inttype_level; + u32 gpio_int_polarity; + u32 gpio_intstatus; /* 0x840 */ + u32 gpio_raw_intstatus; + u32 _pad_0x848; + u32 gpio_porta_eoi; + u32 gpio_ext_porta; /* 0x850 */ + u32 _pad_0x854_0x85c[3]; + u32 gpio_1s_sync; /* 0x860 */ + u32 _pad_0x864_0x868[2]; + u32 gpio_ver_id_code; + u32 gpio_config_reg2; /* 0x870 */ + u32 gpio_config_reg1; +}; + +#define FPGAMGRREGS_STAT_MODE_MASK 0x7 +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 +#define FPGAMGRREGS_STAT_MSEL_LSB 3 + +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 +#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 +#define FPGAMGRREGS_CTRL_EN_MASK 0x1 +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 + +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 + +/* FPGA Mode */ +#define FPGAMGRREGS_MODE_FPGAOFF 0x0 +#define FPGAMGRREGS_MODE_RESETPHASE 0x1 +#define FPGAMGRREGS_MODE_CFGPHASE 0x2 +#define FPGAMGRREGS_MODE_INITPHASE 0x3 +#define FPGAMGRREGS_MODE_USERMODE 0x4 +#define FPGAMGRREGS_MODE_UNKNOWN 0x5 + +/* FPGA CD Ratio Value */ +#define CDRATIO_x1 0x0 +#define CDRATIO_x2 0x1 +#define CDRATIO_x4 0x2 +#define CDRATIO_x8 0x3 + +/* SoCFPGA support functions */ +int fpgamgr_test_fpga_ready(void); +int fpgamgr_poll_fpga_ready(void); +int fpgamgr_get_mode(void); + +#endif /* _FPGA_MANAGER_H_ */ -- cgit v1.1 From abb25f4e9529c1b91d651c74af9bd3f1c955437b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: reset: Add function to reset FPGA bridges Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/reset_manager.c | 38 +++++++++++++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 2 ++ 2 files changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index badc569..1d3a95d 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,43 @@ void reset_deassert_peripherals_handoff(void) writel(0, &reset_manager_base->per_mod_reset); } +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +void socfpga_bridges_reset(int enable) +{ + /* For SoCFPGA-VT, this is NOP. */ +} +#else + +#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 +#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 +#define L3REGS_REMAP_OCRAM_MASK 0x01 + +void socfpga_bridges_reset(int enable) +{ + const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | + L3REGS_REMAP_HPS2FPGA_MASK | + L3REGS_REMAP_OCRAM_MASK; + + if (enable) { + /* brdmodrst */ + writel(0xffffffff, &reset_manager_base->brg_mod_reset); + } else { + /* Check signal from FPGA. */ + if (fpgamgr_poll_fpga_ready()) { + /* FPGA not ready. Wait for watchdog timeout. */ + printf("%s: fpga not ready, hanging.\n", __func__); + hang(); + } + + /* brdmodrst */ + writel(0, &reset_manager_base->brg_mod_reset); + + /* Remap the bridges into memory map */ + writel(l3mask, SOCFPGA_L3REGS_ADDRESS); + } +} +#endif + /* Change the reset state for EMAC 0 and EMAC 1 */ void socfpga_emac_reset(int enable) { diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 3c5ab40..1857b80 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,8 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +void socfpga_bridges_reset(int enable); + void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); -- cgit v1.1 From 807abb18f1376bcd674540e374f2ab7503caea51 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: sysmgr: Add FPGA bits into system manager Add missing system manager bits from Altera U-Boot to make the code comparable. These are the bits which depend on the FPGA manager. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/system_manager.c | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c index 07c72e4..11f7bad 100644 --- a/arch/arm/cpu/armv7/socfpga/system_manager.c +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c @@ -15,6 +15,43 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /* + * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. + * The value is not wrote to SYSMGR.FPGAINTF.MODULE but + * CONFIG_SYSMGR_ISWGRP_HANDOFF. + */ +static void populate_sysmgr_fpgaintf_module(void) +{ + uint32_t handoff_val = 0; + + /* ISWGRP_HANDOFF_FPGAINTF */ + writel(0, &sysmgr_regs->iswgrp_handoff[2]); + + /* Enable the signal for those HPS peripherals that use FPGA. */ + if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_NAND; + if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC1; + if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SDMMC; + if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC0; + if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM0; + if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM1; + + /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE + based on pinmux setting */ + setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val); + + handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]); + if (fpgamgr_test_fpga_ready()) { + /* Enable the required signals only */ + writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module); + } +} + +/* * Configure all the pin muxes */ void sysmgr_pinmux_init(void) @@ -26,4 +63,6 @@ void sysmgr_pinmux_init(void) writel(sys_mgr_init_table[i], regs); regs += sizeof(regs); } + + populate_sysmgr_fpgaintf_module(); } -- cgit v1.1 From 181d363852b8b92e2175fd8ea220b7db444796f1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 06:28:01 +0200 Subject: arm: socfpga: scu: Add SCU register file Add the Snoop Control Unit register definition file. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/include/asm/arch-socfpga/scu.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/scu.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-socfpga/scu.h b/arch/arm/include/asm/arch-socfpga/scu.h new file mode 100644 index 0000000..7a5b074 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scu.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SOCFPGA_SCU_H__ +#define __SOCFPGA_SCU_H__ + +struct scu_registers { + u32 ctrl; /* 0x00 */ + u32 cfg; + u32 cpsr; + u32 iassr; + u32 _pad_0x10_0x3c[12]; /* 0x10 */ + u32 fsar; /* 0x40 */ + u32 fear; + u32 _pad_0x48_0x50[2]; + u32 acr; /* 0x54 */ + u32 sacr; +}; + +#endif /* __SOCFPGA_SCU_H__ */ -- cgit v1.1 From 7056efcc32081256af6172611874709c780f2007 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 06:03:38 +0200 Subject: arm: socfpga: nic301: Add NIC-301 GPV register file Add register definition for the NIC-301 used on SoCFPGA. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/include/asm/arch-socfpga/nic301.h | 195 +++++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/nic301.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-socfpga/nic301.h b/arch/arm/include/asm/arch-socfpga/nic301.h new file mode 100644 index 0000000..3c8ab31 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/nic301.h @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _NIC301_REGISTERS_H_ +#define _NIC301_REGISTERS_H_ + +struct nic301_registers { + u32 remap; /* 0x0 */ + /* Security Register Group */ + u32 _pad_0x4_0x8[1]; + u32 l4main; + u32 l4sp; + u32 l4mp; /* 0x10 */ + u32 l4osc1; + u32 l4spim; + u32 stm; + u32 lwhps2fpgaregs; /* 0x20 */ + u32 _pad_0x24_0x28[1]; + u32 usb1; + u32 nanddata; + u32 _pad_0x30_0x80[20]; + u32 usb0; /* 0x80 */ + u32 nandregs; + u32 qspidata; + u32 fpgamgrdata; + u32 hps2fpgaregs; /* 0x90 */ + u32 acp; + u32 rom; + u32 ocram; + u32 sdrdata; /* 0xA0 */ + u32 _pad_0xa4_0x1fd0[1995]; + /* ID Register Group */ + u32 periph_id_4; /* 0x1FD0 */ + u32 _pad_0x1fd4_0x1fe0[3]; + u32 periph_id_0; /* 0x1FE0 */ + u32 periph_id_1; + u32 periph_id_2; + u32 periph_id_3; + u32 comp_id_0; /* 0x1FF0 */ + u32 comp_id_1; + u32 comp_id_2; + u32 comp_id_3; + u32 _pad_0x2000_0x2008[2]; + /* L4 MAIN */ + u32 l4main_fn_mod_bm_iss; + u32 _pad_0x200c_0x3008[1023]; + /* L4 SP */ + u32 l4sp_fn_mod_bm_iss; + u32 _pad_0x300c_0x4008[1023]; + /* L4 MP */ + u32 l4mp_fn_mod_bm_iss; + u32 _pad_0x400c_0x5008[1023]; + /* L4 OSC1 */ + u32 l4osc_fn_mod_bm_iss; + u32 _pad_0x500c_0x6008[1023]; + /* L4 SPIM */ + u32 l4spim_fn_mod_bm_iss; + u32 _pad_0x600c_0x7008[1023]; + /* STM */ + u32 stm_fn_mod_bm_iss; + u32 _pad_0x700c_0x7108[63]; + u32 stm_fn_mod; + u32 _pad_0x710c_0x8008[959]; + /* LWHPS2FPGA */ + u32 lwhps2fpga_fn_mod_bm_iss; + u32 _pad_0x800c_0x8108[63]; + u32 lwhps2fpga_fn_mod; + u32 _pad_0x810c_0xa008[1983]; + /* USB1 */ + u32 usb1_fn_mod_bm_iss; + u32 _pad_0xa00c_0xa044[14]; + u32 usb1_ahb_cntl; + u32 _pad_0xa048_0xb008[1008]; + /* NANDDATA */ + u32 nanddata_fn_mod_bm_iss; + u32 _pad_0xb00c_0xb108[63]; + u32 nanddata_fn_mod; + u32 _pad_0xb10c_0x20008[21439]; + /* USB0 */ + u32 usb0_fn_mod_bm_iss; + u32 _pad_0x2000c_0x20044[14]; + u32 usb0_ahb_cntl; + u32 _pad_0x20048_0x21008[1008]; + /* NANDREGS */ + u32 nandregs_fn_mod_bm_iss; + u32 _pad_0x2100c_0x21108[63]; + u32 nandregs_fn_mod; + u32 _pad_0x2110c_0x22008[959]; + /* QSPIDATA */ + u32 qspidata_fn_mod_bm_iss; + u32 _pad_0x2200c_0x22044[14]; + u32 qspidata_ahb_cntl; + u32 _pad_0x22048_0x23008[1008]; + /* FPGAMGRDATA */ + u32 fpgamgrdata_fn_mod_bm_iss; + u32 _pad_0x2300c_0x23040[13]; + u32 fpgamgrdata_wr_tidemark; /* 0x23040 */ + u32 _pad_0x23044_0x23108[49]; + u32 fn_mod; + u32 _pad_0x2310c_0x24008[959]; + /* HPS2FPGA */ + u32 hps2fpga_fn_mod_bm_iss; + u32 _pad_0x2400c_0x24040[13]; + u32 hps2fpga_wr_tidemark; /* 0x24040 */ + u32 _pad_0x24044_0x24108[49]; + u32 hps2fpga_fn_mod; + u32 _pad_0x2410c_0x25008[959]; + /* ACP */ + u32 acp_fn_mod_bm_iss; + u32 _pad_0x2500c_0x25108[63]; + u32 acp_fn_mod; + u32 _pad_0x2510c_0x26008[959]; + /* Boot ROM */ + u32 bootrom_fn_mod_bm_iss; + u32 _pad_0x2600c_0x26108[63]; + u32 bootrom_fn_mod; + u32 _pad_0x2610c_0x27008[959]; + /* On-chip RAM */ + u32 ocram_fn_mod_bm_iss; + u32 _pad_0x2700c_0x27040[13]; + u32 ocram_wr_tidemark; /* 0x27040 */ + u32 _pad_0x27044_0x27108[49]; + u32 ocram_fn_mod; + u32 _pad_0x2710c_0x42024[27590]; + /* DAP */ + u32 dap_fn_mod2; + u32 dap_fn_mod_ahb; + u32 _pad_0x4202c_0x42100[53]; + u32 dap_read_qos; /* 0x42100 */ + u32 dap_write_qos; + u32 dap_fn_mod; + u32 _pad_0x4210c_0x43100[1021]; + /* MPU */ + u32 mpu_read_qos; /* 0x43100 */ + u32 mpu_write_qos; + u32 mpu_fn_mod; + u32 _pad_0x4310c_0x44028[967]; + /* SDMMC */ + u32 sdmmc_fn_mod_ahb; + u32 _pad_0x4402c_0x44100[53]; + u32 sdmmc_read_qos; /* 0x44100 */ + u32 sdmmc_write_qos; + u32 sdmmc_fn_mod; + u32 _pad_0x4410c_0x45100[1021]; + /* DMA */ + u32 dma_read_qos; /* 0x45100 */ + u32 dma_write_qos; + u32 dma_fn_mod; + u32 _pad_0x4510c_0x46040[973]; + /* FPGA2HPS */ + u32 fpga2hps_wr_tidemark; /* 0x46040 */ + u32 _pad_0x46044_0x46100[47]; + u32 fpga2hps_read_qos; /* 0x46100 */ + u32 fpga2hps_write_qos; + u32 fpga2hps_fn_mod; + u32 _pad_0x4610c_0x47100[1021]; + /* ETR */ + u32 etr_read_qos; /* 0x47100 */ + u32 etr_write_qos; + u32 etr_fn_mod; + u32 _pad_0x4710c_0x48100[1021]; + /* EMAC0 */ + u32 emac0_read_qos; /* 0x48100 */ + u32 emac0_write_qos; + u32 emac0_fn_mod; + u32 _pad_0x4810c_0x49100[1021]; + /* EMAC1 */ + u32 emac1_read_qos; /* 0x49100 */ + u32 emac1_write_qos; + u32 emac1_fn_mod; + u32 _pad_0x4910c_0x4a028[967]; + /* USB0 */ + u32 usb0_fn_mod_ahb; + u32 _pad_0x4a02c_0x4a100[53]; + u32 usb0_read_qos; /* 0x4A100 */ + u32 usb0_write_qos; + u32 usb0_fn_mod; + u32 _pad_0x4a10c_0x4b100[1021]; + /* NAND */ + u32 nand_read_qos; /* 0x4B100 */ + u32 nand_write_qos; + u32 nand_fn_mod; + u32 _pad_0x4b10c_0x4c028[967]; + /* USB1 */ + u32 usb1_fn_mod_ahb; + u32 _pad_0x4c02c_0x4c100[53]; + u32 usb1_read_qos; /* 0x4C100 */ + u32 usb1_write_qos; + u32 usb1_fn_mod; +}; + +#endif /* _NIC301_REGISTERS_H_ */ -- cgit v1.1 From 60d804c2f3ddd0071348c6e65999e19b4d07d16a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 03:58:22 +0200 Subject: arm: socfpga: pl310: Map SDRAM to 0x0 Configure the PL310 address filter to make sure DRAM is mapped to 0x0. This code also configures the "remap" register of NIC-301 and sets the required 'mpuzero' bit. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/misc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index b07d97e..0fc26c2 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -12,11 +12,17 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static struct nic301_registers *nic301_regs = + (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; int dram_init(void) { @@ -142,6 +148,14 @@ int arch_cpu_init(void) int misc_init_r(void) { + /* Configure the L2 controller to make SDRAM start at 0 */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET + writel(0x2, &nic301_regs->remap); +#else + writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + writel(0x1, &pl310->pl310_addr_filter_start); +#endif + /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); return 0; -- cgit v1.1 From 13e81d45f80b58e57a78daf6850d4f3a6bc20d9e Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: nic301: Add NIC-301 configuration code Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA . The code sets the access permissions for the CPU to the AMBA slaves such that the CPU can access them in both secure and non-secure mode. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek --- arch/arm/cpu/armv7/socfpga/misc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 0fc26c2..76186c5 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -23,6 +24,8 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; +static struct scu_registers *scu_regs = + (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; int dram_init(void) { @@ -146,8 +149,31 @@ int arch_cpu_init(void) return 0; } +/* + * Convert all NIC-301 AMBA slaves from secure to non-secure + */ +static void socfpga_nic301_slave_ns(void) +{ + writel(0x1, &nic301_regs->lwhps2fpgaregs); + writel(0x1, &nic301_regs->hps2fpgaregs); + writel(0x1, &nic301_regs->acp); + writel(0x1, &nic301_regs->rom); + writel(0x1, &nic301_regs->ocram); + writel(0x1, &nic301_regs->sdrdata); +} + int misc_init_r(void) { + socfpga_bridges_reset(1); + socfpga_nic301_slave_ns(); + + /* + * Private components security: + * U-Boot : configure private timer, global timer and cpu component + * access as non secure for kernel stage (as required by Linux) + */ + setbits_le32(&scu_regs->sacr, 0xfff); + /* Configure the L2 controller to make SDRAM start at 0 */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET writel(0x2, &nic301_regs->remap); -- cgit v1.1 From 4ab333b765db5cd00b297b4c0e3cd3af5fe320fc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Sep 2014 13:57:40 +0200 Subject: arm: socfpga: Move cache_enable to CPU code Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud Cc: Wolfgang Denk Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/misc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 76186c5..7f9d7f0 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -33,6 +33,16 @@ int dram_init(void) return 0; } +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + /* * DesignWare Ethernet initialization */ -- cgit v1.1 From 7249fafb1a96c014dfc0d4ccf6ea937643199e67 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: Add command to control HPS-FPGA bridges Add command to enable and disable the bridges between HPS and FPGA. This patch does have a checkpatch issue with the assembler portion, checkpatch correctly complains that there should be no whitespace before quoted newline. I do not agree that fixing this specific checkpatch issue will improve the readability, thus this one is not addressed. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud Cc: Wolfgang Denk --- arch/arm/cpu/armv7/socfpga/misc.c | 75 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 7f9d7f0..0eab264 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -22,6 +22,8 @@ static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static struct socfpga_reset_manager *reset_manager_base = + (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = @@ -172,8 +174,14 @@ static void socfpga_nic301_slave_ns(void) writel(0x1, &nic301_regs->sdrdata); } +static uint32_t iswgrp_handoff[8]; + int misc_init_r(void) { + int i; + for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ + iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); + socfpga_bridges_reset(1); socfpga_nic301_slave_ns(); @@ -196,3 +204,70 @@ int misc_init_r(void) socfpga_fpga_add(); return 0; } + +static void socfpga_sdram_apply_static_cfg(void) +{ + const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; + const uint32_t applymask = 0x8; + uint32_t val = readl(staticcfg) | applymask; + + /* + * SDRAM staticcfg register specific: + * When applying the register setting, the CPU must not access + * SDRAM. Luckily for us, we can abuse i-cache here to help us + * circumvent the SDRAM access issue. The idea is to make sure + * that the code is in one full i-cache line by branching past + * it and back. Once it is in the i-cache, we execute the core + * of the code and apply the register settings. + * + * The code below uses 7 instructions, while the Cortex-A9 has + * 32-byte cachelines, thus the limit is 8 instructions total. + */ + asm volatile( + ".align 5 \n" + " b 2f \n" + "1: str %0, [%1] \n" + " dsb \n" + " isb \n" + " b 3f \n" + "2: b 1b \n" + "3: nop \n" + : : "r"(val), "r"(staticcfg) : "memory", "cc"); +} + +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + argv++; + + switch (*argv[0]) { + case 'e': /* Enable */ + writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); + socfpga_sdram_apply_static_cfg(); + writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); + writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[1], &nic301_regs->remap); + break; + case 'd': /* Disable */ + writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); + socfpga_sdram_apply_static_cfg(); + writel(0, &reset_manager_base->brg_mod_reset); + writel(1, &nic301_regs->remap); + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" +); -- cgit v1.1 From 3160b1b98603cba3c480f70e153b259171d3e4a6 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:02 +0300 Subject: OMAP5+: sata/scsi: Implement scsi_init() On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: Roger Quadros --- arch/arm/cpu/armv7/omap-common/sata.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index cad4fee..131d082 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -74,3 +74,9 @@ int init_sata(int dev) return ret; } + +/* On OMAP platforms SATA provides the SCSI subsystem */ +void scsi_init(void) +{ + init_sata(0); +} -- cgit v1.1 From d59baeb76f911d0391e73e5f6068e55ea48514f8 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:03 +0300 Subject: ARM: OMAP5+: sata: Move scsi_scan() to the right place scsi_scan() must be called as part of scsi_init() and not as part of sata_init(). Signed-off-by: Roger Quadros --- arch/arm/cpu/armv7/omap-common/sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index 131d082..3b4dd3f 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -70,7 +70,6 @@ int init_sata(int dev) writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); ret = ahci_init(DWC_AHSATA_BASE); - scsi_scan(1); return ret; } @@ -79,4 +78,5 @@ int init_sata(int dev) void scsi_init(void) { init_sata(0); + scsi_scan(1); } -- cgit v1.1 From 026330af41842e7752a291012428a5ddf2c06449 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Tue, 23 Sep 2014 21:10:26 +0300 Subject: ARM: keystone: clock: fix main pll ratio div definitions The definitions for div ratio supposed to be in hex and were added in dec by mistake. Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/clock_defs.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h index e545341..85a046b 100644 --- a/arch/arm/include/asm/arch-keystone/clock_defs.h +++ b/arch/arm/include/asm/arch-keystone/clock_defs.h @@ -102,10 +102,10 @@ static struct pllctl_regs *pllctl_regs[] = { #define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) #define PLL_BWADJ_HI_MASK 0xf -#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0) -#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0) -#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1) -#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4) -#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17) +#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1) +#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4) +#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17) #endif /* _CLOCK_DEFS_H_ */ -- cgit v1.1 From dc9617e0cee28808863cbb21f4528f89bc383923 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:57 +0900 Subject: powerpc: ppc4xx: remove board support for KAREF and METROBOX These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/ppc4xx/Kconfig | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 41b525c..7c645f1 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -226,12 +226,6 @@ config TARGET_ALPR config TARGET_P3P440 bool "Support p3p440" -config TARGET_KAREF - bool "Support KAREF" - -config TARGET_METROBOX - bool "Support METROBOX" - config TARGET_XPEDITE1000 bool "Support xpedite1000" @@ -306,8 +300,6 @@ source "board/mpl/pip405/Kconfig" source "board/pcs440ep/Kconfig" source "board/prodrive/alpr/Kconfig" source "board/prodrive/p3p440/Kconfig" -source "board/sandburst/karef/Kconfig" -source "board/sandburst/metrobox/Kconfig" source "board/sbc405/Kconfig" source "board/sc3/Kconfig" source "board/t3corp/Kconfig" -- cgit v1.1 From 1521cdc5303db2a3ec5a09231fbaa5831561bf71 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:58 +0900 Subject: powerpc: ppc4xx: remove board support for CRAYL1 This board has been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 7c645f1..d525ad3 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -106,9 +106,6 @@ config TARGET_FX12MM config TARGET_V5FX30TEVAL bool "Support v5fx30teval" -config TARGET_CRAYL1 - bool "Support CRAYL1" - config TARGET_CATCENTER bool "Support CATcenter" @@ -260,7 +257,6 @@ source "board/amcc/yosemite/Kconfig" source "board/amcc/yucca/Kconfig" source "board/avnet/fx12mm/Kconfig" source "board/avnet/v5fx30teval/Kconfig" -source "board/cray/L1/Kconfig" source "board/csb272/Kconfig" source "board/csb472/Kconfig" source "board/dave/PPChameleonEVB/Kconfig" -- cgit v1.1 From 9ed3246e19a42392bf0fd676dcbbe3539cc46ec1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:59 +0900 Subject: powerpc: ppc4xx: remove board support for bluestone This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 -- arch/powerpc/cpu/ppc4xx/cpu.c | 14 ------ arch/powerpc/cpu/ppc4xx/cpu_init.c | 4 +- arch/powerpc/cpu/ppc4xx/speed.c | 75 +-------------------------------- arch/powerpc/cpu/ppc4xx/start.S | 8 ++-- arch/powerpc/include/asm/apm821xx.h | 59 -------------------------- arch/powerpc/include/asm/ppc4xx-ebc.h | 3 +- arch/powerpc/include/asm/ppc4xx-isram.h | 10 ++--- arch/powerpc/include/asm/ppc4xx-sdram.h | 12 +++--- arch/powerpc/include/asm/ppc4xx-uic.h | 5 +-- arch/powerpc/include/asm/ppc4xx.h | 4 -- 11 files changed, 18 insertions(+), 180 deletions(-) delete mode 100644 arch/powerpc/include/asm/apm821xx.h (limited to 'arch') diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index d525ad3..56abe8d 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -52,9 +52,6 @@ config TARGET_ACADIA config TARGET_BAMBOO bool "Support bamboo" -config TARGET_BLUESTONE - bool "Support bluestone" - config TARGET_BUBINGA bool "Support bubinga" @@ -239,7 +236,6 @@ endchoice source "board/amcc/acadia/Kconfig" source "board/amcc/bamboo/Kconfig" -source "board/amcc/bluestone/Kconfig" source "board/amcc/bubinga/Kconfig" source "board/amcc/canyonlands/Kconfig" source "board/amcc/ebony/Kconfig" diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 6a48526..aab65d4 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -234,20 +234,6 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif -#if defined(CONFIG_APM821XX) -#define SDR0_PINSTP_SHIFT 29 -static char *bootstrap_str[] = { - "RESERVED", - "RESERVED", - "RESERVED", - "NAND (8 bits)", - "NOR (8 bits)", - "NOR (8 bits) w/PLL Bypassed", - "I2C (Addr 0x54)", - "I2C (Addr 0x52)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; -#endif #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index 0b27d29..2256123 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -284,7 +284,7 @@ cpu_init_f (void) reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \ - !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE) + !defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -440,7 +440,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 4baee77..3e1a701 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -171,7 +171,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -232,78 +232,6 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } -#if defined(CONFIG_APM821XX) - -void get_sys_info(sys_info_t *sysInfo) -{ - unsigned long plld; - unsigned long temp; - unsigned long mul; - unsigned long cpudv; - unsigned long plb2dv; - unsigned long ddr2dv; - - /* Calculate Forward divisor A and Feeback divisor */ - mfcpr(CPR0_PLLD, plld); - - temp = CPR0_PLLD_FWDVA(plld); - sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); - - temp = CPR0_PLLD_FDV(plld); - sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); - - /* Calculate OPB clock divisor */ - mfcpr(CPR0_OPBD, temp); - temp = CPR0_OPBD_OPBDV(temp); - sysInfo->pllOpbDiv = temp ? temp : 4; - - /* Calculate Peripheral clock divisor */ - mfcpr(CPR0_PERD, temp); - temp = CPR0_PERD_PERDV(temp); - sysInfo->pllExtBusDiv = temp ? temp : 4; - - /* Calculate CPU clock divisor */ - mfcpr(CPR0_CPUD, temp); - temp = CPR0_CPUD_CPUDV(temp); - cpudv = temp ? temp : 8; - - /* Calculate PLB2 clock divisor */ - mfcpr(CPR0_PLB2D, temp); - temp = CPR0_PLB2D_PLB2DV(temp); - plb2dv = temp ? temp : 4; - - /* Calculate DDR2 clock divisor */ - mfcpr(CPR0_DDR2D, temp); - temp = CPR0_DDR2D_DDR2DV(temp); - ddr2dv = temp ? temp : 4; - - /* Calculate 'M' based on feedback source */ - mfcpr(CPR0_PLLC, temp); - temp = CPR0_PLLC_SEL(temp); - if (temp == 0) { - /* PLL internal feedback */ - mul = sysInfo->pllFbkDiv; - } else { - /* PLL PerClk feedback */ - mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv - * plb2dv * 2 * sysInfo->pllOpbDiv * - sysInfo->pllExtBusDiv; - } - - /* Now calculate the individual clocks */ - sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); - sysInfo->freqProcessor = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv; - sysInfo->freqPLB = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv / plb2dv / 2; - sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; - sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; - sysInfo->freqDDR = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; - sysInfo->freqUART = sysInfo->freqPLB; -} - -#else /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -361,7 +289,6 @@ void get_sys_info (sys_info_t * sysInfo) return; } -#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 11b55d5..09a02d7 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -664,8 +664,7 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -694,7 +693,7 @@ _start: ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ - defined(CONFIG_460GT) || defined(CONFIG_APM821XX) + defined(CONFIG_460GT) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -707,8 +706,7 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h deleted file mode 100644 index d027866..0000000 --- a/arch/powerpc/include/asm/apm821xx.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _APM821XX_H_ -#define _APM821XX_H_ - -#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ - -/* Memory mapped registers */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) - -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) - -#define SDR0_SRST0_DMC 0x00200000 -#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ - -/* AHB config. */ -#define AHB_TOP 0xA4 -#define AHB_BOT 0xA5 - -/* clk divisors */ -#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ -#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ -#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ -#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ -#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ -#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ -#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ -#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ -#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ - -/* - + * Clocking Controller - + */ -#define CPR0_CLKUPD 0x0020 -#define CPR0_PLLC 0x0040 -#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) -#define CPR0_PLLD 0x0060 -#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) -#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) -#define CPR0_CPUD 0x0080 -#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) -#define CPR0_PLB2D 0x00a0 -#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) -#define CPR0_OPBD 0x00c0 -#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) -#define CPR0_PERD 0x00e0 -#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) -#define CPR0_DDR2D 0x0100 -#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) -#define CLK_ICFG 0x0140 - -#endif /* _APM821XX_H_ */ diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 07a3fe0..952783f 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -53,8 +53,7 @@ #define EBC_NUM_BANKS 6 #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define EBC_NUM_BANKS 3 #endif diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index 4d1106b..2ae399f 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -8,8 +8,7 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -26,8 +25,7 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -41,8 +39,6 @@ #if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_SIZE 0x0984 /* OCM size 64k */ -#elif defined(CONFIG_APM821XX) -#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ #endif /* @@ -51,7 +47,7 @@ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 12d6d03..e6fed83 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -276,7 +276,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -349,7 +349,7 @@ /* * Memory controller registers */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -359,9 +359,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX || CONFIG_APM821XX */ +#else /* CONFIG_405EX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX || CONFIG_APM821XX */ +#endif /* CONFIG_405EX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -407,12 +407,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) +#if !defined(CONFIG_405EX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 05b4690..58e65c1 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -15,7 +15,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -236,8 +236,7 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index e6a3bff..b8b0ff9 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -56,10 +56,6 @@ #include #endif -#if defined(CONFIG_APM821XX) -#include -#endif - /* * Common registers for all SoC's */ -- cgit v1.1 From e7a565638a7a727f1a4074c0b39e7de22ff3d6c9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:38:00 +0900 Subject: powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7 These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc83xx/Kconfig | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 6de9265..42e0e29 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -64,12 +64,6 @@ config TARGET_SUVD3 config TARGET_TUXX1 bool "Support tuxx1" -config TARGET_MERGERBOX - bool "Support MERGERBOX" - -config TARGET_MVBLM7 - bool "Support MVBLM7" - config TARGET_TQM834X bool "Support TQM834x" @@ -89,8 +83,6 @@ source "board/freescale/mpc837xemds/Kconfig" source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/km83xx/Kconfig" -source "board/matrix_vision/mergerbox/Kconfig" -source "board/matrix_vision/mvblm7/Kconfig" source "board/mpc8308_p1m/Kconfig" source "board/sbc8349/Kconfig" source "board/tqc/tqm834x/Kconfig" -- cgit v1.1 From af55e35d33894295cf0f2f94c050f67d05b50944 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:38:01 +0900 Subject: powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc5xxx/Kconfig | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index cca58e5..8a477e7 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -97,12 +97,6 @@ config TARGET_MUCMC52 config TARGET_UC101 bool "Support uc101" -config TARGET_MVBC_P - bool "Support MVBC_P" - -config TARGET_MVSMR - bool "Support MVSMR" - config TARGET_PCM030 bool "Support pcm030" @@ -139,8 +133,6 @@ source "board/jupiter/Kconfig" source "board/manroland/hmi1001/Kconfig" source "board/manroland/mucmc52/Kconfig" source "board/manroland/uc101/Kconfig" -source "board/matrix_vision/mvbc_p/Kconfig" -source "board/matrix_vision/mvsmr/Kconfig" source "board/mcc200/Kconfig" source "board/motionpro/Kconfig" source "board/munices/Kconfig" -- cgit v1.1