From 13194f3b5f51d104bdfdd7ff5a7556136b6dc35c Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Sat, 14 Sep 2013 14:02:46 +0530 Subject: USB: XHCI: Add xHCI host controller support for Exynos5 This adds driver layer for xHCI controller in Samsung's exynos5 soc. This interacts with xHCI host controller stack. Signed-off-by: Vikas C Sajjan Signed-off-by: Vivek Gautam Cc: Julius Werner Cc: Simon Glass Cc: Minkyu Kang Cc: Dan Murphy Cc: Marek Vasut --- arch/arm/include/asm/arch-exynos/cpu.h | 8 +++ arch/arm/include/asm/arch-exynos/xhci-exynos.h | 88 ++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 arch/arm/include/asm/arch-exynos/xhci-exynos.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 4b67191..b4ef03e 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -51,6 +51,8 @@ #define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE /* EXYNOS4X12 */ #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 @@ -87,6 +89,8 @@ #define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE /* EXYNOS5 Common*/ #define EXYNOS5_I2C_SPACING 0x10000 @@ -106,6 +110,8 @@ #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 +#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000 +#define EXYNOS5_USB3PHY_BASE 0x12100000 #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 #define EXYNOS5_USBPHY_BASE 0x12130000 #define EXYNOS5_USBOTG_BASE 0x12140000 @@ -220,7 +226,9 @@ SAMSUNG_BASE(swreset, SWRESET) SAMSUNG_BASE(timer, PWMTIMER_BASE) SAMSUNG_BASE(uart, UART_BASE) SAMSUNG_BASE(usb_phy, USBPHY_BASE) +SAMSUNG_BASE(usb3_phy, USB3PHY_BASE) SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE) +SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE) SAMSUNG_BASE(usb_otg, USBOTG_BASE) SAMSUNG_BASE(watchdog, WATCHDOG_BASE) SAMSUNG_BASE(power, POWER_BASE) diff --git a/arch/arm/include/asm/arch-exynos/xhci-exynos.h b/arch/arm/include/asm/arch-exynos/xhci-exynos.h new file mode 100644 index 0000000..92b90a4 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/xhci-exynos.h @@ -0,0 +1,88 @@ +/* Copyright (c) 2012 Samsung Electronics Co. Ltd + * + * Exynos Phy register definitions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_XHCI_EXYNOS_H_ +#define _ASM_ARCH_XHCI_EXYNOS_H_ + +/* Phy register MACRO definitions */ + +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) + +#define PHYUTMI_OTGDISABLE (1 << 6) +#define PHYUTMI_FORCESUSPEND (1 << 1) +#define PHYUTMI_FORCESLEEP (1 << 0) + +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) +#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) + +#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) +#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) + +#define PHYCLKRST_SSC_EN (0x1 << 20) +#define PHYCLKRST_REF_SSP_EN (0x1 << 19) +#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) + +#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) + +#define PHYCLKRST_FSEL_MASK (0x3f << 5) +#define PHYCLKRST_FSEL(_x) ((_x) << 5) +#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) +#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) +#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) +#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) + +#define PHYCLKRST_RETENABLEN (0x1 << 4) + +#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) + +#define PHYCLKRST_PORTRESET (0x1 << 1) +#define PHYCLKRST_COMMONONN (0x1 << 0) + +#define PHYPARAM0_REF_USE_PAD (0x1 << 31) +#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) +#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) + +#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) +#define PHYPARAM1_PCS_TXDEEMPH (0x1c) + +#define PHYTEST_POWERDOWN_SSP (0x1 << 3) +#define PHYTEST_POWERDOWN_HSP (0x1 << 2) + +#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) + +#define FSEL_CLKSEL_24M (0x5) + +/* XHCI PHY register structure */ +struct exynos_usb3_phy { + unsigned int reserve1; + unsigned int link_system; + unsigned int phy_utmi; + unsigned int phy_pipe; + unsigned int phy_clk_rst; + unsigned int phy_reg0; + unsigned int phy_reg1; + unsigned int phy_param0; + unsigned int phy_param1; + unsigned int phy_term; + unsigned int phy_test; + unsigned int phy_adp; + unsigned int phy_batchg; + unsigned int phy_resume; + unsigned int reserve2[3]; + unsigned int link_port; +}; + +#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */ -- cgit v1.1 From 80c4c5964fe35872d601d5d77e86f14b183f5bb9 Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Sat, 14 Sep 2013 14:02:47 +0530 Subject: arm: exynos: Add methods to control power to USB 3.0 PHY Adding methods to turn on/off power to USB3.0 type PHY as and when required by the controller. Signed-off-by: Vivek Gautam Cc: Julius Werner Cc: Simon Glass Cc: Minkyu Kang Cc: Dan Murphy Cc: Marek Vasut --- arch/arm/cpu/armv7/exynos/power.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 5 +++++ 2 files changed, 27 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index 517e804..563abd7 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -59,6 +59,28 @@ void set_usbhost_phy_ctrl(unsigned int enable) exynos5_set_usbhost_phy_ctrl(enable); } +static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBDRD_PHY */ + setbits_le32(&power->usbdrd_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + } else { + /* Disabling USBDRD_PHY */ + clrbits_le32(&power->usbdrd_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + } +} + +void set_usbdrd_phy_ctrl(unsigned int enable) +{ + if (cpu_is_exynos5()) + exynos5_set_usbdrd_phy_ctrl(enable); +} + static void exynos5_dp_phy_control(unsigned int enable) { unsigned int cfg; diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 3241327..8db18c5 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -847,6 +847,11 @@ void set_hw_thermal_trip(void); #define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) #define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) +void set_usbdrd_phy_ctrl(unsigned int enable); + +#define POWER_USB_DRD_PHY_CTRL_EN (1 << 0) +#define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0) + void set_dp_phy_ctrl(unsigned int enable); #define EXYNOS_DP_PHY_ENABLE (1 << 0) -- cgit v1.1 From 28cfef5f41b8d35a447ac99e747622e5d47ae04c Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Sat, 14 Sep 2013 14:02:49 +0530 Subject: exynos5: dts: Add device node for XHCI Adding device node for xhci host controller to enable usb 3.0 on exynos5250. Signed-off-by: Vivek Gautam Cc: Julius Werner Cc: Simon Glass Cc: Minkyu Kang Cc: Dan Murphy Cc: Marek Vasut --- arch/arm/dts/exynos5250.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index 44cbb5a..31880eb 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -158,6 +158,18 @@ interrupts = <0 130 0>; }; + xhci@12000000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12000000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12100000 0x100>; + }; + }; + ehci@12110000 { compatible = "samsung,exynos-ehci"; reg = <0x12110000 0x100>; -- cgit v1.1 From d861a333da84dd7ab70e975171159c37f7d06939 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Mon, 26 Aug 2013 08:54:50 -0500 Subject: ARM: OMAP5: Add registers and defines for USBOTG SS Add the prcm registers and the bit definitions to enable the USB SS port of the OMAP5 device. Signed-off-by: Dan Murphy --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 ++-- arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++++ arch/arm/include/asm/arch-omap5/clock.h | 10 ++++++++++ arch/arm/include/asm/omap_common.h | 4 ++++ 4 files changed, 20 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index ab0c568..bb77b5c 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -339,7 +339,7 @@ void configure_mpu_dpll(void) debug("MPU DPLL locked\n"); } -#ifdef CONFIG_USB_EHCI_OMAP +#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) static void setup_usb_dpll(void) { const struct dpll_params *params; @@ -404,7 +404,7 @@ static void setup_dplls(void) /* MPU dpll */ configure_mpu_dpll(); -#ifdef CONFIG_USB_EHCI_OMAP +#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) setup_usb_dpll(); #endif params = get_ddr_dpll_params(*dplls_data); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 764620d..e6686fd 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -295,6 +295,7 @@ struct prcm_regs const omap5_es1_prcm = { struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, + .control_phy_power_usb = 0x4A002370, .control_padconf_core_base = 0x4A002800, .control_paconf_global = 0x4A002DA0, .control_paconf_mode = 0x4A002DA4, @@ -567,6 +568,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_div_m2_dpll_unipro = 0x4a0081d0, .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640, .cm_coreaon_bandgap_clkctrl = 0x4a008648, .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, @@ -698,6 +700,8 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_p1500_clkctrl = 0x4a009678, .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, + .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0, /* prm irqstatus regs */ .prm_irqstatus_mpu_2 = 0x4ae06014, diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 9a2166c..5cbbc44 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -166,6 +166,16 @@ #define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9) #define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10) +/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) + +/* CM_L3INIT_USB_OTG_SS_CLKCTRL */ +#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) +#define OPTFCLKEN_REFCLK960M (1 << 8) + +/* CM_L3INIT_OCP2SCP1_CLKCTRL */ +#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) + /* CM_MPU_MPU_CLKCTRL */ #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 3a998cc..bea1835 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -143,6 +143,7 @@ struct prcm_regs { u32 cm_div_m2_dpll_unipro; u32 cm_ssc_deltamstep_dpll_unipro; u32 cm_ssc_modfreqdiv_dpll_unipro; + u32 cm_coreaon_usb_phy_core_clkctrl; /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; @@ -226,6 +227,8 @@ struct prcm_regs { u32 cm_l3init_p1500_clkctrl; u32 cm_l3init_fsusb_clkctrl; u32 cm_l3init_ocp2scp1_clkctrl; + u32 cm_l3init_ocp2scp3_clkctrl; + u32 cm_l3init_usb_otg_ss_clkctrl; u32 prm_irqstatus_mpu_2; @@ -348,6 +351,7 @@ struct omap_sys_ctrl_regs { u32 control_core_mac_id_1_lo; u32 control_core_mac_id_1_hi; u32 control_std_fuse_opp_vdd_mpu_2; + u32 control_phy_power_usb; u32 control_core_mmr_lock1; u32 control_core_mmr_lock2; u32 control_core_mmr_lock3; -- cgit v1.1 From 2d2358ac157e6cc039cfbbbdffbf617526c099c6 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Mon, 26 Aug 2013 08:54:52 -0500 Subject: OMAP5: USB: Add OMAP xHCI file and header Add the OMAP file for the xHCI Host controller This code will initilialize the proper components within the OMAP5 to enable the xHCI host controller. Signed-off-by: Dan Murphy --- arch/arm/include/asm/arch-omap5/xhci-omap.h | 124 ++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 arch/arm/include/asm/arch-omap5/xhci-omap.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap5/xhci-omap.h b/arch/arm/include/asm/arch-omap5/xhci-omap.h new file mode 100644 index 0000000..b557a43 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/xhci-omap.h @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Inc, + * + * Author: Dan Murphy + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_XHCI_OMAP_H_ +#define _ASM_ARCH_XHCI_OMAP_H_ + +#define OMAP_XHCI_BASE 0x4a030000 +#define OMAP_OCP1_SCP_BASE 0x4a084c00 +#define OMAP_OTG_WRAPPER_BASE 0x4A020000 + +/* Phy register MACRO definitions */ +#define PLL_REGM_MASK 0x001FFE00 +#define PLL_REGM_SHIFT 0x9 +#define PLL_REGM_F_MASK 0x0003FFFF +#define PLL_REGM_F_SHIFT 0x0 +#define PLL_REGN_MASK 0x000001FE +#define PLL_REGN_SHIFT 0x1 +#define PLL_SELFREQDCO_MASK 0x0000000E +#define PLL_SELFREQDCO_SHIFT 0x1 +#define PLL_SD_MASK 0x0003FC00 +#define PLL_SD_SHIFT 0x9 +#define SET_PLL_GO 0x1 +#define PLL_TICOPWDN 0x10000 +#define PLL_LOCK 0x2 +#define PLL_IDLE 0x1 + +#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 +#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC +#define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) +#define USB3_PHY_RX_POWERON (1 << 14) +#define USB3_PHY_TX_POWERON (1 << 15) +#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) +#define USB3_PWRCTL_CLK_CMD_SHIFT 14 +#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 + +/* USBOTGSS_WRAPPER definitions */ +#define USBOTGSS_WRAPRESET (1 << 17) +#define USBOTGSS_DMADISABLE (1 << 16) +#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) +#define USBOTGSS_STANDBYMODE_SMRT (1 << 5) +#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) +#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) +#define USBOTGSS_IDLEMODE_SMRT (1 << 3) +#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) + +/* USBOTGSS_IRQENABLE_SET_0 bit */ +#define USBOTGSS_COREIRQ_EN (1 << 0) + +/* USBOTGSS_IRQENABLE_SET_1 bits */ +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) +#define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) + +/* + * USBOTGSS_WRAPPER registers + */ +struct omap_dwc_wrapper { + u32 revision; + + u32 reserve_1[3]; + + u32 sysconfig; /* offset of 0x10 */ + + u32 reserve_2[3]; + u16 reserve_3; + + u32 irqstatus_raw_0; /* offset of 0x24 */ + u32 irqstatus_0; + u32 irqenable_set_0; + u32 irqenable_clr_0; + + u32 irqstatus_raw_1; /* offset of 0x34 */ + u32 irqstatus_1; + u32 irqenable_set_1; + u32 irqenable_clr_1; + + u32 reserve_4[15]; + + u32 utmi_otg_ctrl; /* offset of 0x80 */ + u32 utmi_otg_status; + + u32 reserve_5[30]; + + u32 mram_offset; /* offset of 0x100 */ + u32 fladj; + u32 dbg_config; + u32 dbg_data; + u32 dev_ebc_en; +}; + +/* XHCI PHY register structure */ +struct omap_usb3_phy { + u32 reserve1; + u32 pll_status; + u32 pll_go; + u32 pll_config_1; + u32 pll_config_2; + u32 pll_config_3; + u32 pll_ssc_config_1; + u32 pll_ssc_config_2; + u32 pll_config_4; +}; + +struct omap_xhci { + struct omap_dwc_wrapper *otg_wrapper; + struct omap_usb3_phy *usb3_phy; + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +#endif /* _ASM_ARCH_XHCI_OMAP_H_ */ -- cgit v1.1 From 7132869d4c9e03180226146b27c8c4266ceab351 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Wed, 25 Sep 2013 18:41:16 -0700 Subject: mx6: iomux: add GPR1 defines for use with nitrogen6x Select GPIO1 as the USB OTG ID pin for Nitrogen6x Signed-off-by: Troy Kisky --- arch/arm/include/asm/arch-mx6/iomux.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index ff13a1e..fe4675e 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -10,6 +10,12 @@ #define MX6_IOMUXC_GPR7 0x020e001c /* + * IOMUXC_GPR1 bit fields + */ +#define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) +#define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) +#define IOMUXC_GPR1_OTG_ID_MASK (1<<13) +/* * IOMUXC_GPR13 bit fields */ #define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30) -- cgit v1.1 From 16297cfb2a20c9d89834cd9e31edac5184a777a1 Mon Sep 17 00:00:00 2001 From: Mateusz Zalega Date: Fri, 4 Oct 2013 19:22:26 +0200 Subject: usb: new board-specific USB init interface This commit unifies board-specific USB initialization implementations under one symbol (usb_board_init), declaration of which is available in usb.h. New API allows selective initialization of USB controllers whenever needed. Signed-off-by: Mateusz Zalega Signed-off-by: Kyungmin Park Reviewed-by: Lukasz Majewski Cc: Marek Vasut Cc: Lukasz Majewski --- arch/arm/include/asm/arch-tegra/usb.h | 3 +-- arch/arm/include/asm/ehci-omap.h | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index f66257c..a1efd07 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -131,8 +131,7 @@ /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ #define VBUS_VLD_STS (1 << 26) - /* Setup USB on the board */ -int board_usb_init(const void *blob); +int usb_process_devicetree(const void *blob); #endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index ac83a53..c7bca05 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -145,8 +145,8 @@ struct omap_ehci { struct ehci_hccr; struct ehci_hcor; -int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, - struct ehci_hccr **hccr, struct ehci_hcor **hcor); +int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata, + struct ehci_hccr **hccr, struct ehci_hcor **hcor); int omap_ehci_hcd_stop(void); #endif /* _OMAP_COMMON_EHCI_H_ */ -- cgit v1.1 From 41b667b834aaf550faabbf1d222a456cb4fc97ec Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Fri, 11 Oct 2013 12:28:14 -0500 Subject: usb: omap: Move the xhci-omap header file to common location Moving the xhci-omap header to a more global location so that other code can reference this code. Signed-off-by: Dan Murphy --- arch/arm/include/asm/arch-omap5/xhci-omap.h | 124 ---------------------------- 1 file changed, 124 deletions(-) delete mode 100644 arch/arm/include/asm/arch-omap5/xhci-omap.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap5/xhci-omap.h b/arch/arm/include/asm/arch-omap5/xhci-omap.h deleted file mode 100644 index b557a43..0000000 --- a/arch/arm/include/asm/arch-omap5/xhci-omap.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2013 - * Texas Instruments Inc, - * - * Author: Dan Murphy - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_XHCI_OMAP_H_ -#define _ASM_ARCH_XHCI_OMAP_H_ - -#define OMAP_XHCI_BASE 0x4a030000 -#define OMAP_OCP1_SCP_BASE 0x4a084c00 -#define OMAP_OTG_WRAPPER_BASE 0x4A020000 - -/* Phy register MACRO definitions */ -#define PLL_REGM_MASK 0x001FFE00 -#define PLL_REGM_SHIFT 0x9 -#define PLL_REGM_F_MASK 0x0003FFFF -#define PLL_REGM_F_SHIFT 0x0 -#define PLL_REGN_MASK 0x000001FE -#define PLL_REGN_SHIFT 0x1 -#define PLL_SELFREQDCO_MASK 0x0000000E -#define PLL_SELFREQDCO_SHIFT 0x1 -#define PLL_SD_MASK 0x0003FC00 -#define PLL_SD_SHIFT 0x9 -#define SET_PLL_GO 0x1 -#define PLL_TICOPWDN 0x10000 -#define PLL_LOCK 0x2 -#define PLL_IDLE 0x1 - -#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 -#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC -#define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) -#define USB3_PHY_RX_POWERON (1 << 14) -#define USB3_PHY_TX_POWERON (1 << 15) -#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) -#define USB3_PWRCTL_CLK_CMD_SHIFT 14 -#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 - -/* USBOTGSS_WRAPPER definitions */ -#define USBOTGSS_WRAPRESET (1 << 17) -#define USBOTGSS_DMADISABLE (1 << 16) -#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) -#define USBOTGSS_STANDBYMODE_SMRT (1 << 5) -#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) -#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) -#define USBOTGSS_IDLEMODE_SMRT (1 << 3) -#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) - -/* USBOTGSS_IRQENABLE_SET_0 bit */ -#define USBOTGSS_COREIRQ_EN (1 << 0) - -/* USBOTGSS_IRQENABLE_SET_1 bits */ -#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) -#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) -#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) -#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) -#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) -#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) -#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) -#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) -#define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) -#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) - -/* - * USBOTGSS_WRAPPER registers - */ -struct omap_dwc_wrapper { - u32 revision; - - u32 reserve_1[3]; - - u32 sysconfig; /* offset of 0x10 */ - - u32 reserve_2[3]; - u16 reserve_3; - - u32 irqstatus_raw_0; /* offset of 0x24 */ - u32 irqstatus_0; - u32 irqenable_set_0; - u32 irqenable_clr_0; - - u32 irqstatus_raw_1; /* offset of 0x34 */ - u32 irqstatus_1; - u32 irqenable_set_1; - u32 irqenable_clr_1; - - u32 reserve_4[15]; - - u32 utmi_otg_ctrl; /* offset of 0x80 */ - u32 utmi_otg_status; - - u32 reserve_5[30]; - - u32 mram_offset; /* offset of 0x100 */ - u32 fladj; - u32 dbg_config; - u32 dbg_data; - u32 dev_ebc_en; -}; - -/* XHCI PHY register structure */ -struct omap_usb3_phy { - u32 reserve1; - u32 pll_status; - u32 pll_go; - u32 pll_config_1; - u32 pll_config_2; - u32 pll_config_3; - u32 pll_ssc_config_1; - u32 pll_ssc_config_2; - u32 pll_config_4; -}; - -struct omap_xhci { - struct omap_dwc_wrapper *otg_wrapper; - struct omap_usb3_phy *usb3_phy; - struct xhci_hccr *hcd; - struct dwc3 *dwc3_reg; -}; - -#endif /* _ASM_ARCH_XHCI_OMAP_H_ */ -- cgit v1.1 From 834e91af432479e3808e9cbd1d38199f724fc5aa Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Fri, 11 Oct 2013 12:28:17 -0500 Subject: usb: dra7xx: Add support for dra7xx xhci USB host Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy --- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/include/asm/arch-omap5/clock.h | 4 ++++ arch/arm/include/asm/omap_common.h | 1 + 3 files changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index e6686fd..304ac1c 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -793,6 +793,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, .cm_clkmode_dpll_gmac = 0x4a0052a8, + .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, /* cm1.mpu */ .cm_mpu_mpu_clkctrl = 0x4a005320, diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 5cbbc44..8869b50 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -202,6 +202,10 @@ /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 +/* CTRL_CORE_SRCOMP_NORTH_SIDE */ +#define USB2PHY_DISCHGDET (1 << 29) +#define USB2PHY_AUTORESUME_EN (1 << 30) + /* SMPS */ #define SMPS_I2C_SLAVE_ADDR 0x12 #define SMPS_REG_ADDR_12_MPU 0x23 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index bea1835..8a395e8 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -144,6 +144,7 @@ struct prcm_regs { u32 cm_ssc_deltamstep_dpll_unipro; u32 cm_ssc_modfreqdiv_dpll_unipro; u32 cm_coreaon_usb_phy_core_clkctrl; + u32 cm_coreaon_usb_phy2_core_clkctrl; /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; -- cgit v1.1 From 3d799c7f5e0dd2bea3f4ec839ad7692f7122d992 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Fri, 11 Oct 2013 12:28:18 -0500 Subject: usb: am437x: Add support for am437x xhci USB host Add the support for the am437x xhci usb host. The xHCI host on AM437 is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy --- arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 303c594..3b665e6 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -51,4 +51,14 @@ /* RTC base address */ #define RTC_BASE 0x44E3E000 +/* USB Clock Control */ +#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) +#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) +#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 2) +#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) + +#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) +#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) +#define USBPHYOCPSCP_MODULE_EN (1 << 2) + #endif /* __AM43XX_HARDWARE_AM43XX_H */ -- cgit v1.1 From 06d513ecb61a6711157707ebe10b968aacc0f2a8 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Thu, 10 Oct 2013 15:27:56 -0700 Subject: usb: add enum usb_init_type parameter to usb_lowlevel_init This parameter will later be used to verify OTG ports. Signed-off-by: Troy Kisky --- arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c | 2 +- arch/powerpc/cpu/mpc5xxx/usb_ohci.c | 2 +- arch/powerpc/cpu/ppc4xx/usb_ohci.c | 2 +- arch/sparc/cpu/leon3/usb_uhci.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c index 931f95a..fd0ec65 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c @@ -1548,7 +1548,7 @@ static void hc_release_ohci (ohci_t *ohci) */ static char ohci_inited = 0; -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { u32 pin_func; u32 sys_freqctrl, sys_clksrc; diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c index 3d345ff..a68f9d6 100644 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c +++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c @@ -1544,7 +1544,7 @@ static void hc_release_ohci (ohci_t *ohci) */ static char ohci_inited = 0; -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { /* Set the USB Clock */ diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c index b371a75..fafc15e 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c @@ -1549,7 +1549,7 @@ static void hc_release_ohci (ohci_t *ohci) */ static char ohci_inited = 0; -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { memset (&gohci, 0, sizeof (ohci_t)); memset (&urb_priv, 0, sizeof (urb_priv_t)); diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c index 5de48c1..c411ded 100644 --- a/arch/sparc/cpu/leon3/usb_uhci.c +++ b/arch/sparc/cpu/leon3/usb_uhci.c @@ -688,7 +688,7 @@ void handle_usb_interrupt(void) /* init uhci */ -int usb_lowlevel_init(int index, void **controller) +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { unsigned char temp; ambapp_ahbdev ahbdev; -- cgit v1.1