From 234370cab4b2f096e095fe8f3284fd39740a4023 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Fri, 22 Mar 2013 02:26:36 +0000 Subject: Exynos5: clock: Update the equation to calculate PLL output frequency According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/clock.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 223660a..1203ada 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -116,10 +116,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ fout = (m + k / 1024) * (freq / (p * (1 << s))); } else { - if (s < 1) - s = 1; - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ - fout = m * (freq / (p * (1 << (s - 1)))); + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ + fout = m * (freq / (p * (1 << s))); } return fout; -- cgit v1.1 From 72af2fc8504daccd2f8ae2459e3e225e9c2cc512 Mon Sep 17 00:00:00 2001 From: Inderpal Singh Date: Thu, 4 Apr 2013 23:09:19 +0000 Subject: exynos: move tzpc_init to armv7/exynos tzpc_init is common for all exynos5 boards, hence move it to armv7/exynos so that all other boards can use it. Also update the smdk5250 Makefile and config file. Signed-off-by: Inderpal Singh Acked-by: Chander Kashyap Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/Makefile | 2 +- arch/arm/cpu/armv7/exynos/tzpc.c | 48 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/tzpc.h | 28 +++++++++++++++++++ 3 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/exynos/tzpc.c (limited to 'arch') diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile index 9119961..b2f9152 100644 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ b/arch/arm/cpu/armv7/exynos/Makefile @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS += clock.o power.o soc.o system.o pinmux.o +COBJS += clock.o power.o soc.o system.o pinmux.o tzpc.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/exynos/tzpc.c b/arch/arm/cpu/armv7/exynos/tzpc.c new file mode 100644 index 0000000..81adb4b --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/tzpc.c @@ -0,0 +1,48 @@ +/* + * Lowlevel setup for SMDK5250 board based on S5PC520 + * + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Setting TZPC[TrustZone Protection Controller] */ +void tzpc_init(void) +{ + struct exynos_tzpc *tzpc; + unsigned int addr; + + for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { + tzpc = (struct exynos_tzpc *)addr; + + if (addr == TZPC0_BASE) + writel(R0SIZE, &tzpc->r0size); + + writel(DECPROTXSET, &tzpc->decprot0set); + writel(DECPROTXSET, &tzpc->decprot1set); + + if (addr != TZPC9_BASE) { + writel(DECPROTXSET, &tzpc->decprot2set); + writel(DECPROTXSET, &tzpc->decprot3set); + } + } +} diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h index c5eb4b1..050ad70 100644 --- a/arch/arm/include/asm/arch-exynos/tzpc.h +++ b/arch/arm/include/asm/arch-exynos/tzpc.h @@ -47,6 +47,34 @@ struct exynos_tzpc { unsigned int pcellid2; unsigned int pcellid3; }; + +/* TZPC : Register Offsets */ +#define TZPC0_BASE 0x10100000 +#define TZPC1_BASE 0x10110000 +#define TZPC2_BASE 0x10120000 +#define TZPC3_BASE 0x10130000 +#define TZPC4_BASE 0x10140000 +#define TZPC5_BASE 0x10150000 +#define TZPC6_BASE 0x10160000 +#define TZPC7_BASE 0x10170000 +#define TZPC8_BASE 0x10180000 +#define TZPC9_BASE 0x10190000 + +#define TZPC_BASE_OFFSET 0x10000 + +/* + * TZPC Register Value : + * R0SIZE: 0x0 : Size of secured ram + */ +#define R0SIZE 0x0 + +/* + * TZPC Decode Protection Register Value : + * DECPROTXSET: 0xFF : Set Decode region to non-secure + */ +#define DECPROTXSET 0xFF +void tzpc_init(void); + #endif #endif -- cgit v1.1 From b5f9756f7f2449cf1b6c3e64dbc40f159f7dcbe2 Mon Sep 17 00:00:00 2001 From: Inderpal Singh Date: Thu, 4 Apr 2013 23:09:20 +0000 Subject: exynos: update tzpc to make it common for exynos4 and exynos5 This requires that cpu_is_exynos4/5 should be made available before tzpc_init. Hence this patch also makes necessary changes to have cpu_info in spl and invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250. Signed-off-by: Inderpal Singh Acked-by: Chander Kashyap Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/tzpc.c | 23 ++++++++++++++++------- arch/arm/cpu/armv7/s5p-common/Makefile | 2 ++ arch/arm/include/asm/arch-exynos/cpu.h | 4 ++++ arch/arm/include/asm/arch-exynos/tzpc.h | 14 +++----------- 4 files changed, 25 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/exynos/tzpc.c b/arch/arm/cpu/armv7/exynos/tzpc.c index 81adb4b..f5e8e9c 100644 --- a/arch/arm/cpu/armv7/exynos/tzpc.c +++ b/arch/arm/cpu/armv7/exynos/tzpc.c @@ -22,6 +22,7 @@ * MA 02111-1307 USA */ +#include #include #include @@ -29,20 +30,28 @@ void tzpc_init(void) { struct exynos_tzpc *tzpc; - unsigned int addr; + unsigned int addr, start = 0, end = 0; - for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { + start = samsung_get_base_tzpc(); + + if (cpu_is_exynos5()) + end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET); + else if (cpu_is_exynos4()) + end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET); + + for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) { tzpc = (struct exynos_tzpc *)addr; - if (addr == TZPC0_BASE) + if (addr == start) writel(R0SIZE, &tzpc->r0size); writel(DECPROTXSET, &tzpc->decprot0set); writel(DECPROTXSET, &tzpc->decprot1set); - if (addr != TZPC9_BASE) { - writel(DECPROTXSET, &tzpc->decprot2set); - writel(DECPROTXSET, &tzpc->decprot3set); - } + if (cpu_is_exynos5() && (addr == end)) + break; + + writel(DECPROTXSET, &tzpc->decprot2set); + writel(DECPROTXSET, &tzpc->decprot3set); } } diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index 1705399..0c38bd0 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -26,9 +26,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)libs5p-common.o COBJS-y += cpu_info.o +ifndef CONFIG_SPL_BUILD COBJS-y += timer.o COBJS-y += sromc.o COBJS-$(CONFIG_PWM) += pwm.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index f76e489..36b98c8 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -38,6 +38,7 @@ #define EXYNOS4_CLOCK_BASE 0x10030000 #define EXYNOS4_SYSTIMER_BASE 0x10050000 #define EXYNOS4_WATCHDOG_BASE 0x10060000 +#define EXYNOS4_TZPC_BASE 0x10110000 #define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_DMC0_BASE 0x10400000 #define EXYNOS4_DMC1_BASE 0x10410000 @@ -74,6 +75,7 @@ #define EXYNOS4X12_CLOCK_BASE 0x10030000 #define EXYNOS4X12_SYSTIMER_BASE 0x10050000 #define EXYNOS4X12_WATCHDOG_BASE 0x10060000 +#define EXYNOS4X12_TZPC_BASE 0x10110000 #define EXYNOS4X12_DMC0_BASE 0x10600000 #define EXYNOS4X12_DMC1_BASE 0x10610000 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 @@ -107,6 +109,7 @@ #define EXYNOS5_POWER_BASE 0x10040000 #define EXYNOS5_SWRESET 0x10040400 #define EXYNOS5_SYSREG_BASE 0x10050000 +#define EXYNOS5_TZPC_BASE 0x10100000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 #define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 @@ -233,6 +236,7 @@ SAMSUNG_BASE(watchdog, WATCHDOG_BASE) SAMSUNG_BASE(power, POWER_BASE) SAMSUNG_BASE(spi, SPI_BASE) SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) +SAMSUNG_BASE(tzpc, TZPC_BASE) #endif #endif /* _EXYNOS4_CPU_H */ diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h index 050ad70..4d9c3a3 100644 --- a/arch/arm/include/asm/arch-exynos/tzpc.h +++ b/arch/arm/include/asm/arch-exynos/tzpc.h @@ -48,18 +48,10 @@ struct exynos_tzpc { unsigned int pcellid3; }; -/* TZPC : Register Offsets */ -#define TZPC0_BASE 0x10100000 -#define TZPC1_BASE 0x10110000 -#define TZPC2_BASE 0x10120000 -#define TZPC3_BASE 0x10130000 -#define TZPC4_BASE 0x10140000 -#define TZPC5_BASE 0x10150000 -#define TZPC6_BASE 0x10160000 -#define TZPC7_BASE 0x10170000 -#define TZPC8_BASE 0x10180000 -#define TZPC9_BASE 0x10190000 +#define EXYNOS4_NR_TZPC_BANKS 6 +#define EXYNOS5_NR_TZPC_BANKS 10 +/* TZPC : Register Offsets */ #define TZPC_BASE_OFFSET 0x10000 /* -- cgit v1.1 From 07eb5f9ce70cbed40d0bb2799430a0978e054ef2 Mon Sep 17 00:00:00 2001 From: Amar Date: Sat, 27 Apr 2013 11:42:53 +0530 Subject: EXYNOS5: FDT: Add DWMMC device node data This patch adds DWMMC device node data for exynos5. This patch also adds binding file for DWMMC device node. Signed-off-by: Vivek Gautam Signed-off-by: Amar Acked-by: Jaehoon Chung Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5250.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index df4b231..cee4fe8 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -169,4 +169,37 @@ #address-cells = <1>; #size-cells = <1>; }; + + mmc@12200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12200000 0x1000>; + interrupts = <0 75 0>; + }; + + mmc@12210000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12210000 0x1000>; + interrupts = <0 76 0>; + }; + + mmc@12220000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12220000 0x1000>; + interrupts = <0 77 0>; + }; + + mmc@12230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12230000 0x1000>; + interrupts = <0 78 0>; + }; + }; -- cgit v1.1 From a082a2dde06142bb599551ed3dad324923a130e0 Mon Sep 17 00:00:00 2001 From: Amar Date: Sat, 27 Apr 2013 11:42:55 +0530 Subject: EXYNOS5: DWMMC: Added FDT support for DWMMC This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node. Signed-off-by: Vivek Gautam Signed-off-by: Amar Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/include/asm/arch-exynos/dwmmc.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 8acdf9b..3b147b8 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,7 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) -int exynos_dwmci_init(u32 regbase, int bus_width, int index); - -static inline unsigned int exynos_dwmmc_init(int index, int bus_width) -{ - unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return exynos_dwmci_init(base, bus_width, index); -} +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel); -- cgit v1.1 From 2b81c26b7c43f01cfaa5c4c50571b6854eece656 Mon Sep 17 00:00:00 2001 From: Amar Date: Sat, 27 Apr 2013 11:42:56 +0530 Subject: EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results. This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk(). Signed-off-by: Amar Acked-by: Simon Glass Acked-by: Jaehoon Chung Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 1203ada..e1c4246 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -611,7 +611,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -660,7 +660,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) (struct exynos5_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; -- cgit v1.1 From 1149ca005a548aff8e65d44634d31db965ed66bd Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Fri, 5 Apr 2013 15:21:38 -0700 Subject: power: exynos-tmu: fix warnings and clean up code This patch does the folowing 1. change the data types for unsigned int variable to unsigned 2. change the tmu_base type to struct exynos5_tmu_reg * 3. Add timer functionality for get_cur_temp() 4. error handling in the get_tmu_fdt_values() 5. Add check for curr_temp reading 6. some cosmotic changes. Signed-off-by: Naveen Krishna Chatradhi Reviewed-by: Vadim Bendebury Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/include/asm/arch-exynos/tmu.h | 58 +++++++++++++++------------------- 1 file changed, 25 insertions(+), 33 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-exynos/tmu.h b/arch/arm/include/asm/arch-exynos/tmu.h index 7e0158e..cad3569 100644 --- a/arch/arm/include/asm/arch-exynos/tmu.h +++ b/arch/arm/include/asm/arch-exynos/tmu.h @@ -21,38 +21,30 @@ #define __ASM_ARCH_TMU_H struct exynos5_tmu_reg { - unsigned triminfo; - unsigned rsvd1; - unsigned rsvd2; - unsigned rsvd3; - unsigned rsvd4; - unsigned triminfo_control; - unsigned rsvd5; - unsigned rsvd6; - unsigned tmu_control; - unsigned rsvd7; - unsigned tmu_status; - unsigned sampling_internal; - unsigned counter_value0; - unsigned counter_value1; - unsigned rsvd8; - unsigned rsvd9; - unsigned current_temp; - unsigned rsvd10; - unsigned rsvd11; - unsigned rsvd12; - unsigned threshold_temp_rise; - unsigned threshold_temp_fall; - unsigned rsvd13; - unsigned rsvd14; - unsigned past_temp3_0; - unsigned past_temp7_4; - unsigned past_temp11_8; - unsigned past_temp15_12; - unsigned inten; - unsigned intstat; - unsigned intclear; - unsigned rsvd15; - unsigned emul_con; + u32 triminfo; + u32 rsvd1[4]; + u32 triminfo_control; + u32 rsvd5[2]; + u32 tmu_control; + u32 rsvd7; + u32 tmu_status; + u32 sampling_internal; + u32 counter_value0; + u32 counter_value1; + u32 rsvd8[2]; + u32 current_temp; + u32 rsvd10[3]; + u32 threshold_temp_rise; + u32 threshold_temp_fall; + u32 rsvd13[2]; + u32 past_temp3_0; + u32 past_temp7_4; + u32 past_temp11_8; + u32 past_temp15_12; + u32 inten; + u32 intstat; + u32 intclear; + u32 rsvd15; + u32 emul_con; }; #endif /* __ASM_ARCH_TMU_H */ -- cgit v1.1