From 652a7bbd87d322c49ffe138b98563dc6c8cd2885 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 21 Nov 2016 13:31:34 -0800 Subject: powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/Kconfig | 5 +++++ arch/powerpc/cpu/mpc85xx/Makefile | 4 ++-- arch/powerpc/cpu/mpc85xx/fdt.c | 4 ++-- arch/powerpc/cpu/mpc85xx/speed.c | 2 +- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 2 +- arch/powerpc/include/asm/config_mpc85xx.h | 4 ++-- arch/powerpc/include/asm/immap_85xx.h | 4 ++-- 7 files changed, 15 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 9d4e5ba..991127d 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -262,11 +262,13 @@ config TARGET_T2081QDS config TARGET_T4160QDS bool "Support T4160QDS" + select ARCH_T4160 select SUPPORT_SPL select PHYS_64BIT config TARGET_T4160RDB bool "Support T4160RDB" + select ARCH_T4160 select SUPPORT_SPL select PHYS_64BIT @@ -419,6 +421,9 @@ config ARCH_T2080 config ARCH_T2081 bool +config ARCH_T4160 + bool + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f74018b..cf2aaa1 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -45,7 +45,7 @@ obj-$(CONFIG_ARCH_P4080) += p4080_ids.o obj-$(CONFIG_ARCH_P5020) += p5020_ids.o obj-$(CONFIG_ARCH_P5040) += p5040_ids.o obj-$(CONFIG_PPC_T4240) += t4240_ids.o -obj-$(CONFIG_PPC_T4160) += t4240_ids.o +obj-$(CONFIG_ARCH_T4160) += t4240_ids.o obj-$(CONFIG_PPC_T4080) += t4240_ids.o obj-$(CONFIG_ARCH_B4420) += b4860_ids.o obj-$(CONFIG_ARCH_B4860) += b4860_ids.o @@ -87,7 +87,7 @@ obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o obj-$(CONFIG_PPC_T4240) += t4240_serdes.o -obj-$(CONFIG_PPC_T4160) += t4240_serdes.o +obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o obj-$(CONFIG_PPC_T4080) += t4240_serdes.o obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 6bde60d..9fab8ed 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -512,7 +512,7 @@ static void fdt_fixup_usb(void *fdt) #endif #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) + defined(CONFIG_ARCH_T4160) || defined(CONFIG_PPC_T4080) void fdt_fixup_dma3(void *blob) { /* the 3rd DMA is not functional if SRIO2 is chosen */ @@ -529,7 +529,7 @@ void fdt_fixup_dma3(void *blob) case 0x29: case 0x2d: case 0x2e: -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS4_PRTCL; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 4de5dcf..e4feb3f 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -130,7 +130,7 @@ void get_sys_info(sys_info_t *sys_info) * it uses 6. * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) || defined(CONFIG_ARCH_T2080) || \ defined(CONFIG_ARCH_T2081) svr = get_svr(); diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 7b43b28..4b73e76 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -263,7 +263,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) +#elif defined(CONFIG_ARCH_T4160) || defined(CONFIG_PPC_T4080) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {NONE, NONE, NONE, NONE, diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 65a4777..fc8e011 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -545,7 +545,7 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -568,7 +568,7 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 -#if defined(CONFIG_PPC_T4160) +#if defined(CONFIG_ARCH_T4160) #define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #elif defined(CONFIG_PPC_T4080) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 783db18..19ce7f3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,7 +1759,7 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 @@ -1875,7 +1875,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 -- cgit v1.1