From 5e5925930bf26236563828bcd65577ba6fcb6841 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Fri, 19 Nov 2010 10:04:37 +0100 Subject: AT91: rework at91sam9261.h Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91sam9261.h | 187 +++++++++++++++------------ 1 file changed, 102 insertions(+), 85 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index 7ca0283..f8048d5 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -2,9 +2,15 @@ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] * * Copyright (C) SAN People + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) + * Definitions for the SoCs: + * AT91SAM9261, AT91SAM9G10 + * + * Note that those SoCs are mostly software and pin compatible, + * therefore this file applies to all of them. Differences between + * those SoCs are concentrated at the end of this file. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,106 +22,117 @@ #define AT91SAM9261_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_RTT_BASE 0xfffffd20 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 -#define AT91_GPBR_BASE 0xfffffd50 +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Peripherals */ +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ +/* Reserved: 5 */ +#define ATMEL_ID_USART0 6 /* USART 0 */ +#define ATMEL_ID_USART1 7 /* USART 1 */ +#define ATMEL_ID_USART2 8 /* USART 2 */ +#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ +#define ATMEL_ID_UDP 10 /* USB Device Port */ +#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ +#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ +#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ +#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ +#define ATMEL_ID_UHP 20 /* USB Host port */ +#define ATMEL_ID_LCDC 21 /* LDC Controller */ +/* Reserved: 22-28 */ +#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ -#ifdef CONFIG_AT91_LEGACY +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_TCB0 0xfffa0000 +#define ATMEL_BASE_TC0 0xfffa0000 +#define ATMEL_BASE_TC1 0xfffa0040 +#define ATMEL_BASE_TC2 0xfffa0080 +#define ATMEL_BASE_UDP0 0xfffa4000 +#define ATMEL_BASE_MCI 0xfffa8000 +#define ATMEL_BASE_TWI0 0xfffac000 +#define ATMEL_BASE_USART0 0xfffb0000 +#define ATMEL_BASE_USART1 0xfffb4000 +#define ATMEL_BASE_USART2 0xfffb8000 +#define ATMEL_BASE_SSC0 0xfffbc000 +#define ATMEL_BASE_SSC1 0xfffc0000 +#define ATMEL_BASE_SSC2 0xfffc4000 +#define ATMEL_BASE_SPI0 0xfffc8000 +#define ATMEL_BASE_SPI1 0xfffcc000 +/* Reserved: 0xfffc4000 - 0xffffe9ff */ /* - * User Peripheral physical base addresses. + * System Peripherals physical base addresses. */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 -#define AT91_BASE_SYS 0xffffea00 +#define ATMEL_BASE_SYS 0xffffea00 +#define ATMEL_BASE_SDRAMC 0xffffea00 +#define ATMEL_BASE_SMC 0xffffec00 +#define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWN 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_GPBR 0xfffffd50 /* - * System Peripherals (offset from AT91_BASE_SYS) + * Internal Memory common on all these SoCs */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */ -#define AT91_USART0 AT91SAM9261_BASE_US0 -#define AT91_USART1 AT91SAM9261_BASE_US1 -#define AT91_USART2 AT91SAM9261_BASE_US2 +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ +#define ATMEL_SIZE_ROM SZ_32K /* Internal ROM size (32Kb) */ -#endif /* CONFIG_AT91_LEGACY */ +#define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */ +#define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */ /* - * Internal Memory. + * External memory */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ +#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */ /* - * Cpu Name + * SoC specific defines */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" +#if defined(CONFIG_AT91SAM9261) +# define ATMEL_CPU_NAME "AT91SAM9261" +#elif defined(CONFIG_AT91SAM9G10) +# define ATMEL_CPU_NAME "AT91SAM9G10" +#endif #endif -- cgit v1.1