From 4611d5bab26f93471b84f6f33967cef69b3f723a Mon Sep 17 00:00:00 2001 From: Sergey Alyoshin Date: Tue, 17 Dec 2013 23:24:54 +0400 Subject: arm: mx5: Add fuse supply enable in fsl_iim MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin Reviewed-by: Benoît Thébaudeau --- arch/arm/cpu/armv7/mx5/clock.c | 12 ++++++++++++ arch/arm/include/asm/arch-mx5/clock.h | 1 + arch/arm/include/asm/arch-mx5/crm_regs.h | 3 +++ 3 files changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index fb3b128..bf52f0d 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable) MXC_CCM_CCGR5_EMI_ENFC(cg)); } +#ifdef CONFIG_FSL_IIM +void enable_efuse_prog_supply(bool enable) +{ + if (enable) + setbits_le32(&mxc_ccm->cgpr, + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); + else + clrbits_le32(&mxc_ccm->cgpr, + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); +} +#endif + /* Config main_bus_clock for periphs */ static int config_periph_clk(u32 ref, u32 freq) { diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 9ee79ae..3db4112 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable); void mxc_set_sata_internal_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_nfc_clk(unsigned char enable); +void enable_efuse_prog_supply(bool enable); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index 392881c..efe57e0 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -305,6 +305,9 @@ struct mxc_ccm_reg { /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) +/* Define the bits in register CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) + /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 #define MXC_CCM_CCGR_CG_OFF 0x0 -- cgit v1.1