From cfd701b5f3eefc98cf699143d34e8a8b737b90a5 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Mon, 27 May 2013 22:55:41 +0000 Subject: arm: vf610: Add IOMUX support for Vybrid VF610 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds the IOMUX support for Vybrid VF610 platform. There is a little difference for IOMUXC module between VF610 and i.MX platform, the muxmode and pad configuration share one 32bit register on VF610, but they are two independent registers on I.MX platform. A CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference. Signed-off-by: Alison Wang Acked-by: Stefano Babic Reviewed-by: Benoît Thébaudeau --- arch/arm/imx-common/Makefile | 2 +- arch/arm/imx-common/iomux-v3.c | 6 ++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 18 ++++++++++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 8bba8a5..9492326 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libimx-common.o -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610)) COBJS-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 7fe5ce7..35880c7 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) __raw_writel(sel_input, base + sel_input_ofs); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG + if (!(pad_ctrl & NO_PAD_CTRL)) + __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl, + base + pad_ctrl_ofs); +#else if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); +#endif } void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 0b4e763..ebf54cf 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -121,6 +121,24 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 << 3) #define PAD_CTL_DSE_34ohm (7 << 3) +#elif defined(CONFIG_VF610) + +#define PAD_MUX_MODE_SHIFT 20 + +#define PAD_CTL_SPEED_MED (1 << 12) +#define PAD_CTL_SPEED_HIGH (3 << 12) + +#define PAD_CTL_DSE_50ohm (3 << 6) +#define PAD_CTL_DSE_25ohm (6 << 6) +#define PAD_CTL_DSE_20ohm (7 << 6) + +#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PKE (1 << 3) +#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) + +#define PAD_CTL_OBE_IBE_ENABLE (3 << 0) + #else #define PAD_CTL_DVS (1 << 13) -- cgit v1.1 From 24e8bee508a341d1de4c708f8d0b9950ee95fab6 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Mon, 27 May 2013 22:55:42 +0000 Subject: arm: vf610: Add Vybrid VF610 CPU support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds generic codes to support Freescale's Vybrid VF610 CPU. It aligns Vybrid VF610 platform with i.MX platform. As there are some differences between VF610 and i.MX platforms, the specific codes are in the arch/arm/cpu/armv7/vf610 directory. Signed-off-by: Alison Wang Reviewed-by: Benoît Thébaudeau --- arch/arm/cpu/armv7/vf610/Makefile | 42 +++ arch/arm/cpu/armv7/vf610/generic.c | 324 ++++++++++++++++++++ arch/arm/cpu/armv7/vf610/timer.c | 103 +++++++ arch/arm/include/asm/arch-vf610/clock.h | 39 +++ arch/arm/include/asm/arch-vf610/crm_regs.h | 225 ++++++++++++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 419 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-vf610/iomux-vf610.h | 101 +++++++ 7 files changed, 1253 insertions(+) create mode 100644 arch/arm/cpu/armv7/vf610/Makefile create mode 100644 arch/arm/cpu/armv7/vf610/generic.c create mode 100644 arch/arm/cpu/armv7/vf610/timer.c create mode 100644 arch/arm/include/asm/arch-vf610/clock.h create mode 100644 arch/arm/include/asm/arch-vf610/crm_regs.h create mode 100644 arch/arm/include/asm/arch-vf610/imx-regs.h create mode 100644 arch/arm/include/asm/arch-vf610/iomux-vf610.h (limited to 'arch') diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile new file mode 100644 index 0000000..9232cd4 --- /dev/null +++ b/arch/arm/cpu/armv7/vf610/Makefile @@ -0,0 +1,42 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS += generic.o +COBJS += timer.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c new file mode 100644 index 0000000..87f2a86 --- /dev/null +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -0,0 +1,324 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_FSL_ESDHC +#include +#endif + +#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&ccm->ccgr6); + if (enable) + reg |= CCM_CCGR6_OCOTP_CTRL_MASK; + else + reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK; + writel(reg, &ccm->ccgr6); +} +#endif + +static u32 get_mcu_main_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_ccsr, ccm_cacrr, armclk_div; + u32 sysclk_sel, pll_pfd_sel = 0; + u32 freq = 0; + + ccm_ccsr = readl(&ccm->ccsr); + sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK; + sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET; + + ccm_cacrr = readl(&ccm->cacrr); + armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK; + armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET; + armclk_div += 1; + + switch (sysclk_sel) { + case 0: + freq = FASE_CLK_FREQ; + break; + case 1: + freq = SLOW_CLK_FREQ; + break; + case 2: + pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK; + pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET; + if (pll_pfd_sel == 0) + freq = PLL2_MAIN_FREQ; + else if (pll_pfd_sel == 1) + freq = PLL2_PFD1_FREQ; + else if (pll_pfd_sel == 2) + freq = PLL2_PFD2_FREQ; + else if (pll_pfd_sel == 3) + freq = PLL2_PFD3_FREQ; + else if (pll_pfd_sel == 4) + freq = PLL2_PFD4_FREQ; + break; + case 3: + freq = PLL2_MAIN_FREQ; + break; + case 4: + pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; + pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET; + if (pll_pfd_sel == 0) + freq = PLL1_MAIN_FREQ; + else if (pll_pfd_sel == 1) + freq = PLL1_PFD1_FREQ; + else if (pll_pfd_sel == 2) + freq = PLL1_PFD2_FREQ; + else if (pll_pfd_sel == 3) + freq = PLL1_PFD3_FREQ; + else if (pll_pfd_sel == 4) + freq = PLL1_PFD4_FREQ; + break; + case 5: + freq = PLL3_MAIN_FREQ; + break; + default: + printf("unsupported system clock select\n"); + } + + return freq / armclk_div; +} + +static u32 get_bus_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_cacrr, busclk_div; + + ccm_cacrr = readl(&ccm->cacrr); + + busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK; + busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET; + busclk_div += 1; + + return get_mcu_main_clk() / busclk_div; +} + +static u32 get_ipg_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_cacrr, ipgclk_div; + + ccm_cacrr = readl(&ccm->cacrr); + + ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK; + ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET; + ipgclk_div += 1; + + return get_bus_clk() / ipgclk_div; +} + +static u32 get_uart_clk(void) +{ + return get_ipg_clk(); +} + +static u32 get_sdhc_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div; + u32 freq = 0; + + ccm_cscmr1 = readl(&ccm->cscmr1); + sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK; + sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET; + + ccm_cscdr2 = readl(&ccm->cscdr2); + sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK; + sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET; + sdhc_clk_div += 1; + + switch (sdhc_clk_sel) { + case 0: + freq = PLL3_MAIN_FREQ; + break; + case 1: + freq = PLL3_PFD3_FREQ; + break; + case 2: + freq = PLL1_PFD3_FREQ; + break; + case 3: + freq = get_bus_clk(); + break; + } + + return freq / sdhc_clk_div; +} + +u32 get_fec_clk(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + u32 ccm_cscmr2, rmii_clk_sel; + u32 freq = 0; + + ccm_cscmr2 = readl(&ccm->cscmr2); + rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK; + rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET; + + switch (rmii_clk_sel) { + case 0: + freq = ENET_EXTERNAL_CLK; + break; + case 1: + freq = AUDIO_EXTERNAL_CLK; + break; + case 2: + freq = PLL5_MAIN_FREQ; + break; + case 3: + freq = PLL5_MAIN_FREQ / 2; + break; + } + + return freq; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_mcu_main_clk(); + case MXC_BUS_CLK: + return get_bus_clk(); + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_UART_CLK: + return get_uart_clk(); + case MXC_ESDHC_CLK: + return get_sdhc_clk(); + case MXC_FEC_CLK: + return get_fec_clk(); + default: + break; + } + return -1; +} + +/* Dump some core clocks */ +int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + printf("\n"); + printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000); + printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000); + + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks, + "display clocks", + "" +); + +#ifdef CONFIG_FEC_MXC +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[4]; + struct fuse_bank4_regs *fuse = + (struct fuse_bank4_regs *)bank->fuse_regs; + + u32 value = readl(&fuse->mac_addr0); + mac[0] = (value >> 8); + mac[1] = value; + + value = readl(&fuse->mac_addr1); + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; +} +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +static char *get_reset_cause(void) +{ + u32 cause; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + cause = readl(&src_regs->srsr); + writel(cause, &src_regs->srsr); + cause &= 0xff; + + switch (cause) { + case 0x08: + return "WDOG"; + case 0x20: + return "JTAG HIGH-Z"; + case 0x80: + return "EXTERNAL RESET"; + case 0xfd: + return "POR"; + default: + return "unknown reset"; + } +} + +int print_cpuinfo(void) +{ + printf("CPU: Freescale Vybrid VF610 at %d MHz\n", + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause()); + + return 0; +} +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_FEC_MXC) + rc = fecmxc_initialize(bis); +#endif + + return rc; +} + +#ifdef CONFIG_FSL_ESDHC +int cpu_mmc_init(bd_t *bis) +{ + return fsl_esdhc_mmc_init(bis); +} +#endif + +int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} diff --git a/arch/arm/cpu/armv7/vf610/timer.c b/arch/arm/cpu/armv7/vf610/timer.c new file mode 100644 index 0000000..f8fbed7 --- /dev/null +++ b/arch/arm/cpu/armv7/vf610/timer.c @@ -0,0 +1,103 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +static struct pit_reg *cur_pit = (struct pit_reg *)PIT_BASE_ADDR; + +DECLARE_GLOBAL_DATA_PTR; + +#define TIMER_LOAD_VAL 0xffffffff + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, mxc_get_clock(MXC_IPG_CLK)); + + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long usec) +{ + usec = usec * mxc_get_clock(MXC_IPG_CLK) + 999999; + do_div(usec, 1000000); + + return usec; +} + +int timer_init(void) +{ + __raw_writel(0, &cur_pit->mcr); + + __raw_writel(TIMER_LOAD_VAL, &cur_pit->ldval1); + __raw_writel(0, &cur_pit->tctrl1); + __raw_writel(1, &cur_pit->tctrl1); + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +unsigned long long get_ticks(void) +{ + ulong now = TIMER_LOAD_VAL - __raw_readl(&cur_pit->cval1); + + /* increment tbu if tbl has rolled over */ + if (now < gd->arch.tbl) + gd->arch.tbu++; + gd->arch.tbl = now; + + return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* delay x useconds AND preserve advance timstamp value */ +void __udelay(unsigned long usec) +{ + unsigned long long start; + ulong tmo; + + start = get_ticks(); /* get current timestamp */ + tmo = us_to_tick(usec); /* convert usecs to ticks */ + while ((get_ticks() - start) < tmo) + ; /* loop till time has passed */ +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return mxc_get_clock(MXC_IPG_CLK); +} diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h new file mode 100644 index 0000000..04e418c --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -0,0 +1,39 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#include + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_BUS_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_FEC_CLK, +}; + +void enable_ocotp_clk(unsigned char enable); +unsigned int mxc_get_clock(enum mxc_clock clk); + +#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h new file mode 100644 index 0000000..e3f703d --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -0,0 +1,225 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__ +#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__ + +#ifndef __ASSEMBLY__ + +/* Clock Controller Module (CCM) */ +struct ccm_reg { + u32 ccr; + u32 csr; + u32 ccsr; + u32 cacrr; + u32 cscmr1; + u32 cscdr1; + u32 cscdr2; + u32 cscdr3; + u32 cscmr2; + u32 cscdr4; + u32 ctor; + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; + u32 cgpr; + u32 ccgr0; + u32 ccgr1; + u32 ccgr2; + u32 ccgr3; + u32 ccgr4; + u32 ccgr5; + u32 ccgr6; + u32 ccgr7; + u32 ccgr8; + u32 ccgr9; + u32 ccgr10; + u32 ccgr11; + u32 cmeor0; + u32 cmeor1; + u32 cmeor2; + u32 cmeor3; + u32 cmeor4; + u32 cmeor5; + u32 cppdsr; + u32 ccowr; + u32 ccpgr0; + u32 ccpgr1; + u32 ccpgr2; + u32 ccpgr3; +}; + +/* Analog components control digital interface (ANADIG) */ +struct anadig_reg { + u32 pll3_ctrl; + u32 resv0[3]; + u32 pll7_ctrl; + u32 resv1[3]; + u32 pll2_ctrl; + u32 resv2[3]; + u32 pll2_ss; + u32 resv3[3]; + u32 pll2_num; + u32 resv4[3]; + u32 pll2_denom; + u32 resv5[3]; + u32 pll4_ctrl; + u32 resv6[3]; + u32 pll4_num; + u32 resv7[3]; + u32 pll4_denom; + u32 pll6_ctrl; + u32 resv8[3]; + u32 pll6_num; + u32 resv9[3]; + u32 pll6_denom; + u32 resv10[3]; + u32 pll5_ctrl; + u32 resv11[3]; + u32 pll3_pfd; + u32 resv12[3]; + u32 pll2_pfd; + u32 resv13[3]; + u32 reg_1p1; + u32 resv14[3]; + u32 reg_3p0; + u32 resv15[3]; + u32 reg_2p5; + u32 resv16[7]; + u32 ana_misc0; + u32 resv17[3]; + u32 ana_misc1; + u32 resv18[63]; + u32 anadig_digprog; + u32 resv19[3]; + u32 pll1_ctrl; + u32 resv20[3]; + u32 pll1_ss; + u32 resv21[3]; + u32 pll1_num; + u32 resv22[3]; + u32 pll1_denom; + u32 resv23[3]; + u32 pll1_pdf; + u32 resv24[3]; + u32 pll_lock; +}; +#endif + +#define CCM_CCR_FIRC_EN (1 << 16) +#define CCM_CCR_OSCNT_MASK 0xff +#define CCM_CCR_OSCNT(v) ((v) & 0xff) + +#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 +#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) +#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) + +#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 +#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) +#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) + +#define CCM_CCSR_PLL2_PFD4_EN (1 << 15) +#define CCM_CCSR_PLL2_PFD3_EN (1 << 14) +#define CCM_CCSR_PLL2_PFD2_EN (1 << 13) +#define CCM_CCSR_PLL2_PFD1_EN (1 << 12) +#define CCM_CCSR_PLL1_PFD4_EN (1 << 11) +#define CCM_CCSR_PLL1_PFD3_EN (1 << 10) +#define CCM_CCSR_PLL1_PFD2_EN (1 << 9) +#define CCM_CCSR_PLL1_PFD1_EN (1 << 8) + +#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) +#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) + +#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 +#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 +#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) + +#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 +#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) +#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) +#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 +#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) +#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) +#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 +#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 +#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) + +#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 +#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) +#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) + +#define CCM_CSCDR1_RMII_CLK_EN (1 << 24) + +#define CCM_CSCDR2_ESDHC1_EN (1 << 29) +#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 +#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) +#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) + +#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 +#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) +#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) + +#define CCM_REG_CTRL_MASK 0xffffffff +#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) +#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) +#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) +#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) +#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) +#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) +#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) +#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) +#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 +#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) +#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) +#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) +#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) +#define CCM_CCGR9_FEC0_CTRL_MASK 0x3 +#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) + +#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL2_CTRL_DIV_SELECT 1 +#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL1_CTRL_DIV_SELECT 1 + +#define FASE_CLK_FREQ 24000000 +#define SLOW_CLK_FREQ 32000 +#define PLL1_PFD1_FREQ 500000000 +#define PLL1_PFD2_FREQ 452000000 +#define PLL1_PFD3_FREQ 396000000 +#define PLL1_PFD4_FREQ 528000000 +#define PLL1_MAIN_FREQ 528000000 +#define PLL2_PFD1_FREQ 500000000 +#define PLL2_PFD2_FREQ 396000000 +#define PLL2_PFD3_FREQ 339000000 +#define PLL2_PFD4_FREQ 413000000 +#define PLL2_MAIN_FREQ 528000000 +#define PLL3_MAIN_FREQ 480000000 +#define PLL3_PFD3_FREQ 298000000 +#define PLL5_MAIN_FREQ 500000000 + +#define ENET_EXTERNAL_CLK 50000000 +#define AUDIO_EXTERNAL_CLK 24576000 + +#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h new file mode 100644 index 0000000..c9df32a --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -0,0 +1,419 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IMX_REGS_H__ +#define __ASM_ARCH_IMX_REGS_H__ + +#define ARCH_MXC + +#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */ +#define IRAM_SIZE 0x00080000 /* 512 KB */ + +#define AIPS0_BASE_ADDR 0x40000000 +#define AIPS1_BASE_ADDR 0x40080000 + +/* AIPS 0 */ +#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) +#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800) +#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) +#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000) +#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000) +#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000) +#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000) +#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) +#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) +#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000) +#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) +#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000) +#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000) +#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) +#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000) +#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000) +#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000) +#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000) +#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000) +#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000) +#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000) +#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000) +#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000) +#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000) +#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000) +#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000) +#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000) +#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000) +#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000) +#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000) +#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000) +#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000) +#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) +#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) +#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) +#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000) +#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) +#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) +#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) +#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) +#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000) +#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000) +#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000) +#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000) +#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) +#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000) +#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) +#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) +#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) +#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) +#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) +#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) +#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) +#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) +#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000) +#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) +#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000) +#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000) +#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) +#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) +#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) +#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) + +/* AIPS 1 */ +#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) +#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000) +#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) +#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) +#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) + +/* MUX mode and PAD ctrl are in one register */ +#define CONFIG_IOMUX_SHARE_CONF_REG + +#define FEC_QUIRK_ENET_MAC + +/* MSCM interrupt rounter */ +#define MSCM_IRSPRC_CP0_EN 1 +#define MSCM_IRSPRC_NUM 112 + +/* DDRMC */ +#define DDRMC_PHY_DQ_TIMING 0x00002613 +#define DDRMC_PHY_DQS_TIMING 0x00002615 +#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_MASTER_CTRL 0x0001012a +#define DDRMC_PHY_SLAVE_CTRL 0x00012020 + +#define DDRMC_PHY50_DDR3_MODE (1 << 12) +#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) + +#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8) +#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8) +#define DDRMC_CR00_START 1 +#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff) +#define DDRMC_CR10_TRST_PWRON(v) (v) +#define DDRMC_CR11_CKE_INACTIVE(v) (v) +#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8) +#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f) +#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24) +#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16) +#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8) +#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7) +#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24) +#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16) +#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8) +#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff) +#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24) +#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16) +#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8) +#define DDRMC_CR17_TMOD(v) ((v) & 0xff) +#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8) +#define DDRMC_CR18_TCKE(v) ((v) & 0x7) +#define DDRMC_CR20_AP_EN (1 << 24) +#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16) +#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8) +#define DDRMC_CR21_CCMAP_EN 1 +#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) +#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) +#define DDRMC_CR23_TDLL(v) ((v) & 0xff) +#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) +#define DDRMC_CR25_TREF_EN (1 << 16) +#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) +#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff) +#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff) +#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff) +#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff) +#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16) +#define DDRMC_CR31_TXSR(v) ((v) & 0xffff) +#define DDRMC_CR33_EN_QK_SREF (1 << 16) +#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) +#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) +#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) +#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) +#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) +#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) +#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1 +#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16) +#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff) +#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16) +#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff) +#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) +#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) +#define DDRMC_CR70_REF_PER_ZQ(v) (v) +#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) +#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) +#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) +#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) +#define DDRMC_CR74_BANKSPLT_EN (1 << 24) +#define DDRMC_CR74_ADDR_CMP_EN (1 << 16) +#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8) +#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff) +#define DDRMC_CR75_RW_PG_EN (1 << 24) +#define DDRMC_CR75_RW_EN (1 << 16) +#define DDRMC_CR75_PRI_EN (1 << 8) +#define DDRMC_CR75_PLEN 1 +#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24) +#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16) +#define DDRMC_CR76_W2R_SPLT_EN (1 << 8) +#define DDRMC_CR76_CS_EN 1 +#define DDRMC_CR77_CS_MAP (1 << 24) +#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) +#define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) +#define DDRMC_CR79_CTLUPD_AREF (1 << 24) +#define DDRMC_CR82_INT_MASK 0x1fffffff +#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) +#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) +#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) +#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) +#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) +#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) +#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) +#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) +#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) +#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) +#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) +#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16) +#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24) +#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16) +#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8) +#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24) +#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16) +#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) +#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) +#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) +#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) +#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) +#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) +#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) +#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) +#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) +#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) +#define DDRMC_CR155_AXI0_AWCACHE (1 << 10) +#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) +#define DDRMC_CR158_TWR(v) ((v) & 0x3f) + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 sbmr1; + u32 srsr; + u32 secr; + u32 gpsr; + u32 sicr; + u32 simr; + u32 sbmr2; + u32 gpr0; + u32 gpr1; + u32 gpr2; + u32 gpr3; + u32 gpr4; + u32 hab0; + u32 hab1; + u32 hab2; + u32 hab3; + u32 hab4; + u32 hab5; + u32 misc0; + u32 misc1; + u32 misc2; + u32 misc3; +}; + +/* Periodic Interrupt Timer (PIT) */ +struct pit_reg { + u32 mcr; + u32 recv0[55]; + u32 ltmr64h; + u32 ltmr64l; + u32 recv1[6]; + u32 ldval0; + u32 cval0; + u32 tctrl0; + u32 tflg0; + u32 ldval1; + u32 cval1; + u32 tctrl1; + u32 tflg1; + u32 ldval2; + u32 cval2; + u32 tctrl2; + u32 tflg2; + u32 ldval3; + u32 cval3; + u32 tctrl3; + u32 tflg3; + u32 ldval4; + u32 cval4; + u32 tctrl4; + u32 tflg4; + u32 ldval5; + u32 cval5; + u32 tctrl5; + u32 tflg5; + u32 ldval6; + u32 cval6; + u32 tctrl6; + u32 tflg6; + u32 ldval7; + u32 cval7; + u32 tctrl7; + u32 tflg7; +}; + +/* Watchdog Timer (WDOG) */ +struct wdog_regs { + u16 wcr; + u16 wsr; + u16 wrsr; + u16 wicr; + u16 wmcr; +}; + +/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */ +struct ddrmr_regs { + u32 cr[162]; + u32 rsvd[94]; + u32 phy[53]; +}; + +/* On-Chip One Time Programmable Controller (OCOTP) */ +struct ocotp_regs { + u32 ctrl; + u32 ctrl_set; + u32 ctrl_clr; + u32 ctrl_tog; + u32 timing; + u32 rsvd0[3]; + u32 data; + u32 rsvd1[3]; + u32 read_ctrl; + u32 rsvd2[3]; + u32 read_fuse_data; + u32 rsvd3[7]; + u32 scs; + u32 scs_set; + u32 scs_clr; + u32 scs_tog; + u32 crc_addr; + u32 rsvd4[3]; + u32 crc_value; + u32 rsvd5[3]; + u32 version; + u32 rsvd6[0xdb]; + + struct fuse_bank { + u32 fuse_regs[0x20]; + } bank[16]; +}; + +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[3]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[0x17]; +}; + +struct fuse_bank4_regs { + u32 sjc_resp0; + u32 rsvd0[3]; + u32 sjc_resp1; + u32 rsvd1[3]; + u32 mac_addr0; + u32 rsvd2[3]; + u32 mac_addr1; + u32 rsvd3[3]; + u32 mac_addr2; + u32 rsvd4[3]; + u32 mac_addr3; + u32 rsvd5[3]; + u32 gp1; + u32 rsvd6[3]; + u32 gp2; + u32 rsvd7[3]; +}; + +/* UART */ +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; + +/* MSCM Interrupt Router */ +struct mscm_ir { + u32 ircp0ir; + u32 ircp1ir; + u32 rsvd1[6]; + u32 ircpgir; + u32 rsvd2[23]; + u16 irsprc[112]; + u16 rsvd3[848]; +}; + +#endif /* __ASSEMBLER__*/ + +#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h new file mode 100644 index 0000000..1c728fa --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -0,0 +1,101 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IOMUX_VF610_H__ +#define __IOMUX_VF610_H__ + +#include + +/* Pad control groupings */ +#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ + PAD_CTL_OBE_IBE_ENABLE) +#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm + +enum { + VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), + VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), +}; + +#endif /* __IOMUX_VF610_H__ */ -- cgit v1.1 From 86fb7b3d5b8ae7158cfcd408b847d3d8295e3aae Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 25 Apr 2013 16:37:12 +0000 Subject: arm: mxs: Fix vectoring table crafting The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28 starts from RAM, so the vectoring table at 0x0 is not present. Craft code that will be placed at 0x0 and will redirect interrupt vectoring to proper location of the U-Boot in RAM. Signed-off-by: Marek Vasut CC: Stefano Babic CC: Fabio Estevam Tested-by: Fabio Estevam --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index a5e388b..45667bd 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -76,13 +76,32 @@ void enable_caches(void) #endif } +/* + * This function will craft a jumptable at 0x0 which will redirect interrupt + * vectoring to proper location of U-Boot in RAM. + * + * The structure of the jumptable will be as follows: + * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times + * ... for each previous ldr, thus also repeated 8 times + * + * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at + * offset 0x18 from current value of PC register. Note that PC is already + * incremented by 4 when computing the offset, so the effective offset is + * actually 0x20, this the associated . Loading the PC + * register with an address performs a jump to that address. + */ void mx28_fixup_vt(uint32_t start_addr) { - uint32_t *vt = (uint32_t *)0x20; + /* ldr pc, [pc, #0x18] */ + const uint32_t ldr_pc = 0xe59ff018; + /* Jumptable location is 0x0 */ + uint32_t *vt = (uint32_t *)0x0; int i; - for (i = 0; i < 8; i++) - vt[i] = start_addr + (4 * i); + for (i = 0; i < 8; i++) { + vt[i] = ldr_pc; + vt[i + 8] = start_addr + (4 * i); + } } #ifdef CONFIG_ARCH_MISC_INIT -- cgit v1.1 From dbc000bfb51eb30d786521e6b8e29048c36cbefa Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 23 May 2013 12:26:18 +0000 Subject: ARM: tegra: only enable SCU on Tegra20 The non-SPL build of U-Boot on Tegra only runs on a single CPU, and hence there is no need to enable the SCU when running U-Boot. If an SMP OS is booted, and it needs the SCU enabled, it will enable the SCU itself. U-Boot doing so is redundant. The one exception is Tegra20, where an enabled SCU is required for some aspects of PCIe to work correctly. Some Tegra SoCs contain CPUs without a software-controlled SCU. In this case, attempting to turn it on actively causes problems. This is the case for Tegra114. For example, when running Linux, the first (or at least some very early) user-space process will trigger the following kernel message: Unhandled fault: imprecise external abort (0x406) at 0x00000000 This is typically accompanied by that process receving a fatal signal, and exiting. Since this process is usually pid 1, this causes total system boot failure. Signed-off-by: Tom Warren [swarren, fleshed out description, ported to upstream chipid APIs] Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/cpu/tegra-common/ap.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index e099683..9e6d51d 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -109,6 +109,10 @@ static void enable_scu(void) struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; u32 reg; + /* Only enable the SCU on T20/T25 */ + if (tegra_get_chip() != CHIPID_TEGRA20) + return; + /* If SCU already setup/enabled, return */ if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) return; -- cgit v1.1 From 4d0df9c1e94f32a9695be352fead3167fb5135c7 Mon Sep 17 00:00:00 2001 From: Andrii Tseglytskyi Date: Mon, 20 May 2013 22:42:08 +0000 Subject: OMAP3+: introduce generic ABB support Adaptive Body Biasing (ABB) modulates transistor bias voltages dynamically in order to optimize switching speed versus leakage. Adaptive Body-Bias ldos are present for some voltage domains starting with OMAP3630. There are three modes of operation: * Bypass - the default, it just follows the vdd voltage * Foward Body-Bias - applies voltage bias to increase transistor performance at the cost of power. Used to operate safely at high OPPs. * Reverse Body-Bias - applies voltage bias to decrease leakage and save power. Used to save power at lower OPPs. Signed-off-by: Andrii Tseglytskyi Acked-by: Nishanth Menon --- arch/arm/cpu/armv7/omap-common/Makefile | 1 + arch/arm/cpu/armv7/omap-common/abb.c | 137 ++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap5/Makefile | 1 + arch/arm/cpu/armv7/omap5/abb.c | 67 ++++++++++++++++ arch/arm/include/asm/arch-omap3/omap3.h | 7 ++ arch/arm/include/asm/arch-omap4/omap.h | 8 ++ arch/arm/include/asm/arch-omap5/omap.h | 13 +++ arch/arm/include/asm/omap_common.h | 22 +++++ 8 files changed, 256 insertions(+) create mode 100644 arch/arm/cpu/armv7/omap-common/abb.c create mode 100644 arch/arm/cpu/armv7/omap5/abb.c (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 55e82ba..c4b9809 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -34,6 +34,7 @@ COBJS += hwinit-common.o COBJS += clocks-common.o COBJS += emif-common.o COBJS += vc.o +COBJS += abb.o endif ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c new file mode 100644 index 0000000..87d1fb8 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/abb.c @@ -0,0 +1,137 @@ +/* + * + * Adaptive Body Bias programming sequence for OMAP family + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Andrii Tseglytskyi + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) +{ + return -1; +} + +static void abb_setup_timings(u32 setup) +{ + u32 sys_rate, sr2_cnt, clk_cycles; + + /* + * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a + * transition and must be programmed with the correct time at boot. + * The value programmed into the register is the number of SYS_CLK + * clock cycles that match a given wall time profiled for the ldo. + * This value depends on: + * settling time of ldo in micro-seconds (varies per OMAP family), + * of clock cycles per SYS_CLK period (varies per OMAP family), + * the SYS_CLK frequency in MHz (varies per board) + * The formula is: + * + * ldo settling time (in micro-seconds) + * SR2_WTCNT_VALUE = ------------------------------------------ + * (# system clock cycles) * (sys_clk period) + * + * Put another way: + * + * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate)) + * + * To avoid dividing by zero multiply both "# clock cycles" and + * "settling time" by 10 such that the final result is the one we want. + */ + + /* calculate SR2_WTCNT_VALUE */ + sys_rate = DIV_ROUND(V_OSCK, 1000000); + clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate); + sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles); + + setbits_le32(setup, + sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1)); +} + +void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, + u32 txdone, u32 txdone_mask, u32 opp) +{ + u32 abb_type_mask, opp_sel_mask; + + /* sanity check */ + if (!setup || !control || !txdone) + return; + + /* setup ABB only in case of Fast or Slow OPP */ + switch (opp) { + case OMAP_ABB_FAST_OPP: + abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK; + opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK; + break; + case OMAP_ABB_SLOW_OPP: + abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK; + opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK; + break; + default: + return; + } + + /* + * For some OMAP silicons additional setup for LDOVBB register is + * required. This is determined by data retrieved from corresponding + * OPP EFUSE register. Data, which is retrieved from EFUSE - is + * ABB enable/disable flag and VSET value, which must be copied + * to LDOVBB register. If function call fails - return quietly, + * it means no ABB is required for such silicon. + * + * For silicons, which don't require LDOVBB setup "fuse" and + * "ldovbb" offsets are not defined. ABB will be initialized in + * the common way for them. + */ + if (fuse && ldovbb) { + if (abb_setup_ldovbb(fuse, ldovbb)) + return; + } + + /* clear ABB registers */ + writel(0, setup); + writel(0, control); + + /* configure timings, based on oscillator value */ + abb_setup_timings(setup); + + /* clear pending interrupts before setup */ + setbits_le32(txdone, txdone_mask); + + /* select ABB type */ + setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK); + + /* initiate ABB ldo change */ + setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); + + /* wait until transition complete */ + if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY)) + puts("Error: ABB txdone is not set\n"); + + /* clear ABB tranxdone */ + setbits_le32(txdone, txdone_mask); +} diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index ce00e2c..6ff8dbb 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -30,6 +30,7 @@ COBJS += emif.o COBJS += sdram.o COBJS += prcm-regs.o COBJS += hw_data.o +COBJS += abb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c new file mode 100644 index 0000000..92470be --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/abb.c @@ -0,0 +1,67 @@ +/* + * + * Adaptive Body Bias programming sequence for OMAP5 family + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Andrii Tseglytskyi + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Setup LDOVBB for OMAP5. + * On OMAP5+ some ABB settings are fused. They are handled + * in the following way: + * + * 1. corresponding EFUSE register contains ABB enable bit + * and VSET value + * 2. If ABB enable bit is set to 1, than ABB should be + * enabled, otherwise ABB should be disabled + * 3. If ABB is enabled, than VSET value should be copied + * to corresponding MUX control register + */ +s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) +{ + u32 vset; + + /* + * ABB parameters must be properly fused + * otherwise ABB should be disabled + */ + vset = readl(fuse); + if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK)) + return -1; + + /* prepare VSET value for LDOVBB mux register */ + vset &= OMAP5_ABB_FUSE_VSET_MASK; + vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1; + vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; + vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK; + + /* setup LDOVBB using fused value */ + clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset); + + return 0; +} diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 2b5e9ae..c57599a 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -253,4 +253,11 @@ struct gpio { #define OMAP3_EMU_HAL_START_HAL_CRITICAL 4 +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 30 +#define OMAP_ABB_CLOCK_CYCLES 8 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26) + #endif diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index e9a6ffe..55a0760 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -143,4 +143,12 @@ struct s32ktimer { #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4030D000 + +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 50 +#define OMAP_ABB_CLOCK_CYCLES 16 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) + #endif diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 4f43a90..1c1a64b 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -215,6 +215,19 @@ struct s32ktimer { #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 50 +#define OMAP_ABB_CLOCK_CYCLES 16 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) + +/* ABB efuse masks */ +#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) +#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) +#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) +#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) + #ifndef __ASSEMBLY__ struct srcomp_params { s8 divide_factor; diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index ee7b188..f8f3719 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -242,6 +242,8 @@ struct prcm_regs { u32 cm_l3init_fsusb_clkctrl; u32 cm_l3init_ocp2scp1_clkctrl; + u32 prm_irqstatus_mpu_2; + /* cm2.l4per */ u32 cm_l4per_clkstctrl; u32 cm_l4per_dynamicdep; @@ -328,6 +330,8 @@ struct prcm_regs { u32 prm_sldo_mpu_ctrl; u32 prm_sldo_mm_setup; u32 prm_sldo_mm_ctrl; + u32 prm_abbldo_mpu_setup; + u32 prm_abbldo_mpu_ctrl; u32 cm_div_m4_dpll_core; u32 cm_div_m5_dpll_core; @@ -350,6 +354,7 @@ struct prcm_regs { struct omap_sys_ctrl_regs { u32 control_status; + u32 control_std_fuse_opp_vdd_mpu_2; u32 control_core_mmr_lock1; u32 control_core_mmr_lock2; u32 control_core_mmr_lock3; @@ -419,6 +424,7 @@ struct omap_sys_ctrl_regs { u32 control_port_emif2_sdram_config; u32 control_emif1_sdram_config_ext; u32 control_emif2_sdram_config_ext; + u32 control_wkup_ldovbb_mpu_voltage_ctrl; u32 control_smart1nopmio_padconf_0; u32 control_smart1nopmio_padconf_1; u32 control_padconf_mode; @@ -545,6 +551,9 @@ void enable_non_essential_clocks(void); void scale_vcores(struct vcores_data const *); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); +void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, + u32 txdone, u32 txdone_mask, u32 opp); +s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); /* Max value for DPLL multiplier M */ #define OMAP_DPLL_MAX_N 127 @@ -555,6 +564,19 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 +/* ABB */ +#define OMAP_ABB_NOMINAL_OPP 0 +#define OMAP_ABB_FAST_OPP 1 +#define OMAP_ABB_SLOW_OPP 3 +#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0) +#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1) +#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2) +#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6) +#define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0) +#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2) +#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1) +#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8) + static inline u32 omap_revision(void) { extern u32 *const omap_si_rev; -- cgit v1.1 From e69c585d76b7c8f422ad488ea92268c60dc2a436 Mon Sep 17 00:00:00 2001 From: Andrii Tseglytskyi Date: Mon, 20 May 2013 22:42:09 +0000 Subject: OMAP5: add ABB setup for MPU voltage domain Patch adds a call of abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain. Signed-off-by: Andrii Tseglytskyi --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 9 +++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 7 +++++++ 2 files changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 99910cd..f86f79b 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -533,6 +533,15 @@ void scale_vcores(struct vcores_data const *vcores) do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic); + /* Configure MPU ABB LDO after scale */ + abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2, + (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, + (*prcm)->prm_abbldo_mpu_setup, + (*prcm)->prm_abbldo_mpu_ctrl, + (*prcm)->prm_irqstatus_mpu_2, + OMAP_ABB_MPU_TXDONE_MASK, + OMAP_ABB_FAST_OPP); + do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index e9f6a32..6bff8ae 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -311,6 +311,7 @@ struct prcm_regs const omap5_es1_prcm = { struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, + .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, .control_paconf_global = 0x4A002DA0, .control_paconf_mode = 0x4A002DA4, .control_smart1io_padconf_0 = 0x4A002DA8, @@ -358,6 +359,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_port_emif2_sdram_config = 0x4AE0C118, .control_emif1_sdram_config_ext = 0x4AE0C144, .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318, .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, .control_padconf_mode = 0x4AE0CDA8, @@ -709,6 +711,9 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, + /* prm irqstatus regs */ + .prm_irqstatus_mpu_2 = 0x4ae06014, + /* l4 wkup regs */ .cm_abe_pll_ref_clksel = 0x4ae0610c, .cm_sys_clksel = 0x4ae06110, @@ -740,6 +745,8 @@ struct prcm_regs const omap5_es2_prcm = { .prm_sldo_mpu_ctrl = 0x4ae07cd0, .prm_sldo_mm_setup = 0x4ae07cd4, .prm_sldo_mm_ctrl = 0x4ae07cd8, + .prm_abbldo_mpu_setup = 0x4ae07cdc, + .prm_abbldo_mpu_ctrl = 0x4ae07ce0, }; struct prcm_regs const dra7xx_prcm = { -- cgit v1.1 From e0a8c99e6103a9052510ea9e2067c18cb688e1cb Mon Sep 17 00:00:00 2001 From: Lubomir Popov Date: Sun, 26 May 2013 10:03:17 +0000 Subject: OMAP5: Fix bug in omap5_es1_prcm struct The newly introduced function setup_warmreset_time(), called from within prcm_init(), tries to write to the prm_rsttime OMAP5 register. The struct member holding this register's address is however initialized for OMAP5 ES2.0 only. On ES1.0 devices this uninitialized value causes a second (warm) reset at startup. Add .prm_rsttime address init to the ES1.0 struct. Signed-off-by: Lubomir Popov Acked-by: Tom Rini --- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 6bff8ae..5010739 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -298,6 +298,7 @@ struct prcm_regs const omap5_es1_prcm = { .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, .prm_rstctrl = 0x4ae07b00, .prm_rstst = 0x4ae07b04, + .prm_rsttime = 0x4ae07b08, .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, -- cgit v1.1 From 9239f5b62550e9f1438c784cb8d1e578dc3852a8 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 02:54:30 +0000 Subject: ARM: OMAP4+: Cleanup header files After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap4/prcm-regs.c | 3 +++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 ++ arch/arm/include/asm/arch-omap4/clocks.h | 28 ---------------------------- arch/arm/include/asm/arch-omap4/cpu.h | 12 ------------ arch/arm/include/asm/arch-omap4/omap.h | 14 -------------- arch/arm/include/asm/arch-omap5/clocks.h | 22 ---------------------- arch/arm/include/asm/arch-omap5/cpu.h | 12 ------------ arch/arm/include/asm/arch-omap5/omap.h | 31 +------------------------------ arch/arm/include/asm/omap_common.h | 4 +--- 9 files changed, 7 insertions(+), 121 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index 7225a30..7e71ca0 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -301,6 +301,8 @@ struct omap_sys_ctrl_regs const omap4_ctrl = { .control_ldosram_iva_voltage_ctrl = 0x4A002320, .control_ldosram_mpu_voltage_ctrl = 0x4A002324, .control_ldosram_core_voltage_ctrl = 0x4A002328, + .control_usbotghs_ctrl = 0x4A00233C, + .control_padconf_core_base = 0x4A100000, .control_pbiaslite = 0x4A100600, .control_lpddr2io1_0 = 0x4A100638, .control_lpddr2io1_1 = 0x4A10063C, @@ -312,4 +314,5 @@ struct omap_sys_ctrl_regs const omap4_ctrl = { .control_lpddr2io2_3 = 0x4A100654, .control_efuse_1 = 0x4A100700, .control_efuse_2 = 0x4A100704, + .control_padconf_wkup_base = 0x4A31E000, }; diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 5010739..f3b3155 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -313,6 +313,7 @@ struct prcm_regs const omap5_es1_prcm = { struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, + .control_padconf_core_base = 0x4A002800, .control_paconf_global = 0x4A002DA0, .control_paconf_mode = 0x4A002DA4, .control_smart1io_padconf_0 = 0x4A002DA8, @@ -361,6 +362,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_emif1_sdram_config_ext = 0x4AE0C144, .control_emif2_sdram_config_ext = 0x4AE0C148, .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318, + .control_padconf_wkup_base = 0x4AE0C800, .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, .control_padconf_mode = 0x4AE0CDA8, diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index ed7a1c8..f544edf 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -34,25 +34,6 @@ */ #define LDELAY 1000000 -#define CM_CLKMODE_DPLL_CORE 0x4A004120 -#define CM_CLKMODE_DPLL_PER 0x4A008140 -#define CM_CLKMODE_DPLL_MPU 0x4A004160 -#define CM_CLKSEL_CORE 0x4A004100 - -/* DPLL register offsets */ -#define CM_CLKMODE_DPLL 0 -#define CM_IDLEST_DPLL 0x4 -#define CM_AUTOIDLE_DPLL 0x8 -#define CM_CLKSEL_DPLL 0xC -#define CM_DIV_M2_DPLL 0x10 -#define CM_DIV_M3_DPLL 0x14 -#define CM_DIV_M4_DPLL 0x18 -#define CM_DIV_M5_DPLL 0x1C -#define CM_DIV_M6_DPLL 0x20 -#define CM_DIV_M7_DPLL 0x24 - -#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ - /* CM_DLL_CTRL */ #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) @@ -94,8 +75,6 @@ #define CM_CLKSEL_DCC_EN_SHIFT 22 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) -#define OMAP4_DPLL_MAX_N 127 - /* CM_SYS_CLKSEL */ #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 @@ -181,9 +160,7 @@ #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) /* Clock frequencies */ -#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 -#define OMAP_32K_CLK_FREQ 32768 /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 @@ -234,11 +211,6 @@ #define ALTCLKSRC_MODE_ACTIVE 1 -/* Defines for DPLL setup */ -#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 -#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 -#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 - #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index 3a0bfbf..311c6ff 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -115,18 +115,6 @@ struct watchdog { #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 -#define SYSCLKDIV_1 (0x1 << 6) -#define SYSCLKDIV_2 (0x1 << 7) - -#define CLKSEL_GPT1 (0x1 << 0) - -#define EN_GPT1 (0x1 << 0) -#define EN_32KSYNC (0x1 << 2) - -#define ST_WDT2 (0x1 << 5) - -#define RESETDONE (0x1 << 0) - #define TCLR_ST (0x1 << 0) #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 55a0760..66afd92 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -47,14 +47,6 @@ #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END -/* CONTROL */ -#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) -#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) -#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000) - -/* LPDDR2 IO regs */ -#define LPDDR2_IO_REGS_BASE 0x4A100638 - /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE 0x4A002204 @@ -79,15 +71,9 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000) - /* GPMC */ #define OMAP44XX_GPMC_BASE 0x50000000 -/* SYSTEM CONTROL MODULE */ -#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000 - /* * Hardware Register Details */ diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 68afa76..6673a02 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -35,19 +35,6 @@ */ #define LDELAY 1000000 -#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120) -#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140) -#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160) -#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100) - -/* DPLL register offsets */ -#define CM_CLKMODE_DPLL 0 -#define CM_IDLEST_DPLL 0x4 -#define CM_AUTOIDLE_DPLL 0x8 -#define CM_CLKSEL_DPLL 0xC - -#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ - /* CM_DLL_CTRL */ #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) @@ -93,8 +80,6 @@ #define CM_CLKSEL_DCC_EN_SHIFT 22 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) -#define OMAP4_DPLL_MAX_N 127 - /* CM_SYS_CLKSEL */ #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 @@ -195,9 +180,7 @@ #define RSTTIME1_MASK (0x3ff << 0) /* Clock frequencies */ -#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 -#define OMAP_32K_CLK_FREQ 32768 /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 @@ -247,11 +230,6 @@ #define TPS62361_BASE_VOLT_MV 500 #define TPS62361_VSEL0_GPIO 7 -/* Defines for DPLL setup */ -#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 -#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 -#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 - #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 044ab55..4753f46 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -119,18 +119,6 @@ struct watchdog { #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 -#define SYSCLKDIV_1 (0x1 << 6) -#define SYSCLKDIV_2 (0x1 << 7) - -#define CLKSEL_GPT1 (0x1 << 0) - -#define EN_GPT1 (0x1 << 0) -#define EN_32KSYNC (0x1 << 2) - -#define ST_WDT2 (0x1 << 5) - -#define RESETDONE (0x1 << 0) - #define TCLR_ST (0x1 << 0) #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 1c1a64b..4fcd99f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -44,16 +44,8 @@ #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END -/* CONTROL */ -#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) -#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800) -#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800) - -/* LPDDR2 IO regs. To be verified */ -#define LPDDR2_IO_REGS_BASE 0x4A100638 - /* CONTROL_ID_CODE */ -#define CONTROL_ID_CODE (CTRL_BASE + 0x204) +#define CONTROL_ID_CODE 0x4A002204 /* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F @@ -62,11 +54,6 @@ #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F -/* STD_FUSE_PROD_ID_1 */ -#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) -#define PROD_ID_1_SILICON_TYPE_SHIFT 16 -#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16) - /* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) @@ -80,15 +67,9 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000) - /* GPMC */ #define OMAP54XX_GPMC_BASE 0x50000000 -/* SYSTEM CONTROL MODULE */ -#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000 - /* * Hardware Register Details */ @@ -191,16 +172,6 @@ struct s32ktimer { /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 -/* Silicon revisions */ -#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF -#define OMAP4430_ES1_0 0x44300100 -#define OMAP4430_ES2_0 0x44300200 -#define OMAP4430_ES2_1 0x44300210 -#define OMAP4430_ES2_2 0x44300220 -#define OMAP4430_ES2_3 0x44300230 -#define OMAP4460_ES1_0 0x44600100 -#define OMAP4460_ES1_1 0x44600110 - /* CONTROL_SRCOMP_XXX_SIDE */ #define OVERRIDE_XS_SHIFT 30 #define OVERRIDE_XS_MASK (1 << 30) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index f8f3719..712d78b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -367,6 +367,7 @@ struct omap_sys_ctrl_regs { u32 control_ldosram_iva_voltage_ctrl; u32 control_ldosram_mpu_voltage_ctrl; u32 control_ldosram_core_voltage_ctrl; + u32 control_usbotghs_ctrl; u32 control_padconf_core_base; u32 control_paconf_global; u32 control_paconf_mode; @@ -555,9 +556,6 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, u32 txdone, u32 txdone_mask, u32 opp); s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); -/* Max value for DPLL multiplier M */ -#define OMAP_DPLL_MAX_N 127 - /* HW Init Context */ #define OMAP_INIT_CONTEXT_SPL 0 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 -- cgit v1.1 From bcdd8f72f34bcf2a6e9730e37dd2d2292548a8a4 Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Thu, 30 May 2013 02:54:31 +0000 Subject: ARM: OMAP5: clocks: Do not enable sgx clocks SGX clocks should be enabled only for OMAP5 ES1.0. So this can be removed. Signed-off-by: Sricharan R Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap5/hw_data.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 604fa42..842cf27 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -383,12 +383,6 @@ void enable_basic_clocks(void) clk_modules_explicit_en_essential, 1); - /* Select 384Mhz for GPU as its the POR for ES1.0 */ - setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, - CLKSEL_GPU_HYD_GCLK_MASK); - setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, - CLKSEL_GPU_CORE_GCLK_MASK); - /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); -- cgit v1.1 From af1d002f896e7f9cda47c384db31349cf923e95c Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 02:54:32 +0000 Subject: ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h To be consistent with other ARM platforms, renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 2 +- arch/arm/cpu/armv7/omap-common/emif-common.c | 2 +- arch/arm/cpu/armv7/omap3/clock.c | 2 +- arch/arm/cpu/armv7/omap4/hw_data.c | 2 +- arch/arm/cpu/armv7/omap5/hw_data.c | 2 +- arch/arm/cpu/armv7/omap5/hwinit.c | 2 +- arch/arm/include/asm/arch-omap24xx/clock.h | 112 +++++++++++ arch/arm/include/asm/arch-omap24xx/clocks.h | 112 ----------- arch/arm/include/asm/arch-omap3/clock.h | 80 ++++++++ arch/arm/include/asm/arch-omap3/clocks.h | 80 -------- arch/arm/include/asm/arch-omap4/clock.h | 257 +++++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/clocks.h | 257 ------------------------- arch/arm/include/asm/arch-omap4/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap5/clock.h | 242 +++++++++++++++++++++++ arch/arm/include/asm/arch-omap5/clocks.h | 242 ----------------------- arch/arm/include/asm/arch-omap5/sys_proto.h | 4 +- 16 files changed, 700 insertions(+), 700 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap24xx/clock.h delete mode 100644 arch/arm/include/asm/arch-omap24xx/clocks.h create mode 100644 arch/arm/include/asm/arch-omap3/clock.h delete mode 100644 arch/arm/include/asm/arch-omap3/clocks.h create mode 100644 arch/arm/include/asm/arch-omap4/clock.h delete mode 100644 arch/arm/include/asm/arch-omap4/clocks.h create mode 100644 arch/arm/include/asm/arch-omap5/clock.h delete mode 100644 arch/arm/include/asm/arch-omap5/clocks.h (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index f86f79b..403b672 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 11e830a..8823967 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 09c51f6..81cc859 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 06a2fc8..650319a 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 842cf27..d2f5900 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index e192fea..afb7000 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/include/asm/arch-omap24xx/clock.h b/arch/arm/include/asm/arch-omap24xx/clock.h new file mode 100644 index 0000000..2e92569 --- /dev/null +++ b/arch/arm/include/asm/arch-omap24xx/clock.h @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_CLOCKS_H_ +#define _OMAP24XX_CLOCKS_H_ + +#define COMMIT_DIVIDERS 0x1 + +#define MODE_BYPASS_FAST 0x2 +#define APLL_LOCK 0xc +#ifdef CONFIG_APTIX +#define DPLL_LOCK 0x1 /* stay in bypass mode */ +#else +#define DPLL_LOCK 0x3 /* DPLL lock */ +#endif + +/****************************************************************************; +; PRCM Scheme II +; +; Enable clocks and DPLL for: +; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 +; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] +; DSPI=100 6 CM_CLKSEL_DSP[6:5] +; DSP_S bypass CM_CLKSEL_DSP[7] +; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] +; IVAF=100 auto +; IVAI auto +; IVA_MPU auto +; IVA_S bypass CM_CLKSEL_DSP[13] +; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] +; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=100 auto +; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] +; L4=100Mhz 6 +; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define II_DPLL_OUT_X2 0x2 /* x2 core out */ +#define II_MPU_DIV 0x2 /* mpu = core/2 */ +#define II_DSP_DIV 0x343 /* dsp & iva divider */ +#define II_GFX_DIV 0x2 +#define II_BUS_DIV 0x04601026 +#define II_DPLL_300 0x01832100 + +/****************************************************************************; +; PRCM Scheme III +; +; Enable clocks and DPLL for: +; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 +; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] +; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] +; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] +; DSP_S ACTIVATED CM_CLKSEL_DSP[7] +; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] +; IVAF=88.67 auto +; IVAI auto +; IVA_MPU auto +; IVA_S ACTIVATED CM_CLKSEL_DSP[13] +; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: +; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=88.67 auto +; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] +; L4=66.5Mhz /8 +; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define III_DPLL_OUT_X2 0x2 /* x2 core out */ +#define III_MPU_DIV 0x2 /* mpu = core/2 */ +#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ +#define III_GFX_DIV 0x2 +#define III_BUS_DIV 0x08301044 +#define III_DPLL_266 0x01885500 + +/* set defaults for boot up */ +#ifdef PRCM_CONFIG_II +# define DPLL_OUT II_DPLL_OUT_X2 +# define MPU_DIV II_MPU_DIV +# define DSP_DIV II_DSP_DIV +# define GFX_DIV II_GFX_DIV +# define BUS_DIV II_BUS_DIV +# define DPLL_VAL II_DPLL_300 +#elif PRCM_CONFIG_III +# define DPLL_OUT III_DPLL_OUT_X2 +# define MPU_DIV III_MPU_DIV +# define DSP_DIV III_DSP_DIV +# define GFX_DIV III_GFX_DIV +# define BUS_DIV III_BUS_DIV +# define DPLL_VAL III_DPLL_266 +#endif + +/* lock delay time out */ +#define LDELAY 12000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap24xx/clocks.h b/arch/arm/include/asm/arch-omap24xx/clocks.h deleted file mode 100644 index 2e92569..0000000 --- a/arch/arm/include/asm/arch-omap24xx/clocks.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_CLOCKS_H_ -#define _OMAP24XX_CLOCKS_H_ - -#define COMMIT_DIVIDERS 0x1 - -#define MODE_BYPASS_FAST 0x2 -#define APLL_LOCK 0xc -#ifdef CONFIG_APTIX -#define DPLL_LOCK 0x1 /* stay in bypass mode */ -#else -#define DPLL_LOCK 0x3 /* DPLL lock */ -#endif - -/****************************************************************************; -; PRCM Scheme II -; -; Enable clocks and DPLL for: -; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 -; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] -; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] -; DSPI=100 6 CM_CLKSEL_DSP[6:5] -; DSP_S bypass CM_CLKSEL_DSP[7] -; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] -; IVAF=100 auto -; IVAI auto -; IVA_MPU auto -; IVA_S bypass CM_CLKSEL_DSP[13] -; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] -; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=100 auto -; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] -; L4=100Mhz 6 -; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define II_DPLL_OUT_X2 0x2 /* x2 core out */ -#define II_MPU_DIV 0x2 /* mpu = core/2 */ -#define II_DSP_DIV 0x343 /* dsp & iva divider */ -#define II_GFX_DIV 0x2 -#define II_BUS_DIV 0x04601026 -#define II_DPLL_300 0x01832100 - -/****************************************************************************; -; PRCM Scheme III -; -; Enable clocks and DPLL for: -; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 -; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] -; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] -; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] -; DSP_S ACTIVATED CM_CLKSEL_DSP[7] -; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] -; IVAF=88.67 auto -; IVAI auto -; IVA_MPU auto -; IVA_S ACTIVATED CM_CLKSEL_DSP[13] -; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: -; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=88.67 auto -; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] -; L4=66.5Mhz /8 -; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define III_DPLL_OUT_X2 0x2 /* x2 core out */ -#define III_MPU_DIV 0x2 /* mpu = core/2 */ -#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ -#define III_GFX_DIV 0x2 -#define III_BUS_DIV 0x08301044 -#define III_DPLL_266 0x01885500 - -/* set defaults for boot up */ -#ifdef PRCM_CONFIG_II -# define DPLL_OUT II_DPLL_OUT_X2 -# define MPU_DIV II_MPU_DIV -# define DSP_DIV II_DSP_DIV -# define GFX_DIV II_GFX_DIV -# define BUS_DIV II_BUS_DIV -# define DPLL_VAL II_DPLL_300 -#elif PRCM_CONFIG_III -# define DPLL_OUT III_DPLL_OUT_X2 -# define MPU_DIV III_MPU_DIV -# define DSP_DIV III_DSP_DIV -# define GFX_DIV III_GFX_DIV -# define BUS_DIV III_BUS_DIV -# define DPLL_VAL III_DPLL_266 -#endif - -/* lock delay time out */ -#define LDELAY 12000000 - -#endif diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h new file mode 100644 index 0000000..bed0002 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_H_ +#define _CLOCKS_H_ + +#define LDELAY 12000000 + +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#define FCK_IVA2_ON 0x00000001 +#define FCK_CORE1_ON 0x03fffe29 +#define ICK_CORE1_ON 0x3ffffffb +#define ICK_CORE2_ON 0x0000001f +#define FCK_WKUP_ON 0x000000e9 +#define ICK_WKUP_ON 0x0000003f +#define FCK_DSS_ON 0x00000005 +#define ICK_DSS_ON 0x00000001 +#define FCK_CAM_ON 0x00000001 +#define ICK_CAM_ON 0x00000001 +#define FCK_PER_ON 0x0003ffff +#define ICK_PER_ON 0x0003ffff + +/* Used to index into DPLL parameter tables */ +typedef struct { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +} dpll_param; + +struct dpll_per_36x_param { + unsigned int sys_clk; + unsigned int m; + unsigned int n; + unsigned int m2; + unsigned int m3; + unsigned int m4; + unsigned int m5; + unsigned int m6; + unsigned int m2div; +}; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param *get_mpu_dpll_param(void); +extern dpll_param *get_iva_dpll_param(void); +extern dpll_param *get_core_dpll_param(void); +extern dpll_param *get_per_dpll_param(void); +extern dpll_param *get_per2_dpll_param(void); + +extern dpll_param *get_36x_mpu_dpll_param(void); +extern dpll_param *get_36x_iva_dpll_param(void); +extern dpll_param *get_36x_core_dpll_param(void); +extern dpll_param *get_36x_per_dpll_param(void); + +extern void *_end_vect, *_start; + +#endif diff --git a/arch/arm/include/asm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clocks.h deleted file mode 100644 index bed0002..0000000 --- a/arch/arm/include/asm/arch-omap3/clocks.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _CLOCKS_H_ -#define _CLOCKS_H_ - -#define LDELAY 12000000 - -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#define FCK_IVA2_ON 0x00000001 -#define FCK_CORE1_ON 0x03fffe29 -#define ICK_CORE1_ON 0x3ffffffb -#define ICK_CORE2_ON 0x0000001f -#define FCK_WKUP_ON 0x000000e9 -#define ICK_WKUP_ON 0x0000003f -#define FCK_DSS_ON 0x00000005 -#define ICK_DSS_ON 0x00000001 -#define FCK_CAM_ON 0x00000001 -#define ICK_CAM_ON 0x00000001 -#define FCK_PER_ON 0x0003ffff -#define ICK_PER_ON 0x0003ffff - -/* Used to index into DPLL parameter tables */ -typedef struct { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -} dpll_param; - -struct dpll_per_36x_param { - unsigned int sys_clk; - unsigned int m; - unsigned int n; - unsigned int m2; - unsigned int m3; - unsigned int m4; - unsigned int m5; - unsigned int m6; - unsigned int m2div; -}; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(void); -extern dpll_param *get_iva_dpll_param(void); -extern dpll_param *get_core_dpll_param(void); -extern dpll_param *get_per_dpll_param(void); -extern dpll_param *get_per2_dpll_param(void); - -extern dpll_param *get_36x_mpu_dpll_param(void); -extern dpll_param *get_36x_iva_dpll_param(void); -extern dpll_param *get_36x_core_dpll_param(void); -extern dpll_param *get_36x_per_dpll_param(void); - -extern void *_end_vect, *_start; - -#endif diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h new file mode 100644 index 0000000..f544edf --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP4_H_ +#define _CLOCKS_OMAP4_H_ +#include +#include + +/* + * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per + * loop, allow for a minimum of 2 ms wait (in reality the wait will be + * much more than that) + */ +#define LDELAY 1000000 + +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F +#define CM_CLKSEL_DCC_EN_SHIFT 22 +#define CM_CLKSEL_DCC_EN_MASK (1 << 22) + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_ABE_PLL_REF_CLKSEL */ +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 + +/* CM_BYPCLK_DPLL_IVA */ +#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 +#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 + +#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/*CM___CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + + +/* CM___CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_CAM_ISS_CLKCTRL */ +#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_DSS_DSS_CLKCTRL */ +#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 + +/* CM_MPU_MPU_CLKCTRL */ +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) + +/* Clock frequencies */ +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + +/* SMPS */ +#define SMPS_I2C_SLAVE_ADDR 0x12 +#define SMPS_REG_ADDR_VCORE1 0x55 +#define SMPS_REG_ADDR_VCORE2 0x5B +#define SMPS_REG_ADDR_VCORE3 0x61 + +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 + +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 +#define TPS62361_VSEL0_GPIO 7 + +/* AUXCLKx reg fields */ +#define AUXCLK_ENABLE_MASK (1 << 8) +#define AUXCLK_SRCSELECT_SHIFT 1 +#define AUXCLK_SRCSELECT_MASK (3 << 1) +#define AUXCLK_CLKDIV_SHIFT 16 +#define AUXCLK_CLKDIV_MASK (0xF << 16) + +#define AUXCLK_SRCSELECT_SYS_CLK 0 +#define AUXCLK_SRCSELECT_CORE_DPLL 1 +#define AUXCLK_SRCSELECT_PER_DPLL 2 +#define AUXCLK_SRCSELECT_ALTERNATE 3 + +#define AUXCLK_CLKDIV_2 1 +#define AUXCLK_CLKDIV_16 0xF + +/* ALTCLKSRC */ +#define ALTCLKSRC_MODE_MASK 3 +#define ALTCLKSRC_ENABLE_INT_MASK 4 +#define ALTCLKSRC_ENABLE_EXT_MASK 8 + +#define ALTCLKSRC_MODE_ACTIVE 1 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +struct omap4_scrm_regs { + u32 revision; /* 0x0000 */ + u32 pad00[63]; + u32 clksetuptime; /* 0x0100 */ + u32 pmicsetuptime; /* 0x0104 */ + u32 pad01[2]; + u32 altclksrc; /* 0x0110 */ + u32 pad02[2]; + u32 c2cclkm; /* 0x011c */ + u32 pad03[56]; + u32 extclkreq; /* 0x0200 */ + u32 accclkreq; /* 0x0204 */ + u32 pwrreq; /* 0x0208 */ + u32 pad04[1]; + u32 auxclkreq0; /* 0x0210 */ + u32 auxclkreq1; /* 0x0214 */ + u32 auxclkreq2; /* 0x0218 */ + u32 auxclkreq3; /* 0x021c */ + u32 auxclkreq4; /* 0x0220 */ + u32 auxclkreq5; /* 0x0224 */ + u32 pad05[3]; + u32 c2cclkreq; /* 0x0234 */ + u32 pad06[54]; + u32 auxclk0; /* 0x0310 */ + u32 auxclk1; /* 0x0314 */ + u32 auxclk2; /* 0x0318 */ + u32 auxclk3; /* 0x031c */ + u32 auxclk4; /* 0x0320 */ + u32 auxclk5; /* 0x0324 */ + u32 pad07[54]; + u32 rsttime_reg; /* 0x0400 */ + u32 pad08[6]; + u32 c2crstctrl; /* 0x041c */ + u32 extpwronrstctrl; /* 0x0420 */ + u32 pad09[59]; + u32 extwarmrstst_reg; /* 0x0510 */ + u32 apewarmrstst_reg; /* 0x0514 */ + u32 pad10[1]; + u32 c2cwarmrstst_reg; /* 0x051C */ +}; +#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h deleted file mode 100644 index f544edf..0000000 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _CLOCKS_OMAP4_H_ -#define _CLOCKS_OMAP4_H_ -#include -#include - -/* - * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per - * loop, allow for a minimum of 2 ms wait (in reality the wait will be - * much more than that) - */ -#define LDELAY 1000000 - -/* CM_DLL_CTRL */ -#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 -#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) -#define CM_DLL_CTRL_NO_OVERRIDE 0 - -/* CM_CLKMODE_DPLL */ -#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) -#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 -#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_FAST_RELOCK_BYPASS 6 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F -#define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) - -/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 - -/* CM_CLKSEL_CORE */ -#define CLKSEL_CORE_SHIFT 0 -#define CLKSEL_L3_SHIFT 4 -#define CLKSEL_L4_SHIFT 8 - -#define CLKSEL_CORE_X2_DIV_1 0 -#define CLKSEL_L3_CORE_DIV_2 1 -#define CLKSEL_L4_L3_DIV_2 1 - -/* CM_ABE_PLL_REF_CLKSEL */ -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 - -/* CM_BYPCLK_DPLL_IVA */ -#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 -#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 - -#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 - -/* CM_SHADOW_FREQ_CONFIG1 */ -#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 -#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 -#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 - -#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 -#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) - -#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 -#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) - -/*CM___CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 -#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - - -/* CM___CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_CAM_ISS_CLKCTRL */ -#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_DSS_DSS_CLKCTRL */ -#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 - -/* CM_L3INIT_USBPHY_CLKCTRL */ -#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 - -/* CM_MPU_MPU_CLKCTRL */ -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) - -/* Clock frequencies */ -#define OMAP_SYS_CLK_IND_38_4_MHZ 6 - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 - -/* SMPS */ -#define SMPS_I2C_SLAVE_ADDR 0x12 -#define SMPS_REG_ADDR_VCORE1 0x55 -#define SMPS_REG_ADDR_VCORE2 0x5B -#define SMPS_REG_ADDR_VCORE3 0x61 - -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 - -/* TPS */ -#define TPS62361_I2C_SLAVE_ADDR 0x60 -#define TPS62361_REG_ADDR_SET0 0x0 -#define TPS62361_REG_ADDR_SET1 0x1 -#define TPS62361_REG_ADDR_SET2 0x2 -#define TPS62361_REG_ADDR_SET3 0x3 -#define TPS62361_REG_ADDR_CTRL 0x4 -#define TPS62361_REG_ADDR_TEMP 0x5 -#define TPS62361_REG_ADDR_RMP_CTRL 0x6 -#define TPS62361_REG_ADDR_CHIP_ID 0x8 -#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 - -#define TPS62361_BASE_VOLT_MV 500 -#define TPS62361_VSEL0_GPIO 7 - -/* AUXCLKx reg fields */ -#define AUXCLK_ENABLE_MASK (1 << 8) -#define AUXCLK_SRCSELECT_SHIFT 1 -#define AUXCLK_SRCSELECT_MASK (3 << 1) -#define AUXCLK_CLKDIV_SHIFT 16 -#define AUXCLK_CLKDIV_MASK (0xF << 16) - -#define AUXCLK_SRCSELECT_SYS_CLK 0 -#define AUXCLK_SRCSELECT_CORE_DPLL 1 -#define AUXCLK_SRCSELECT_PER_DPLL 2 -#define AUXCLK_SRCSELECT_ALTERNATE 3 - -#define AUXCLK_CLKDIV_2 1 -#define AUXCLK_CLKDIV_16 0xF - -/* ALTCLKSRC */ -#define ALTCLKSRC_MODE_MASK 3 -#define ALTCLKSRC_ENABLE_INT_MASK 4 -#define ALTCLKSRC_ENABLE_EXT_MASK 8 - -#define ALTCLKSRC_MODE_ACTIVE 1 - -#define DPLL_NO_LOCK 0 -#define DPLL_LOCK 1 - -struct omap4_scrm_regs { - u32 revision; /* 0x0000 */ - u32 pad00[63]; - u32 clksetuptime; /* 0x0100 */ - u32 pmicsetuptime; /* 0x0104 */ - u32 pad01[2]; - u32 altclksrc; /* 0x0110 */ - u32 pad02[2]; - u32 c2cclkm; /* 0x011c */ - u32 pad03[56]; - u32 extclkreq; /* 0x0200 */ - u32 accclkreq; /* 0x0204 */ - u32 pwrreq; /* 0x0208 */ - u32 pad04[1]; - u32 auxclkreq0; /* 0x0210 */ - u32 auxclkreq1; /* 0x0214 */ - u32 auxclkreq2; /* 0x0218 */ - u32 auxclkreq3; /* 0x021c */ - u32 auxclkreq4; /* 0x0220 */ - u32 auxclkreq5; /* 0x0224 */ - u32 pad05[3]; - u32 c2cclkreq; /* 0x0234 */ - u32 pad06[54]; - u32 auxclk0; /* 0x0310 */ - u32 auxclk1; /* 0x0314 */ - u32 auxclk2; /* 0x0318 */ - u32 auxclk3; /* 0x031c */ - u32 auxclk4; /* 0x0320 */ - u32 auxclk5; /* 0x0324 */ - u32 pad07[54]; - u32 rsttime_reg; /* 0x0400 */ - u32 pad08[6]; - u32 c2crstctrl; /* 0x041c */ - u32 extpwronrstctrl; /* 0x0420 */ - u32 pad09[59]; - u32 extwarmrstst_reg; /* 0x0510 */ - u32 apewarmrstst_reg; /* 0x0514 */ - u32 pad10[1]; - u32 c2cwarmrstst_reg; /* 0x051C */ -}; -#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ef85594..0126a85 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -22,7 +22,7 @@ #define _SYS_PROTO_H_ #include -#include +#include #include #include #include diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h new file mode 100644 index 0000000..6673a02 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -0,0 +1,242 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * Sricharan R + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP5_H_ +#define _CLOCKS_OMAP5_H_ +#include +#include + +/* + * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per + * loop, allow for a minimum of 2 ms wait (in reality the wait will be + * much more than that) + */ +#define LDELAY 1000000 + +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* SGX */ +#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) +#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F +#define CM_CLKSEL_DCC_EN_SHIFT 22 +#define CM_CLKSEL_DCC_EN_MASK (1 << 22) + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_ABE_PLL_REF_CLKSEL */ +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 + +/* CM_BYPCLK_DPLL_IVA */ +#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 +#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 + +#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/*CM___CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + + +/* CM___CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_CAM_ISS_CLKCTRL */ +#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_DSS_DSS_CLKCTRL */ +#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 + +/* CM_MPU_MPU_CLKCTRL */ +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) + +/* CM_WKUPAON_SCRM_CLKCTRL */ +#define OPTFCLKEN_SCRM_PER_SHIFT 9 +#define OPTFCLKEN_SCRM_PER_MASK (1 << 9) +#define OPTFCLKEN_SCRM_CORE_SHIFT 8 +#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) + +/* CM_COREAON_IO_SRCOMP_CLKCTRL */ +#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 +#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) + +/* PRM_RSTTIME */ +#define RSTTIME1_SHIFT 0 +#define RSTTIME1_MASK (0x3ff << 0) + +/* Clock frequencies */ +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + +/* SMPS */ +#define SMPS_I2C_SLAVE_ADDR 0x12 +#define SMPS_REG_ADDR_12_MPU 0x23 +#define SMPS_REG_ADDR_45_IVA 0x2B +#define SMPS_REG_ADDR_8_CORE 0x37 + +/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ +/* ES1.0 settings */ +#define VDD_MPU 1040 +#define VDD_MM 1040 +#define VDD_CORE 1040 + +#define VDD_MPU_LOW 890 +#define VDD_MM_LOW 890 +#define VDD_CORE_LOW 890 + +/* ES2.0 settings */ +#define VDD_MPU_ES2 1060 +#define VDD_MM_ES2 1025 +#define VDD_CORE_ES2 1040 + +#define VDD_MPU_ES2_HIGH 1250 +#define VDD_MM_ES2_OD 1120 + +#define VDD_MPU_ES2_LOW 880 +#define VDD_MM_ES2_LOW 880 + +/* Standard offset is 0.5v expressed in uv */ +#define PALMAS_SMPS_BASE_VOLT_UV 500000 + +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 +#define TPS62361_VSEL0_GPIO 7 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +/* + * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. + * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles + * into microsec and passing the value. + */ +#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 +#endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h deleted file mode 100644 index 6673a02..0000000 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - * Sricharan R - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _CLOCKS_OMAP5_H_ -#define _CLOCKS_OMAP5_H_ -#include -#include - -/* - * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per - * loop, allow for a minimum of 2 ms wait (in reality the wait will be - * much more than that) - */ -#define LDELAY 1000000 - -/* CM_DLL_CTRL */ -#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 -#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) -#define CM_DLL_CTRL_NO_OVERRIDE 0 - -/* CM_CLKMODE_DPLL */ -#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) -#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 -#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_FAST_RELOCK_BYPASS 6 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* SGX */ -#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) -#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F -#define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) - -/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 - -/* CM_CLKSEL_CORE */ -#define CLKSEL_CORE_SHIFT 0 -#define CLKSEL_L3_SHIFT 4 -#define CLKSEL_L4_SHIFT 8 - -#define CLKSEL_CORE_X2_DIV_1 0 -#define CLKSEL_L3_CORE_DIV_2 1 -#define CLKSEL_L4_L3_DIV_2 1 - -/* CM_ABE_PLL_REF_CLKSEL */ -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 - -/* CM_BYPCLK_DPLL_IVA */ -#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 -#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 - -#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 - -/* CM_SHADOW_FREQ_CONFIG1 */ -#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 -#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 -#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 - -#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 -#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) - -#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 -#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) - -/*CM___CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 -#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - - -/* CM___CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) -#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) - -/* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_CAM_ISS_CLKCTRL */ -#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_DSS_DSS_CLKCTRL */ -#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 - -/* CM_L3INIT_USBPHY_CLKCTRL */ -#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 - -/* CM_MPU_MPU_CLKCTRL */ -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) - -/* CM_WKUPAON_SCRM_CLKCTRL */ -#define OPTFCLKEN_SCRM_PER_SHIFT 9 -#define OPTFCLKEN_SCRM_PER_MASK (1 << 9) -#define OPTFCLKEN_SCRM_CORE_SHIFT 8 -#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) - -/* CM_COREAON_IO_SRCOMP_CLKCTRL */ -#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 -#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) - -/* PRM_RSTTIME */ -#define RSTTIME1_SHIFT 0 -#define RSTTIME1_MASK (0x3ff << 0) - -/* Clock frequencies */ -#define OMAP_SYS_CLK_IND_38_4_MHZ 6 - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 - -/* SMPS */ -#define SMPS_I2C_SLAVE_ADDR 0x12 -#define SMPS_REG_ADDR_12_MPU 0x23 -#define SMPS_REG_ADDR_45_IVA 0x2B -#define SMPS_REG_ADDR_8_CORE 0x37 - -/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ -/* ES1.0 settings */ -#define VDD_MPU 1040 -#define VDD_MM 1040 -#define VDD_CORE 1040 - -#define VDD_MPU_LOW 890 -#define VDD_MM_LOW 890 -#define VDD_CORE_LOW 890 - -/* ES2.0 settings */ -#define VDD_MPU_ES2 1060 -#define VDD_MM_ES2 1025 -#define VDD_CORE_ES2 1040 - -#define VDD_MPU_ES2_HIGH 1250 -#define VDD_MM_ES2_OD 1120 - -#define VDD_MPU_ES2_LOW 880 -#define VDD_MM_ES2_LOW 880 - -/* Standard offset is 0.5v expressed in uv */ -#define PALMAS_SMPS_BASE_VOLT_UV 500000 - -/* TPS */ -#define TPS62361_I2C_SLAVE_ADDR 0x60 -#define TPS62361_REG_ADDR_SET0 0x0 -#define TPS62361_REG_ADDR_SET1 0x1 -#define TPS62361_REG_ADDR_SET2 0x2 -#define TPS62361_REG_ADDR_SET3 0x3 -#define TPS62361_REG_ADDR_CTRL 0x4 -#define TPS62361_REG_ADDR_TEMP 0x5 -#define TPS62361_REG_ADDR_RMP_CTRL 0x6 -#define TPS62361_REG_ADDR_CHIP_ID 0x8 -#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 - -#define TPS62361_BASE_VOLT_MV 500 -#define TPS62361_VSEL0_GPIO 7 - -#define DPLL_NO_LOCK 0 -#define DPLL_LOCK 1 - -/* - * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. - * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles - * into microsec and passing the value. - */ -#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 -#endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 4d99db9..fb35a82 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -23,9 +23,9 @@ #include #include -#include +#include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; -- cgit v1.1 From 4ca94d81869f8c9ba3e72eac3a99d3eef29df991 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 02:54:33 +0000 Subject: ARM: OMAP4+: pmic: Make generic bus init and write functions Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data so that we can call as per our requirement. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 6 ++---- arch/arm/cpu/armv7/omap-common/vc.c | 14 +++++++++++++- arch/arm/cpu/armv7/omap4/hw_data.c | 11 ++++++++++- arch/arm/cpu/armv7/omap5/hw_data.c | 3 +++ arch/arm/include/asm/arch-omap4/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap5/sys_proto.h | 2 +- arch/arm/include/asm/omap_common.h | 3 +++ 7 files changed, 33 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 403b672..6c8e063 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -487,6 +487,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) u32 offset = volt_mv; int ret = 0; + pmic->pmic_bus_init(); /* See if we can first get the GPIO if needed */ if (pmic->gpio_en) ret = gpio_request(pmic->gpio, "PMIC_GPIO"); @@ -509,8 +510,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, offset_code); - if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR, - vcore_reg, offset_code)) + if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code)) printf("Scaling voltage failed for 0x%x\n", vcore_reg); if (pmic->gpio_en) @@ -525,8 +525,6 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) */ void scale_vcores(struct vcores_data const *vcores) { - omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); - do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic); diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c index e6e5f78..a68f1d1 100644 --- a/arch/arm/cpu/armv7/omap-common/vc.c +++ b/arch/arm/cpu/armv7/omap-common/vc.c @@ -17,6 +17,7 @@ #include #include #include +#include /* * Define Master code if there are multiple masters on the I2C_SR bus. @@ -57,7 +58,7 @@ * omap_vc_init() - Initialization for Voltage controller * @speed_khz: I2C buspeed in KHz */ -void omap_vc_init(u16 speed_khz) +static void omap_vc_init(u16 speed_khz) { u32 val; u32 sys_clk_khz, cycles_hi, cycles_low; @@ -137,3 +138,14 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) /* All good.. */ return 0; } + +void sri2c_init(void) +{ + static int sri2c = 1; + + if (sri2c) { + omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); + sri2c = 0; + } + return; +} diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 650319a..b97cad4 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -219,6 +219,9 @@ struct pmic_data twl6030_4430es1 = { .step = 12660, /* 12.66 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; struct pmic_data twl6030 = { @@ -226,6 +229,9 @@ struct pmic_data twl6030 = { .step = 12660, /* 12.66 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; struct pmic_data tps62361 = { @@ -233,7 +239,10 @@ struct pmic_data tps62361 = { .step = 10000, /* 10 mV represented in uV */ .start_code = 0, .gpio = TPS62361_VSEL0_GPIO, - .gpio_en = 1 + .gpio_en = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; struct vcores_data omap4430_volts_es1 = { diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index d2f5900..585e318 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -289,6 +289,9 @@ struct pmic_data palmas = { * Offset code 0 switches OFF the SMPS */ .start_code = 6, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, }; struct vcores_data omap5430_volts = { diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 0126a85..15e3682 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -57,7 +57,7 @@ u32 cortex_rev(void); void save_omap_boot_params(void); void init_omap_revision(void); void do_io_settings(void); -void omap_vc_init(u16 speed_khz); +void sri2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index fb35a82..91eb36c 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -61,7 +61,7 @@ u32 cortex_rev(void); void save_omap_boot_params(void); void init_omap_revision(void); void do_io_settings(void); -void omap_vc_init(u16 speed_khz); +void sri2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 712d78b..b70575b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -501,6 +501,9 @@ struct pmic_data { u32 start_code; unsigned gpio; int gpio_en; + u32 i2c_slave_addr; + void (*pmic_bus_init)(void); + int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); }; struct volts { -- cgit v1.1 From 4de28d7921908d8b222fac331111c94e048ee282 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 03:19:28 +0000 Subject: ARM: DRA7xx: Add control id code for DRA7xx The registers that are used for device identification are changed from OMAP5 to DRA7xx. Using the correct registers for DRA7xx. Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-omap5/omap.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 4fcd99f..43a629f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -44,8 +44,15 @@ #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END -/* CONTROL_ID_CODE */ -#define CONTROL_ID_CODE 0x4A002204 +/* CONTROL ID CODE */ +#define CONTROL_CORE_ID_CODE 0x4A002204 +#define CONTROL_WKUP_ID_CODE 0x4AE0C204 + +#ifdef CONFIG_DRA7XX +#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE +#else +#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE +#endif /* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F -- cgit v1.1 From 63fc0c775c1eb86b9a1abb4e37311bbcf1dca008 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 03:19:29 +0000 Subject: ARM: DRA7xx: power Add support for tps659038 PMIC TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 23 ++++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 38 +++++++++++++++++++++++++- arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + arch/arm/include/asm/arch-omap5/clock.h | 15 ++++++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/omap_common.h | 3 ++ 6 files changed, 80 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 6c8e063..eda3451 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -30,6 +30,7 @@ * MA 02111-1307 USA */ #include +#include #include #include #include @@ -487,6 +488,9 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) u32 offset = volt_mv; int ret = 0; + if (!volt_mv) + return; + pmic->pmic_bus_init(); /* See if we can first get the GPIO if needed */ if (pmic->gpio_en) @@ -543,6 +547,15 @@ void scale_vcores(struct vcores_data const *vcores) do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic); + do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, + vcores->gpu.pmic); + + do_scale_vcore(vcores->eve.addr, vcores->eve.value, + vcores->eve.pmic); + + do_scale_vcore(vcores->iva.addr, vcores->iva.value, + vcores->iva.pmic); + if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ writel(2, (*prcm)->prm_sldo_core_setup); @@ -732,3 +745,13 @@ void prcm_init(void) if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) enable_basic_uboot_clocks(); } + +void gpi2c_init(void) +{ + static int gpi2c = 1; + + if (gpi2c) { + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gpi2c = 0; + } +} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 585e318..90274a0 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -26,6 +26,7 @@ * MA 02111-1307 USA */ #include +#include #include #include #include @@ -294,6 +295,19 @@ struct pmic_data palmas = { .pmic_write = omap_vc_bypass_send_value, }; +struct pmic_data tps659038 = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, + .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, +}; + struct vcores_data omap5430_volts = { .mpu.value = VDD_MPU, .mpu.addr = SMPS_REG_ADDR_12_MPU, @@ -322,6 +336,28 @@ struct vcores_data omap5430_volts_es2 = { .mm.pmic = &palmas, }; +struct vcores_data dra752_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -562,7 +598,7 @@ void hw_data_init(void) case DRA752_ES1_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; - *omap_vcores = &omap5430_volts_es2; + *omap_vcores = &dra752_volts; *ctrl = &dra7xx_ctrl; break; diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 15e3682..e413466 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -58,6 +58,7 @@ void save_omap_boot_params(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 6673a02..f7ddd5f 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -212,9 +212,24 @@ #define VDD_MPU_ES2_LOW 880 #define VDD_MM_ES2_LOW 880 +/* TPS659038 Voltage settings in mv for OPP_NOMINAL */ +#define VDD_MPU_DRA752 1090 +#define VDD_EVE_DRA752 1060 +#define VDD_GPU_DRA752 1060 +#define VDD_CORE_DRA752 1030 +#define VDD_IVA_DRA752 1060 + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 +/* TPS659038 */ +#define TPS659038_I2C_SLAVE_ADDR 0x58 +#define TPS659038_REG_ADDR_SMPS12_MPU 0x23 +#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B +#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F +#define TPS659038_REG_ADDR_SMPS7_CORE 0x33 +#define TPS659038_REG_ADDR_SMPS8_IVA 0x37 + /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 #define TPS62361_REG_ADDR_SET0 0x0 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 91eb36c..0bb59d8 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -62,6 +62,7 @@ void save_omap_boot_params(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index b70575b..3b8bece 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -516,6 +516,9 @@ struct vcores_data { struct volts mpu; struct volts core; struct volts mm; + struct volts gpu; + struct volts eve; + struct volts iva; }; extern struct prcm_regs const **prcm; -- cgit v1.1 From 3332b244214d63dcf347fefb700fd71becb4b46e Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 03:19:30 +0000 Subject: ARM: DRA7xx: clocks: Fixing i2c_init for PMIC In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 1 + arch/arm/cpu/armv7/omap-common/hwinit-common.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index eda3451..6c8226d 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -730,6 +730,7 @@ void prcm_init(void) case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: enable_basic_clocks(); + timer_init(); scale_vcores(*omap_vcores); setup_dplls(); #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 0776d5c..5df116e 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -166,8 +166,6 @@ void s_init(void) #endif prcm_init(); #ifdef CONFIG_SPL_BUILD - timer_init(); - /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); #endif -- cgit v1.1 From 18c9d55ac611784d161440bb9f127e372e132856 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 30 May 2013 03:19:31 +0000 Subject: ARM: OMAP5: DRA7xx: support class 0 optimized voltages DRA752 now uses AVS Class 0 voltages which are voltages in efuse. This means that we can now use the optimized voltages which are stored as mV values in efuse and program PMIC accordingly. This allows us to go with higher OPP as needed in the system without the need for implementing complex AVS logic. Signed-off-by: Nishanth Menon Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 58 ++++++++++++++++++++------ arch/arm/cpu/armv7/omap5/hw_data.c | 10 +++++ arch/arm/include/asm/arch-omap5/clock.h | 30 +++++++++++++ arch/arm/include/asm/omap_common.h | 11 +++++ 4 files changed, 97 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 6c8226d..9c75c13 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -521,6 +521,38 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) gpio_direction_output(pmic->gpio, 1); } +static u32 optimize_vcore_voltage(struct volts const *v) +{ + u32 val; + if (!v->value) + return 0; + if (!v->efuse.reg) + return v->value; + + switch (v->efuse.reg_bits) { + case 16: + val = readw(v->efuse.reg); + break; + case 32: + val = readl(v->efuse.reg); + break; + default: + printf("Error: efuse 0x%08x bits=%d unknown\n", + v->efuse.reg, v->efuse.reg_bits); + return v->value; + } + + if (!val) { + printf("Error: efuse 0x%08x bits=%d val=0, using %d\n", + v->efuse.reg, v->efuse.reg_bits, v->value); + return v->value; + } + + debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n", + __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val); + return val; +} + /* * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva * We set the maximum voltages allowed here because Smart-Reflex is not @@ -529,11 +561,13 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) */ void scale_vcores(struct vcores_data const *vcores) { - do_scale_vcore(vcores->core.addr, vcores->core.value, - vcores->core.pmic); + u32 val; + + val = optimize_vcore_voltage(&vcores->core); + do_scale_vcore(vcores->core.addr, val, vcores->core.pmic); - do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, - vcores->mpu.pmic); + val = optimize_vcore_voltage(&vcores->mpu); + do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic); /* Configure MPU ABB LDO after scale */ abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2, @@ -544,17 +578,17 @@ void scale_vcores(struct vcores_data const *vcores) OMAP_ABB_MPU_TXDONE_MASK, OMAP_ABB_FAST_OPP); - do_scale_vcore(vcores->mm.addr, vcores->mm.value, - vcores->mm.pmic); + val = optimize_vcore_voltage(&vcores->mm); + do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic); - do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, - vcores->gpu.pmic); + val = optimize_vcore_voltage(&vcores->gpu); + do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic); - do_scale_vcore(vcores->eve.addr, vcores->eve.value, - vcores->eve.pmic); + val = optimize_vcore_voltage(&vcores->eve); + do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic); - do_scale_vcore(vcores->iva.addr, vcores->iva.value, - vcores->iva.pmic); + val = optimize_vcore_voltage(&vcores->iva); + do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic); if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 90274a0..bddcaed 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -338,22 +338,32 @@ struct vcores_data omap5430_volts_es2 = { struct vcores_data dra752_volts = { .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, .mpu.pmic = &tps659038, .eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, .eve.pmic = &tps659038, .gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, .gpu.pmic = &tps659038, .core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, .core.pmic = &tps659038, .iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, .iva.pmic = &tps659038, }; diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index f7ddd5f..6d02835 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -219,6 +219,36 @@ #define VDD_CORE_DRA752 1030 #define VDD_IVA_DRA752 1060 +/* Efuse register offsets for DRA7xx platform */ +#define DRA752_EFUSE_BASE 0x4A002000 +#define DRA752_EFUSE_REGBITS 16 +/* STD_FUSE_OPP_VMIN_IVA_2 */ +#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) +/* STD_FUSE_OPP_VMIN_IVA_3 */ +#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) +/* STD_FUSE_OPP_VMIN_IVA_4 */ +#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) +/* STD_FUSE_OPP_VMIN_DSPEVE_2 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) +/* STD_FUSE_OPP_VMIN_DSPEVE_3 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) +/* STD_FUSE_OPP_VMIN_DSPEVE_4 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) +/* STD_FUSE_OPP_VMIN_CORE_2 */ +#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) +/* STD_FUSE_OPP_VMIN_GPU_2 */ +#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) +/* STD_FUSE_OPP_VMIN_GPU_3 */ +#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) +/* STD_FUSE_OPP_VMIN_GPU_4 */ +#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) +/* STD_FUSE_OPP_VMIN_MPU_2 */ +#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) +/* STD_FUSE_OPP_VMIN_MPU_3 */ +#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) +/* STD_FUSE_OPP_VMIN_MPU_4 */ +#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 3b8bece..f51fccc 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -506,9 +506,20 @@ struct pmic_data { int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); }; +/** + * struct volts_efuse_data - efuse definition for voltage + * @reg: register address for efuse + * @reg_bits: Number of bits in a register address, mandatory. + */ +struct volts_efuse_data { + u32 reg; + u8 reg_bits; +}; + struct volts { u32 value; u32 addr; + struct volts_efuse_data efuse; struct pmic_data *pmic; }; -- cgit v1.1 From e9d6cd042d63d59a43dfe953d488cfbf1ece516c Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 03:19:32 +0000 Subject: ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx. Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap5/hwinit.c | 3 +++ arch/arm/include/asm/omap_common.h | 8 ++++++++ 2 files changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index afb7000..40dbf45 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -201,6 +201,9 @@ void srcomp_enable(void) u32 sysclk_ind = get_sys_clk_index(); u32 omap_rev = omap_revision(); + if (!is_omap54xx()) + return; + mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; div_factor = srcomp_parameters[sysclk_ind].divide_factor; diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index f51fccc..f33f28b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -597,6 +597,14 @@ static inline u32 omap_revision(void) extern u32 *const omap_si_rev; return *omap_si_rev; } + +#define OMAP54xx 0x54000000 + +static inline u8 is_omap54xx(void) +{ + extern u32 *const omap_si_rev; + return ((*omap_si_rev & 0xFF000000) == OMAP54xx); +} #endif /* -- cgit v1.1 From f9b814a8e99390d19628bc1b67c9567fc485d918 Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Thu, 30 May 2013 03:19:34 +0000 Subject: ARM: DRA7xx: Correct the SYS_CLK to 20MHZ The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/timer.c | 1 + arch/arm/include/asm/arch-omap4/clock.h | 4 ++++ arch/arm/include/asm/arch-omap5/clock.h | 8 ++++++++ 3 files changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 507f687..5926a5a 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -35,6 +35,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index f544edf..d7b61c2 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -214,6 +214,10 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 +/* Clock Defines */ +#define V_OSCK 38400000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + struct omap4_scrm_regs { u32 revision; /* 0x0000 */ u32 pad00[63]; diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 6d02835..86d4711 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -284,4 +284,12 @@ * into microsec and passing the value. */ #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 + +#ifdef CONFIG_DRA7XX +#define V_OSCK 20000000 /* Clock output from T2 */ +#else +#define V_OSCK 19200000 /* Clock output from T2 */ +#endif + +#define V_SCLK V_OSCK #endif /* _CLOCKS_OMAP5_H_ */ -- cgit v1.1 From 81ede187c3e4233c08ab30900e86f5e0ec2c4624 Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Thu, 30 May 2013 03:19:35 +0000 Subject: ARM: DRA7xx: Correct SRAM END address NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here. Signed-off-by: Sricharan R Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-omap5/omap.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 43a629f..06171d0 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -169,13 +169,14 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ +#ifdef CONFIG_DRA7XX +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ +#else #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ +#endif + /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 -- cgit v1.1 From a5d439c2d3a55df2718eae19fb128e498f4bef87 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Thu, 6 Jun 2013 05:04:32 +0000 Subject: mmc: omap_hsmmc: Update pbias programming Update pbias programming sequence for OMAP5 ES2.0/DRA7 Signed-off-by: Balaji T K Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-omap5/omap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 06171d0..bb6a757 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -106,9 +106,9 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 +#define SDCARD_BIAS_PWRDNZ (1 << 27) #define SDCARD_PWRDNZ (1 << 26) #define SDCARD_BIAS_HIZ_MODE (1 << 25) -#define SDCARD_BIAS_PWRDNZ (1 << 22) #define SDCARD_PBIASLITE_VMODE (1 << 21) #ifndef __ASSEMBLY__ -- cgit v1.1 From 7f36c88f64ee1affd4db78b2c2f4a616abceb84c Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 03:19:37 +0000 Subject: ARM: DRA7xx: Update pinmux data Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla Signed-off-by: Balaji T K --- arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h index 55e9de6..5f2b0f9 100644 --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -28,11 +28,14 @@ #include +#define FSC (1 << 19) +#define SSC (0 << 19) + #define IEN (1 << 18) #define IDIS (0 << 18) -#define PTU (3 << 16) -#define PTD (1 << 16) +#define PTU (1 << 17) +#define PTD (0 << 17) #define PEN (1 << 16) #define PDIS (0 << 16) -- cgit v1.1 From 97405d843ece2a53e67b801e02ee42005d26e172 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 03:19:38 +0000 Subject: ARM: DRA7xx: clocks: Update PLL values Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla Signed-off-by: Sricharan R --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 16 +++-- arch/arm/cpu/armv7/omap5/hw_data.c | 87 ++++++++++++++++---------- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/include/asm/arch-omap4/clock.h | 2 +- arch/arm/include/asm/arch-omap5/clock.h | 8 ++- arch/arm/include/asm/omap_common.h | 3 +- 6 files changed, 71 insertions(+), 46 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 9c75c13..ef23127 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -50,13 +50,12 @@ const u32 sys_clk_array[8] = { 12000000, /* 12 MHz */ - 13000000, /* 13 MHz */ + 20000000, /* 20 MHz */ 16800000, /* 16.8 MHz */ 19200000, /* 19.2 MHz */ 26000000, /* 26 MHz */ 27000000, /* 27 MHz */ 38400000, /* 38.4 MHz */ - 20000000, /* 20 MHz */ }; static inline u32 __get_sys_clk_index(void) @@ -75,13 +74,6 @@ static inline u32 __get_sys_clk_index(void) /* SYS_CLKSEL - 1 to match the dpll param array indices */ ind = (readl((*prcm)->cm_sys_clksel) & CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; - /* - * SYS_CLKSEL value for 20MHz is 0. This is introduced newly - * in DRA7XX socs. SYS_CLKSEL -1 will be greater than - * NUM_SYS_CLK. So considering the last 3 bits as the index - * for the dpll param array. - */ - ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK; } return ind; } @@ -441,6 +433,12 @@ static void setup_non_essential_dplls(void) params = get_abe_dpll_params(*dplls_data); #ifdef CONFIG_SYS_OMAP_ABE_SYSCK abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; + + if (omap_revision() == DRA752_ES1_0) + /* Select the sys clk for dpll_abe */ + clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel, + CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK, + CM_ABE_PLL_SYS_CLKSEL_SYSCLK2); #else abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; /* diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index bddcaed..44552c3 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -100,14 +100,13 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { }; static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { - {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ - {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ + {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; static const struct dpll_params @@ -133,15 +132,14 @@ static const struct dpll_params }; static const struct dpll_params - core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = { - {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */ - {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */ - {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */ + core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { + {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ + {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ + {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ + {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ + {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */ - {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */ + {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ }; static const struct dpll_params @@ -187,14 +185,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { }; static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { - {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ + {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ + {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ - {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */ + {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ }; static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { @@ -207,6 +204,16 @@ static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { + {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + /* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { @@ -224,26 +231,36 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = { 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 }; +/* ABE M & N values with sysclk2(22.5792 MHz) as input */ +static const struct dpll_params + abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ - {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ }; -static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = { - {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ +static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { + {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ - {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ + {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; struct dplls omap5_dplls_es1 = { @@ -276,10 +293,12 @@ struct dplls omap5_dplls_es2 = { struct dplls dra7xx_dplls = { .mpu = mpu_dpll_params_1ghz, - .core = core_dpll_params_2128mhz_ddr532_dra7xx, + .core = core_dpll_params_2128mhz_dra7xx, .per = per_dpll_params_768mhz_dra7xx, + .abe = abe_dpll_params_sysclk2_361267khz, + .iva = iva_dpll_params_2330mhz_dra7xx, .usb = usb_dpll_params_1920mhz, - .ddr = ddr_dpll_params_1066mhz, + .ddr = ddr_dpll_params_2128mhz, }; struct pmic_data palmas = { diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index f3b3155..b7c2f98 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -951,6 +951,7 @@ struct prcm_regs const dra7xx_prcm = { /* l4 wkup regs */ .cm_abe_pll_ref_clksel = 0x4ae0610c, .cm_sys_clksel = 0x4ae06110, + .cm_abe_pll_sys_clksel = 0x4ae06118, .cm_wkup_clkstctrl = 0x4ae07800, .cm_wkup_l4wkup_clkctrl = 0x4ae07820, .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index d7b61c2..d14d8fb 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -76,7 +76,7 @@ #define CM_CLKSEL_DCC_EN_MASK (1 << 22) /* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 /* CM_CLKSEL_CORE */ #define CLKSEL_CORE_SHIFT 0 diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 86d4711..1affa4f 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -81,7 +81,7 @@ #define CM_CLKSEL_DCC_EN_MASK (1 << 22) /* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 /* CM_CLKSEL_CORE */ #define CLKSEL_CORE_SHIFT 0 @@ -98,6 +98,12 @@ #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 +/* CM_CLKSEL_ABE_PLL_SYS */ +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 + /* CM_BYPCLK_DPLL_IVA */ #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index f33f28b..d5daa27 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -29,7 +29,7 @@ #include -#define NUM_SYS_CLKS 8 +#define NUM_SYS_CLKS 7 struct prcm_regs { /* cm1.ckgen */ @@ -303,6 +303,7 @@ struct prcm_regs { /* l4 wkup regs */ u32 cm_abe_pll_ref_clksel; u32 cm_sys_clksel; + u32 cm_abe_pll_sys_clksel; u32 cm_wkup_clkstctrl; u32 cm_wkup_l4wkup_clkctrl; u32 cm_wkup_wdtimer1_clkctrl; -- cgit v1.1 From 92b0482c17acf92f94ac74fd8536fd95d5b64b5e Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Thu, 30 May 2013 03:19:39 +0000 Subject: ARM: DRA7xx: EMIF: Change settings required for EVM board DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/emif-common.c | 26 +++- arch/arm/cpu/armv7/omap5/hw_data.c | 21 +++- arch/arm/cpu/armv7/omap5/hwinit.c | 19 +-- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/cpu/armv7/omap5/sdram.c | 170 +++++++++++++++++++++++++-- arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/emif.h | 12 +- arch/arm/include/asm/omap_common.h | 1 + 8 files changed, 220 insertions(+), 31 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 8823967..652e5a7 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -209,7 +209,8 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - if (omap_revision() >= OMAP5430_ES1_0) { + if ((omap_revision() >= OMAP5430_ES1_0) || + (omap_revision() == DRA752_ES1_0)) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -263,6 +264,18 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs) __udelay(130); } +static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + config_data_eye_leveling_samples(base); + + writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); + writel(regs->sdram_config, &emif->emif_sdram_config); +} + static void ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -273,6 +286,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) * defined, contents of mode Registers must be fully initialized. * H/W takes care of this initialization */ + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); writel(regs->sdram_config_init, &emif->emif_sdram_config); writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); @@ -290,7 +304,10 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); - ddr3_leveling(base, regs); + if (omap_revision() == DRA752_ES1_0) + ddr3_sw_leveling(base, regs); + else + ddr3_leveling(base, regs); } #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS @@ -1078,7 +1095,10 @@ static void do_sdram_init(u32 base) if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { set_lpmode_selfrefresh(base); emif_reset_phy(base); - ddr3_leveling(base, regs); + if (omap_revision() == DRA752_ES1_0) + ddr3_sw_leveling(base, regs); + else + ddr3_leveling(base, regs); } /* Write to the shadow registers */ diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 44552c3..56cf1f8 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -602,6 +602,17 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = { .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, }; +const struct ctrl_ioregs ioregs_dra7xx_es1 = { + .ctrl_ddrch = 0x40404040, + .ctrl_lpddr2ch = 0x40404040, + .ctrl_ddr3ch = 0x80808080, + .ctrl_ddrio_0 = 0xbae8c631, + .ctrl_ddrio_1 = 0xb46318d8, + .ctrl_ddrio_2 = 0x84210000, + .ctrl_emif_sdram_config_ext = 0xb2c00000, + .ctrl_ddr_ctrl_ext_0 = 0xA2000000, +}; + void hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -644,14 +655,16 @@ void get_ioregs(const struct ctrl_ioregs **regs) case OMAP5430_ES1_0: case OMAP5430_ES2_0: *regs = &ioregs_omap5430; - break; + break; case OMAP5432_ES1_0: *regs = &ioregs_omap5432_es1; - break; + break; case OMAP5432_ES2_0: - case DRA752_ES1_0: *regs = &ioregs_omap5432_es2; - break; + break; + case DRA752_ES1_0: + *regs = &ioregs_dra7xx_es1; + break; default: printf("\n INVALID OMAP REVISION "); diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 40dbf45..daf124e 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -100,16 +100,21 @@ static void io_settings_ddr3(void) writel(ioregs->ctrl_emif_sdram_config_ext, (*ctrl)->control_emif2_sdram_config_ext); - /* Disable DLL select */ - io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) + if (is_omap54xx()) { + /* Disable DLL select */ + io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) & 0xFFEFFFFF); - writel(io_settings, - (*ctrl)->control_port_emif1_sdram_config); + writel(io_settings, + (*ctrl)->control_port_emif1_sdram_config); - io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) + io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) & 0xFFEFFFFF); - writel(io_settings, - (*ctrl)->control_port_emif2_sdram_config); + writel(io_settings, + (*ctrl)->control_port_emif2_sdram_config); + } else { + writel(ioregs->ctrl_ddr_ctrl_ext_0, + (*ctrl)->control_ddr_control_ext_0); + } } /* diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index b7c2f98..5a7370c 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -439,6 +439,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_east_side = 0x4A002E7C, .control_srcomp_west_side = 0x4A002E80, .control_srcomp_code_latch = 0x4A002E84, + .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 6b461e4..1b445a6 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -108,6 +108,7 @@ const struct emif_regs emif_regs_266_mhz_2cs = { const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { .sdram_config_init = 0x61851B32, .sdram_config = 0x61851B32, + .sdram_config2 = 0x0, .ref_ctrl = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, @@ -131,6 +132,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { .sdram_config_init = 0x61851B32, .sdram_config = 0x61851B32, + .sdram_config2 = 0x0, .ref_ctrl = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, @@ -151,6 +153,54 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { .emif_rd_wr_exec_thresh = 0x40000305 }; +const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { + .sdram_config_init = 0x61851ab2, + .sdram_config = 0x61851ab2, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0E20400A, + .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_3 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_4 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0020400A, + .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_3 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_4 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_5 = 0x009D009D, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, @@ -159,11 +209,39 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .is_ma_present = 0x1 }; -const struct dmm_lisa_map_regs lisa_map_512M_x_1 = { +/* + * DRA752 EVM board has 1.5 GB of memory + * EMIF1 --> 2Gb * 2 = 512MB + * EMIF2 --> 2Gb * 4 = 1GB + * so mapping 1GB interleaved and 512MB non-interleaved + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x80640300, + .dmm_lisa_map_2 = 0xC0500220, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +/* + * DRA752 EVM EMIF1 ONLY CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x0, - .dmm_lisa_map_3 = 0x80500100, + .dmm_lisa_map_2 = 0x80500100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +/* + * DRA752 EVM EMIF2 ONLY CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80600200, + .dmm_lisa_map_3 = 0xFF020100, .is_ma_present = 0x1 }; @@ -180,9 +258,20 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_532_mhz_2cs_es2; break; case OMAP5432_ES2_0: + *regs = &emif_regs_ddr3_532_mhz_1cs_es2; + break; case DRA752_ES1_0: + switch (emif_nr) { + case 1: + *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; + break; + case 2: + *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1; + break; + } + break; default: - *regs = &emif_regs_ddr3_532_mhz_1cs_es2; + *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } } @@ -201,7 +290,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs break; case DRA752_ES1_0: default: - *dmm_lisa_regs = &lisa_map_512M_x_1; + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; } } @@ -252,7 +341,8 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000077 + 0x00000077, + 0x0 }; const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { @@ -274,7 +364,8 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000057 + 0x00000057, + 0x0 }; const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { @@ -296,7 +387,56 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000057 + 0x00000057, + 0x0 +}; + +const u32 +dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x009E009E, + 0x002E002E, + 0x002E002E, + 0x002E002E, + 0x002E002E, + 0x002E002E, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x0, + 0x600020, + 0x40010080, + 0x8102040 +}; + +const u32 +dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x009D009D, + 0x002D002D, + 0x002D002D, + 0x002D002D, + 0x002D002D, + 0x002D002D, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x0, + 0x600020, + 0x40010080, + 0x8102040 }; const struct lpddr2_mr_regs mr_regs = { @@ -307,7 +447,7 @@ const struct lpddr2_mr_regs mr_regs = { .mr16 = MR16_REF_FULL_ARRAY }; -static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) +static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs) { switch (omap_revision()) { case OMAP5430_ES1_0: @@ -318,7 +458,14 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) *regs = ddr3_ext_phy_ctrl_const_base_es1; break; case OMAP5432_ES2_0: + *regs = ddr3_ext_phy_ctrl_const_base_es2; + break; case DRA752_ES1_0: + if (emif_nr == 1) + *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; + else + *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2; + break; default: *regs = ddr3_ext_phy_ctrl_const_base_es2; @@ -334,9 +481,12 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) { u32 *ext_phy_ctrl_base = 0; u32 *emif_ext_phy_ctrl_base = 0; + u32 emif_nr; const u32 *ext_phy_ctrl_const_regs; u32 i = 0; + emif_nr = (base == EMIF1_BASE) ? 1 : 2; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); @@ -353,7 +503,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) * external phy 6-24 registers do not change with * ddr frequency */ - emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs); + emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs); for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index bb6a757..817c1ff 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -221,6 +221,7 @@ struct ctrl_ioregs { u32 ctrl_ddrio_1; u32 ctrl_ddrio_2; u32 ctrl_emif_sdram_config_ext; + u32 ctrl_ddr_ctrl_ext_0; }; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 5f11d7b..1b94a99 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -581,7 +581,7 @@ (0xFF << EMIF_SYS_ADDR_SHIFT)) #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 -#define EMIF_EXT_PHY_CTRL_CONST_REG 0x13 +#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14 /* Reg mapping structure */ struct emif_reg_struct { @@ -855,13 +855,10 @@ struct dmm_lisa_map_regs { #define DPD_ENABLE 1 /* Maximum delay before Low Power Modes */ -#ifndef CONFIG_OMAP54XX -#define REG_CS_TIM 0xF -#else #define REG_CS_TIM 0x0 -#endif -#define REG_SR_TIM 0xF -#define REG_PD_TIM 0xF +#define REG_SR_TIM 0x0 +#define REG_PD_TIM 0x0 + /* EMIF_PWR_MGMT_CTRL register */ #define EMIF_PWR_MGMT_CTRL (\ @@ -1113,6 +1110,7 @@ struct emif_regs { u32 freq; u32 sdram_config_init; u32 sdram_config; + u32 sdram_config2; u32 ref_ctrl; u32 sdram_tim1; u32 sdram_tim2; diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index d5daa27..fa2963e 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -401,6 +401,7 @@ struct omap_sys_ctrl_regs { u32 control_ddrio_0; u32 control_ddrio_1; u32 control_ddrio_2; + u32 control_ddr_control_ext_0; u32 control_lpddr2io1_0; u32 control_lpddr2io1_1; u32 control_lpddr2io1_2; -- cgit v1.1 From 7f5eef93af92ed9efed7867d24b03fd6056a7404 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 4 Jun 2013 12:02:06 +0000 Subject: arm: Remove OMAP2420H4 and all omap24xx support The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini --- arch/arm/cpu/arm1136/start.S | 18 -- arch/arm/include/asm/arch-omap24xx/bits.h | 48 ----- arch/arm/include/asm/arch-omap24xx/clock.h | 112 ------------ arch/arm/include/asm/arch-omap24xx/i2c.h | 68 ------- arch/arm/include/asm/arch-omap24xx/mem.h | 156 ---------------- arch/arm/include/asm/arch-omap24xx/mux.h | 176 ------------------ arch/arm/include/asm/arch-omap24xx/omap2420.h | 236 ------------------------- arch/arm/include/asm/arch-omap24xx/sys_info.h | 82 --------- arch/arm/include/asm/arch-omap24xx/sys_proto.h | 54 ------ arch/arm/lib/cache.c | 2 +- 10 files changed, 1 insertion(+), 951 deletions(-) delete mode 100644 arch/arm/include/asm/arch-omap24xx/bits.h delete mode 100644 arch/arm/include/asm/arch-omap24xx/clock.h delete mode 100644 arch/arm/include/asm/arch-omap24xx/i2c.h delete mode 100644 arch/arm/include/asm/arch-omap24xx/mem.h delete mode 100644 arch/arm/include/asm/arch-omap24xx/mux.h delete mode 100644 arch/arm/include/asm/arch-omap24xx/omap2420.h delete mode 100644 arch/arm/include/asm/arch-omap24xx/sys_info.h delete mode 100644 arch/arm/include/asm/arch-omap24xx/sys_proto.h (limited to 'arch') diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index edf249d..a7e0c28 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -142,24 +142,6 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 -#ifdef CONFIG_OMAP2420H4 - /* Copy vectors to mask ROM indirect addr */ - adr r0, _start /* r0 <- current position of code */ - add r0, r0, #4 /* skip reset vector */ - mov r2, #64 /* r2 <- size to copy */ - add r2, r0, r2 /* r2 <- source end address */ - mov r1, #SRAM_OFFSET0 /* build vect addr */ - mov r3, #SRAM_OFFSET1 - add r1, r1, r3 - mov r3, #SRAM_OFFSET2 - add r1, r1, r3 -next: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next /* loop until equal */ - bl cpy_clk_code /* put dpll adjust code behind vectors */ -#endif /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit diff --git a/arch/arm/include/asm/arch-omap24xx/bits.h b/arch/arm/include/asm/arch-omap24xx/bits.h deleted file mode 100644 index 8522335..0000000 --- a/arch/arm/include/asm/arch-omap24xx/bits.h +++ /dev/null @@ -1,48 +0,0 @@ -/* bits.h - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/clock.h b/arch/arm/include/asm/arch-omap24xx/clock.h deleted file mode 100644 index 2e92569..0000000 --- a/arch/arm/include/asm/arch-omap24xx/clock.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_CLOCKS_H_ -#define _OMAP24XX_CLOCKS_H_ - -#define COMMIT_DIVIDERS 0x1 - -#define MODE_BYPASS_FAST 0x2 -#define APLL_LOCK 0xc -#ifdef CONFIG_APTIX -#define DPLL_LOCK 0x1 /* stay in bypass mode */ -#else -#define DPLL_LOCK 0x3 /* DPLL lock */ -#endif - -/****************************************************************************; -; PRCM Scheme II -; -; Enable clocks and DPLL for: -; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 -; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] -; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] -; DSPI=100 6 CM_CLKSEL_DSP[6:5] -; DSP_S bypass CM_CLKSEL_DSP[7] -; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] -; IVAF=100 auto -; IVAI auto -; IVA_MPU auto -; IVA_S bypass CM_CLKSEL_DSP[13] -; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] -; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=100 auto -; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] -; L4=100Mhz 6 -; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define II_DPLL_OUT_X2 0x2 /* x2 core out */ -#define II_MPU_DIV 0x2 /* mpu = core/2 */ -#define II_DSP_DIV 0x343 /* dsp & iva divider */ -#define II_GFX_DIV 0x2 -#define II_BUS_DIV 0x04601026 -#define II_DPLL_300 0x01832100 - -/****************************************************************************; -; PRCM Scheme III -; -; Enable clocks and DPLL for: -; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 -; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] -; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] -; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] -; DSP_S ACTIVATED CM_CLKSEL_DSP[7] -; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] -; IVAF=88.67 auto -; IVAI auto -; IVA_MPU auto -; IVA_S ACTIVATED CM_CLKSEL_DSP[13] -; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: -; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=88.67 auto -; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] -; L4=66.5Mhz /8 -; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define III_DPLL_OUT_X2 0x2 /* x2 core out */ -#define III_MPU_DIV 0x2 /* mpu = core/2 */ -#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ -#define III_GFX_DIV 0x2 -#define III_BUS_DIV 0x08301044 -#define III_DPLL_266 0x01885500 - -/* set defaults for boot up */ -#ifdef PRCM_CONFIG_II -# define DPLL_OUT II_DPLL_OUT_X2 -# define MPU_DIV II_MPU_DIV -# define DSP_DIV II_DSP_DIV -# define GFX_DIV II_GFX_DIV -# define BUS_DIV II_BUS_DIV -# define DPLL_VAL II_DPLL_300 -#elif PRCM_CONFIG_III -# define DPLL_OUT III_DPLL_OUT_X2 -# define MPU_DIV III_MPU_DIV -# define DSP_DIV III_DSP_DIV -# define GFX_DIV III_GFX_DIV -# define BUS_DIV III_BUS_DIV -# define DPLL_VAL III_DPLL_266 -#endif - -/* lock delay time out */ -#define LDELAY 12000000 - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h deleted file mode 100644 index 6f64519..0000000 --- a/arch/arm/include/asm/arch-omap24xx/i2c.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_I2C_H_ -#define _OMAP24XX_I2C_H_ - -#define I2C_BASE1 0x48070000 -#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -struct i2c { - unsigned short rev; /* 0x00 */ - unsigned short res1; - unsigned short ie; /* 0x04 */ - unsigned short res2; - unsigned short stat; /* 0x08 */ - unsigned short res3; - unsigned short iv; /* 0x0C */ - unsigned short res4; - unsigned short syss; /* 0x10 */ - unsigned short res4p1; - unsigned short buf; /* 0x14 */ - unsigned short res5; - unsigned short cnt; /* 0x18 */ - unsigned short res6; - unsigned short data; /* 0x1C */ - unsigned short res7; - unsigned short sysc; /* 0x20 */ - unsigned short res8; - unsigned short con; /* 0x24 */ - unsigned short res9; - unsigned short oa; /* 0x28 */ - unsigned short res10; - unsigned short sa; /* 0x2C */ - unsigned short res11; - unsigned short psc; /* 0x30 */ - unsigned short res12; - unsigned short scll; /* 0x34 */ - unsigned short res13; - unsigned short sclh; /* 0x38 */ - unsigned short res14; - unsigned short systest; /* 0x3c */ - unsigned short res15; -}; - -#define I2C_BUS_MAX 2 - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/mem.h b/arch/arm/include/asm/arch-omap24xx/mem.h deleted file mode 100644 index 42e8ab2..0000000 --- a/arch/arm/include/asm/arch-omap24xx/mem.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_MEM_H_ -#define _OMAP24XX_MEM_H_ - -#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ -/* struct's for holding data tables for current boards, they are getting used - early in init when NO global access are there */ -struct sdrc_data_s { - u32 sdrc_sharing; - u32 sdrc_mdcfg_0_ddr; - u32 sdrc_mdcfg_0_sdr; - u32 sdrc_actim_ctrla_0; - u32 sdrc_actim_ctrlb_0; - u32 sdrc_rfr_ctrl; - u32 sdrc_mr_0_ddr; - u32 sdrc_mr_0_sdr; - u32 sdrc_dllab_ctrl; -} /*__attribute__ ((packed))*/; -typedef struct sdrc_data_s sdrc_data_t; - -typedef enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -} mem_t; - -#endif - -/* Slower full frequency range default timings for x32 operation*/ -#define H4_2420_SDRC_SHARING 0x00000100 -#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ -#define H4_2420_SDRC_MR_0_SDR 0x00000031 -#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ -#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ -#define H4_2420_SDRC_MR_0_DDR 0x00000032 - -#define H4_2422_SDRC_SHARING 0x00004b00 -#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */ -#define H4_2422_SDRC_MR_0_DDR 0x00000032 - -/* ES1 work around timings */ -#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ -#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 -#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ - -/* optimized timings good for current shipping parts */ -#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 -#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e -#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ -#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ -#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 -#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 -#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/ -#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */ - -#ifdef PRCM_CONFIG_II -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz -#elif PRCM_CONFIG_III -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz -#endif - - -/* GPMC settings */ -#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ -# ifdef CONFIG_SYS_NAND_BOOT -# define H4_24XX_GPMC_CONFIG1_0 0x0 -# define H4_24XX_GPMC_CONFIG2_0 0x00141400 -# define H4_24XX_GPMC_CONFIG3_0 0x00141400 -# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -# else /* else NOR */ -# define H4_24XX_GPMC_CONFIG1_0 0x3 -# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 -# define H4_24XX_GPMC_CONFIG3_0 0x00050502 -# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 -# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -# endif /* endif CONFIG_SYS_NAND_BOOT */ -# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) -# define H4_24XX_GPMC_CONFIG1_1 0x00011000 -# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 -# define H4_24XX_GPMC_CONFIG3_1 0x00080802 -# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F -# define H4_24XX_GPMC_CONFIG6_1 0x000003C2 -# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif /* endif PRCM_CONFIG_II */ - -#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ -# ifdef CONFIG_SYS_NAND_BOOT -# define H4_24XX_GPMC_CONFIG1_0 0x0 -# define H4_24XX_GPMC_CONFIG2_0 0x00141400 -# define H4_24XX_GPMC_CONFIG3_0 0x00141400 -# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -# else /* NOR boot */ -# define H4_24XX_GPMC_CONFIG1_0 0x3 -# define H4_24XX_GPMC_CONFIG2_0 0x00151501 -# define H4_24XX_GPMC_CONFIG3_0 0x00060602 -# define H4_24XX_GPMC_CONFIG4_0 0x10081008 -# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -# define H4_24XX_GPMC_CONFIG6_0 0x000004c4 -# endif /* endif CONFIG_SYS_NAND_BOOT */ -# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) -# define H4_24XX_GPMC_CONFIG1_1 0x00011000 -# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 -# define H4_24XX_GPMC_CONFIG3_1 0x00080803 -# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F -# define H4_24XX_GPMC_CONFIG6_1 0x000004C4 -# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif /* endif CONFIG_SYS_PRCM_III */ - -#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap24xx/mux.h b/arch/arm/include/asm/arch-omap24xx/mux.h deleted file mode 100644 index 4fdb9c6..0000000 --- a/arch/arm/include/asm/arch-omap24xx/mux.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP2420_MUX_H_ -#define _OMAP2420_MUX_H_ - -#ifndef __ASSEMBLY__ -typedef unsigned char uint8; -typedef unsigned int uint32; - -void muxSetupSDRC(void); -void muxSetupGPMC(void); -void muxSetupUsb0(void); -void muxSetupUsbHost(void); -void muxSetupUart3(void); -void muxSetupI2C1(void); -void muxSetupUART1(void); -void muxSetupLCD(void); -void muxSetupCamera(void); -void muxSetupMMCSD(void) ; -void muxSetupTouchScreen(void) ; -void muxSetupHDQ(void); -#endif - -#define USB_OTG_CTRL ((volatile uint32 *)0x4805E30C) - -/* Pin Muxing registers used for HDQ (Smart battery) */ -#define CONTROL_PADCONF_HDQ_SIO ((volatile unsigned char *)0x48000115) - -/* Pin Muxing registers used for GPMC */ -#define CONTROL_PADCONF_GPMC_D2_BYTE0 ((volatile unsigned char *)0x48000088) -#define CONTROL_PADCONF_GPMC_D2_BYTE1 ((volatile unsigned char *)0x48000089) -#define CONTROL_PADCONF_GPMC_D2_BYTE2 ((volatile unsigned char *)0x4800008A) -#define CONTROL_PADCONF_GPMC_D2_BYTE3 ((volatile unsigned char *)0x4800008B) - -#define CONTROL_PADCONF_GPMC_NCS0_BYTE0 ((volatile unsigned char *)0x4800008C) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE4 (0x48000090) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE5 (0x48000091) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE6 (0x48000092) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE7 (0x48000093) - -/* Pin Muxing registers used for SDRC */ -#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0) -#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1) -#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2) -#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3) - -#define CONTROL_PADCONF_SDRC_A14_BYTE0 ((volatile unsigned char *)0x48000030) -#define CONTROL_PADCONF_SDRC_A14_BYTE1 ((volatile unsigned char *)0x48000031) -#define CONTROL_PADCONF_SDRC_A14_BYTE2 ((volatile unsigned char *)0x48000032) -#define CONTROL_PADCONF_SDRC_A14_BYTE3 ((volatile unsigned char *)0x48000033) - -/* Pin Muxing registers used for Touch Screen (SPI) */ -#define CONTROL_PADCONF_SPI1_CLK ((volatile unsigned char *)0x480000FF) -#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100) -#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101) -#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102) -#define CONTROL_PADCONF_SPI1_NCS1 (0x48000103) - -#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B) - -/* Pin Muxing registers used for MMCSD */ -#define CONTROL_PADCONF_MMC_CLKI ((volatile unsigned char *)0x480000FE) -#define CONTROL_PADCONF_MMC_CLKO ((volatile unsigned char *)0x480000F3) -#define CONTROL_PADCONF_MMC_CMD ((volatile unsigned char *)0x480000F4) -#define CONTROL_PADCONF_MMC_DAT0 ((volatile unsigned char *)0x480000F5) -#define CONTROL_PADCONF_MMC_DAT1 ((volatile unsigned char *)0x480000F6) -#define CONTROL_PADCONF_MMC_DAT2 ((volatile unsigned char *)0x480000F7) -#define CONTROL_PADCONF_MMC_DAT3 ((volatile unsigned char *)0x480000F8) -#define CONTROL_PADCONF_MMC_DAT_DIR0 ((volatile unsigned char *)0x480000F9) -#define CONTROL_PADCONF_MMC_DAT_DIR1 ((volatile unsigned char *)0x480000FA) -#define CONTROL_PADCONF_MMC_DAT_DIR2 ((volatile unsigned char *)0x480000FB) -#define CONTROL_PADCONF_MMC_DAT_DIR3 ((volatile unsigned char *)0x480000FC) -#define CONTROL_PADCONF_MMC_CMD_DIR ((volatile unsigned char *)0x480000FD) - -#define CONTROL_PADCONF_SDRC_A14 ((volatile unsigned char *)0x48000030) -#define CONTROL_PADCONF_SDRC_A13 ((volatile unsigned char *)0x48000031) - -/* Pin Muxing registers used for CAMERA */ -#define CONTROL_PADCONF_SYS_NRESWARM ((volatile unsigned char *)0x4800012B) - -#define CONTROL_PADCONF_CAM_XCLK ((volatile unsigned char *)0x480000DC) -#define CONTROL_PADCONF_CAM_LCLK ((volatile unsigned char *)0x480000DB) -#define CONTROL_PADCONF_CAM_VS ((volatile unsigned char *)0x480000DA) -#define CONTROL_PADCONF_CAM_HS ((volatile unsigned char *)0x480000D9) -#define CONTROL_PADCONF_CAM_D0 ((volatile unsigned char *)0x480000D8) -#define CONTROL_PADCONF_CAM_D1 ((volatile unsigned char *)0x480000D7) -#define CONTROL_PADCONF_CAM_D2 ((volatile unsigned char *)0x480000D6) -#define CONTROL_PADCONF_CAM_D3 ((volatile unsigned char *)0x480000D5) -#define CONTROL_PADCONF_CAM_D4 ((volatile unsigned char *)0x480000D4) -#define CONTROL_PADCONF_CAM_D5 ((volatile unsigned char *)0x480000D3) -#define CONTROL_PADCONF_CAM_D6 ((volatile unsigned char *)0x480000D2) -#define CONTROL_PADCONF_CAM_D7 ((volatile unsigned char *)0x480000D1) -#define CONTROL_PADCONF_CAM_D8 ((volatile unsigned char *)0x480000D0) -#define CONTROL_PADCONF_CAM_D9 ((volatile unsigned char *)0x480000CF) - -/* Pin Muxing registers used for LCD */ -#define CONTROL_PADCONF_DSS_D0 ((volatile unsigned char *)0x480000B3) -#define CONTROL_PADCONF_DSS_D1 ((volatile unsigned char *)0x480000B4) -#define CONTROL_PADCONF_DSS_D2 ((volatile unsigned char *)0x480000B5) -#define CONTROL_PADCONF_DSS_D3 ((volatile unsigned char *)0x480000B6) -#define CONTROL_PADCONF_DSS_D4 ((volatile unsigned char *)0x480000B7) -#define CONTROL_PADCONF_DSS_D5 ((volatile unsigned char *)0x480000B8) -#define CONTROL_PADCONF_DSS_D6 ((volatile unsigned char *)0x480000B9) -#define CONTROL_PADCONF_DSS_D7 ((volatile unsigned char *)0x480000BA) -#define CONTROL_PADCONF_DSS_D8 ((volatile unsigned char *)0x480000BB) -#define CONTROL_PADCONF_DSS_D9 ((volatile unsigned char *)0x480000BC) -#define CONTROL_PADCONF_DSS_D10 ((volatile unsigned char *)0x480000BD) -#define CONTROL_PADCONF_DSS_D11 ((volatile unsigned char *)0x480000BE) -#define CONTROL_PADCONF_DSS_D12 ((volatile unsigned char *)0x480000BF) -#define CONTROL_PADCONF_DSS_D13 ((volatile unsigned char *)0x480000C0) -#define CONTROL_PADCONF_DSS_D14 ((volatile unsigned char *)0x480000C1) -#define CONTROL_PADCONF_DSS_D15 ((volatile unsigned char *)0x480000C2) -#define CONTROL_PADCONF_DSS_D16 ((volatile unsigned char *)0x480000C3) -#define CONTROL_PADCONF_DSS_D17 ((volatile unsigned char *)0x480000C4) -#define CONTROL_PADCONF_DSS_PCLK ((volatile unsigned char *)0x480000CB) -#define CONTROL_PADCONF_DSS_VSYNC ((volatile unsigned char *)0x480000CC) -#define CONTROL_PADCONF_DSS_HSYNC ((volatile unsigned char *)0x480000CD) -#define CONTROL_PADCONF_DSS_ACBIAS ((volatile unsigned char *)0x480000CE) - -/* Pin Muxing registers used for UART1 */ -#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) -#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) -#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) -#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) - -/* Pin Muxing registers used for I2C1 */ -#define CONTROL_PADCONF_I2C1_SCL ((volatile unsigned char *)0x48000111) -#define CONTROL_PADCONF_I2C1_SDA ((volatile unsigned char *)0x48000112) - -/* Pin Muxing registres used for USB0. */ -#define CONTROL_PADCONF_USB0_PUEN ((volatile uint8 *)0x4800011D) -#define CONTROL_PADCONF_USB0_VP ((volatile uint8 *)0x4800011E) -#define CONTROL_PADCONF_USB0_VM ((volatile uint8 *)0x4800011F) -#define CONTROL_PADCONF_USB0_RCV ((volatile uint8 *)0x48000120) -#define CONTROL_PADCONF_USB0_TXEN ((volatile uint8 *)0x48000121) -#define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122) -#define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123) - -/* Pin Muxing registres used for USB1. */ -#define CONTROL_PADCONF_USB1_RCV (0x480000EB) -#define CONTROL_PADCONF_USB1_TXEN (0x480000EC) - -/* Pin Muxing registers used for UART3/IRDA */ -#define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118) -#define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119) - -/* Pin Muxing registers used for GPIO */ -#define CONTROL_PADCONF_GPIO69 (0x480000ED) -#define CONTROL_PADCONF_GPIO70 (0x480000EE) -#define CONTROL_PADCONF_GPIO102 (0x48000116) -#define CONTROL_PADCONF_GPIO103 (0x48000117) -#define CONTROL_PADCONF_GPIO104 (0x48000118) -#define CONTROL_PADCONF_GPIO105 (0x48000119) - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h deleted file mode 100644 index 5724f5d..0000000 --- a/arch/arm/include/asm/arch-omap24xx/omap2420.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2420_SYS_H_ -#define _OMAP2420_SYS_H_ - -#include - -/* - * 2420 specific Section - */ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 -/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 - -/* CONTROL */ -#define OMAP2420_CTRL_BASE (0x48000000) -#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) - -/* device type */ -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* TAP information */ -#define OMAP2420_TAP_BASE (0x48014000) -#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) -#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) - -/* GPMC */ -#define OMAP2420_GPMC_BASE (0x6800A000) -#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) -#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) -#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) -#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) -#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) -#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) -#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) -#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) -#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) -#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) -#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) -#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) -#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) -#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) -#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) -#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) - -/* SMS */ -#define OMAP2420_SMS_BASE 0x68008000 -#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) -#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0) -# define BURSTCOMPLETE_GROUP7 BIT31 - -/* SDRC */ -#define OMAP2420_SDRC_BASE 0x68009000 -#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) -#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) -#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) -#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) -#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) -#define OMAP2420_SDRC_CS0 0x80000000 -#define OMAP2420_SDRC_CS1 0xA0000000 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2420_UART1 0x4806A000 -#define OMAP2420_UART2 0x4806C000 -#define OMAP2420_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP2420_GPT1 0x48028000 -#define OMAP2420_GPT2 0x4802A000 -#define OMAP2420_GPT3 0x48078000 -#define OMAP2420_GPT4 0x4807A000 -#define OMAP2420_GPT5 0x4807C000 -#define OMAP2420_GPT6 0x4807E000 -#define OMAP2420_GPT7 0x48080000 -#define OMAP2420_GPT8 0x48082000 -#define OMAP2420_GPT9 0x48084000 -#define OMAP2420_GPT10 0x48086000 -#define OMAP2420_GPT11 0x48088000 -#define OMAP2420_GPT12 0x4808A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x48020000 -#define WD2_BASE 0x48022000 -#define WD3_BASE 0x48024000 -#define WD4_BASE 0x48026000 -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP2420_CM_BASE 0x48008000 -#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) -#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) -#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) -#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) - -/* - * H4 specific Section - */ - -/* - * The 2420's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP2420H4) -/* GPMC */ -#ifdef CONFIG_VIRTIO_A /* Pre version B */ -# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x04000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#else -# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x04000000 /* debug board */ -# define H4_CS2_BASE 0x0C000000 /* wifi board */ -#endif - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) -#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) -#endif /* endif CONFIG_2420H4 */ - -/* Common */ -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/sys_info.h b/arch/arm/include/asm/arch-omap24xx/sys_info.h deleted file mode 100644 index 53c231a..0000000 --- a/arch/arm/include/asm/arch-omap24xx/sys_info.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_SYS_INFO_H_ -#define _OMAP24XX_SYS_INFO_H_ - -typedef struct h4_system_data { - /* base board info */ - u32 base_b_rev; /* rev from base board i2c */ - /* cpu board info */ - u32 cpu_b_rev; /* rev from cpu board i2c */ - u32 cpu_b_mux; /* mux type on daughter board */ - u32 cpu_b_ddr_type; /* mem type */ - u32 cpu_b_ddr_speed; /* ddr speed rating */ - u32 cpu_b_switches; /* boot ctrl switch settings */ - /* cpu info */ - u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ - u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ -} h4_sys_data; - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_2420 0x2420 -#define CPU_2422 0x2422 /* 2420 + 64M stacked */ -#define CPU_2423 0x2423 /* 2420 + 96M stacked */ - -#define CPU_2422_ES1 1 -#define CPU_2422_ES2 2 -#define CPU_2420_ES1 1 -#define CPU_2420_ES2 2 -#define CPU_2420_2422_ES1 1 - -#define CPU_2420_CHIPID 0x0B5D9000 -#define CPU_24XX_ID_MASK 0x0FFFF000 -#define CPU_242X_REV_MASK 0xF0000000 -#define CPU_242X_PID_MASK 0x000F0000 - -#define BOARD_H4_MENELAUS 1 -#define BOARD_H4_SDP 2 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ - -#endif diff --git a/arch/arm/include/asm/arch-omap24xx/sys_proto.h b/arch/arm/include/asm/arch-omap24xx/sys_proto.h deleted file mode 100644 index 9d8e5b2..0000000 --- a/arch/arm/include/asm/arch-omap24xx/sys_proto.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_SYS_PROTO_H_ -#define _OMAP24XX_SYS_PROTO_H_ - -void prcm_init(void); -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32,u32); -void gpmc_init(void); - -void ether_init(void); -void watchdog_init(void); -void set_muxconf_regs(void); -void peripheral_enable(void); - -u32 get_cpu_type(void); -u32 get_cpu_rev(void); -u32 get_mem_type(void); -u32 get_sysboot_value(void); -u32 get_gpmc0_base(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); -u32 get_board_type(void); -void display_board_info(u32); -void update_mux(u32,u32); -u32 get_sdr_cs_size(u32 offset); - -u32 running_in_sdram(void); -u32 running_in_sram(void); -u32 running_in_flash(void); -u32 running_from_internal_boot(void); -u32 get_device_type(void); -#endif diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index b545fb7..8b1c8ed 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -27,7 +27,7 @@ void __flush_cache(unsigned long start, unsigned long size) { -#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136) +#if defined(CONFIG_ARM1136) void arm1136_cache_flush(void); arm1136_cache_flush(); -- cgit v1.1 From ee28edac4322602685ea12dc46edad1ec6b60487 Mon Sep 17 00:00:00 2001 From: Lubomir Popov Date: Wed, 15 May 2013 04:41:01 +0000 Subject: OMAP5: Enable access to auxclk registers auxclk0 and auxclk1 are utilized on some OMAP5 boards. Define the infrastructure needed for accessing them without using magic numbers. Also remove unrelated TPS62361 defines from clocks.h Signed-off-by: Lubomir Popov --- arch/arm/cpu/armv7/omap5/prcm-regs.c | 8 ++++++++ arch/arm/include/asm/arch-omap5/clock.h | 18 ++++++++++++++++++ arch/arm/include/asm/omap_common.h | 4 ++++ 3 files changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 5a7370c..e839ff5 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -308,6 +308,10 @@ struct prcm_regs const omap5_es1_prcm = { .prm_sldo_mpu_ctrl = 0x4ae07bd0, .prm_sldo_mm_setup = 0x4ae07bd4, .prm_sldo_mm_ctrl = 0x4ae07bd8, + + /* SCRM stuff, used by some boards */ + .scrm_auxclk0 = 0x4ae0a310, + .scrm_auxclk1 = 0x4ae0a314, }; struct omap_sys_ctrl_regs const omap5_ctrl = { @@ -751,6 +755,10 @@ struct prcm_regs const omap5_es2_prcm = { .prm_sldo_mm_ctrl = 0x4ae07cd8, .prm_abbldo_mpu_setup = 0x4ae07cdc, .prm_abbldo_mpu_ctrl = 0x4ae07ce0, + + /* SCRM stuff, used by some boards */ + .scrm_auxclk0 = 0x4ae0a310, + .scrm_auxclk1 = 0x4ae0a314, }; struct prcm_regs const dra7xx_prcm = { diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 1affa4f..4d2765d 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -281,6 +281,11 @@ #define TPS62361_BASE_VOLT_MV 500 #define TPS62361_VSEL0_GPIO 7 +/* Defines for DPLL setup */ +#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 +#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 +#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 + #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 @@ -298,4 +303,17 @@ #endif #define V_SCLK V_OSCK + +/* AUXCLKx reg fields */ +#define AUXCLK_ENABLE_MASK (1 << 8) +#define AUXCLK_SRCSELECT_SHIFT 1 +#define AUXCLK_SRCSELECT_MASK (3 << 1) +#define AUXCLK_CLKDIV_SHIFT 16 +#define AUXCLK_CLKDIV_MASK (0xF << 16) + +#define AUXCLK_SRCSELECT_SYS_CLK 0 +#define AUXCLK_SRCSELECT_CORE_DPLL 1 +#define AUXCLK_SRCSELECT_PER_DPLL 2 +#define AUXCLK_SRCSELECT_ALTERNATE 3 + #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index fa2963e..787e614 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -351,6 +351,10 @@ struct prcm_regs { u32 cm_l3init_usbphy_clkctrl; u32 cm_l4per_mcbsp4_clkctrl; u32 prm_vc_cfg_channel; + + /* SCRM stuff, used by some boards */ + u32 scrm_auxclk0; + u32 scrm_auxclk1; }; struct omap_sys_ctrl_regs { -- cgit v1.1 From 68cd4a4c9f4d7be8dc95796fb567f6b03faf9d97 Mon Sep 17 00:00:00 2001 From: "Vishwanathrao Badarkhe, Manish" Date: Wed, 29 May 2013 21:55:11 +0000 Subject: arm: da830: moved pinmux configurations to the arch tree Move pinmux configurations for the DA830 SoCs from board file to the arch tree so that it can be used for all da830 based devices. Also, avoids duplicate pinmuxing in case of NAND. Signed-off-by: Vishwanathrao Badarkhe, Manish Reviewed-by: Tom Rini Acked-by: Christian Riesch --- arch/arm/cpu/arm926ejs/davinci/Makefile | 1 + arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c | 151 ++++++++++++++++++++++++ arch/arm/include/asm/arch-davinci/pinmux_defs.h | 15 ++- 3 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index dec7bfb..bba4671 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_SOC_DM646X) += dm646x.o +COBJS-$(CONFIG_SOC_DA830) += da830_pinmux.o COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c new file mode 100644 index 0000000..d0c964a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c @@ -0,0 +1,151 @@ +/* + * Pinmux configurations for the DA830 SoCs + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +/* SPI0 pin muxer settings */ +const struct pinmux_config spi0_pins_base[] = { + { pinmux(7), 1, 3 }, /* SPI0_SOMI */ + { pinmux(7), 1, 4 }, /* SPI0_SIMO */ + { pinmux(7), 1, 6 } /* SPI0_CLK */ +}; + +const struct pinmux_config spi0_pins_scs0[] = { + { pinmux(7), 1, 7 } /* SPI0_SCS[0] */ +}; + +const struct pinmux_config spi0_pins_ena[] = { + { pinmux(7), 1, 5 } /* SPI0_ENA */ +}; + +/* NAND pin muxer settings */ +const struct pinmux_config emifa_pins_cs0[] = { + { pinmux(18), 1, 2 } /* EMA_CS[0] */ +}; + +const struct pinmux_config emifa_pins_cs2[] = { + { pinmux(18), 1, 3 } /* EMA_CS[2] */ +}; + +const struct pinmux_config emifa_pins_cs3[] = { + { pinmux(18), 1, 4 } /* EMA_CS[3] */ +}; + +#ifdef CONFIG_USE_NAND +const struct pinmux_config emifa_pins[] = { + { pinmux(13), 1, 6 }, /* EMA_D[0] */ + { pinmux(13), 1, 7 }, /* EMA_D[1] */ + { pinmux(14), 1, 0 }, /* EMA_D[2] */ + { pinmux(14), 1, 1 }, /* EMA_D[3] */ + { pinmux(14), 1, 2 }, /* EMA_D[4] */ + { pinmux(14), 1, 3 }, /* EMA_D[5] */ + { pinmux(14), 1, 4 }, /* EMA_D[6] */ + { pinmux(14), 1, 5 }, /* EMA_D[7] */ + { pinmux(14), 1, 6 }, /* EMA_D[8] */ + { pinmux(14), 1, 7 }, /* EMA_D[9] */ + { pinmux(15), 1, 0 }, /* EMA_D[10] */ + { pinmux(15), 1, 1 }, /* EMA_D[11] */ + { pinmux(15), 1, 2 }, /* EMA_D[12] */ + { pinmux(15), 1, 3 }, /* EMA_D[13] */ + { pinmux(15), 1, 4 }, /* EMA_D[14] */ + { pinmux(15), 1, 5 }, /* EMA_D[15] */ + { pinmux(15), 1, 6 }, /* EMA_A[0] */ + { pinmux(15), 1, 7 }, /* EMA_A[1] */ + { pinmux(16), 1, 0 }, /* EMA_A[2] */ + { pinmux(16), 1, 1 }, /* EMA_A[3] */ + { pinmux(16), 1, 2 }, /* EMA_A[4] */ + { pinmux(16), 1, 3 }, /* EMA_A[5] */ + { pinmux(16), 1, 4 }, /* EMA_A[6] */ + { pinmux(16), 1, 5 }, /* EMA_A[7] */ + { pinmux(16), 1, 6 }, /* EMA_A[8] */ + { pinmux(16), 1, 7 }, /* EMA_A[9] */ + { pinmux(17), 1, 0 }, /* EMA_A[10] */ + { pinmux(17), 1, 1 }, /* EMA_A[11] */ + { pinmux(17), 1, 2 }, /* EMA_A[12] */ + { pinmux(17), 1, 3 }, /* EMA_BA[1] */ + { pinmux(17), 1, 4 }, /* EMA_BA[0] */ + { pinmux(17), 1, 5 }, /* EMA_CLK */ + { pinmux(17), 1, 6 }, /* EMA_SDCKE */ + { pinmux(17), 1, 7 }, /* EMA_CAS */ + { pinmux(18), 1, 0 }, /* EMA_CAS */ + { pinmux(18), 1, 1 }, /* EMA_WE */ + { pinmux(18), 1, 5 }, /* EMA_OE */ + { pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */ + { pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */ + { pinmux(10), 1, 0 } /* Tristate */ +}; +#endif + +/* EMAC PHY interface pins */ +const struct pinmux_config emac_pins_rmii[] = { + { pinmux(10), 2, 1 }, /* RMII_TXD[0] */ + { pinmux(10), 2, 2 }, /* RMII_TXD[1] */ + { pinmux(10), 2, 3 }, /* RMII_TXEN */ + { pinmux(10), 2, 4 }, /* RMII_CRS_DV */ + { pinmux(10), 2, 5 }, /* RMII_RXD[0] */ + { pinmux(10), 2, 6 }, /* RMII_RXD[1] */ + { pinmux(10), 2, 7 } /* RMII_RXER */ +}; + +const struct pinmux_config emac_pins_mdio[] = { + { pinmux(11), 2, 0 }, /* MDIO_CLK */ + { pinmux(11), 2, 1 } /* MDIO_D */ +}; + +const struct pinmux_config emac_pins_rmii_clk_source[] = { + { pinmux(9), 0, 5 } /* ref.clk from external source */ +}; + +/* UART2 pin muxer settings */ +const struct pinmux_config uart2_pins_txrx[] = { + { pinmux(8), 2, 7 }, /* UART2_RXD */ + { pinmux(9), 2, 0 } /* UART2_TXD */ +}; + +/* I2C0 pin muxer settings */ +const struct pinmux_config i2c0_pins[] = { + { pinmux(8), 2, 3 }, /* I2C0_SDA */ + { pinmux(8), 2, 4 } /* I2C0_SCL */ +}; + +/* USB0_DRVVBUS pin muxer settings */ +const struct pinmux_config usb_pins[] = { + { pinmux(9), 1, 1 } /* USB0_DRVVBUS */ +}; + +#ifdef CONFIG_DAVINCI_MMC +/* MMC0 pin muxer settings */ +const struct pinmux_config mmc0_pins_8bit[] = { + { pinmux(15), 2, 7 }, /* MMCSD0_CLK */ + { pinmux(16), 2, 0 }, /* MMCSD0_CMD */ + { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */ + { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */ + { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */ + { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */ + { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */ + { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */ + { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */ + { pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */ + /* DA830 supports 8-bit mode */ +}; +#endif diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h index a851f1f..beaf0d6 100644 --- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -22,8 +22,14 @@ #define __ASM_ARCH_PINMUX_DEFS_H #include +#include -/* SPI pin muxer settings */ +/* SPI0 pin muxer settings */ +extern const struct pinmux_config spi0_pins_base[3]; +extern const struct pinmux_config spi0_pins_scs0[1]; +extern const struct pinmux_config spi0_pins_ena[1]; + +/* SPI1 pin muxer settings */ extern const struct pinmux_config spi1_pins_base[3]; extern const struct pinmux_config spi1_pins_scs0[1]; @@ -35,6 +41,7 @@ extern const struct pinmux_config uart2_pins_rtscts[2]; /* EMAC pin muxer settings*/ extern const struct pinmux_config emac_pins_rmii[7]; +extern const struct pinmux_config emac_pins_rmii_clk_source[1]; extern const struct pinmux_config emac_pins_mii[15]; extern const struct pinmux_config emac_pins_mdio[2]; @@ -43,13 +50,19 @@ extern const struct pinmux_config i2c0_pins[2]; extern const struct pinmux_config i2c1_pins[2]; /* EMIFA pin muxer settings */ +extern const struct pinmux_config emifa_pins[40]; +extern const struct pinmux_config emifa_pins_cs0[1]; extern const struct pinmux_config emifa_pins_cs2[1]; extern const struct pinmux_config emifa_pins_cs3[1]; extern const struct pinmux_config emifa_pins_cs4[1]; extern const struct pinmux_config emifa_pins_nand[12]; extern const struct pinmux_config emifa_pins_nor[43]; +/* USB pin mux setting */ +extern const struct pinmux_config usb_pins[1]; + /* MMC pin muxer settings */ +extern const struct pinmux_config mmc0_pins_8bit[10]; extern const struct pinmux_config mmc0_pins[6]; #endif -- cgit v1.1 From 58bb8f5f6138fa56875574a709f5af98c600c2a9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 15 May 2013 17:33:16 +0900 Subject: cosmetic: arm: fix comments in arch/arm/lib/crt0.S Signed-off-by: Masahiro Yamada --- arch/arm/lib/crt0.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a9657d1..a5bffb8 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -97,13 +97,13 @@ ENTRY(_main) * 'here' but relocated. */ - ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */ + ldr sp, [r8, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr r8, [r8, #GD_BD] /* r8 = gd->bd */ sub r8, r8, #GD_SIZE /* new GD is below bd */ adr lr, here - ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */ + ldr r0, [r8, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ add lr, lr, r0 ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */ b relocate_code -- cgit v1.1 From 847e6693ccb529bf8346db62876f38f0c4e04ade Mon Sep 17 00:00:00 2001 From: Sergey Yanovich Date: Tue, 21 May 2013 23:49:41 +0400 Subject: arm: pxa: config option for PXA270 turbo mode PXA270 CPU has turbo mode. The mode is 2.5 times faster than the default run mode. Activating the mode early significantly speeds up boot process. Signed-off-by: Sergey Yanovich --- arch/arm/cpu/pxa/pxa2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index 0c18610..f07dc67 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -244,7 +244,7 @@ void pxa_clock_setup(void) { writel(CONFIG_SYS_CKEN, CKEN); writel(CONFIG_SYS_CCCR, CCCR); - asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2)); + asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b)); /* enable the 32Khz oscillator for RTC and PowerManager */ writel(OSCC_OON, OSCC); -- cgit v1.1