From 9a06a1a3a1d5e65d7a14b060e4171b415d614072 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 13 Sep 2016 10:45:42 -0600 Subject: ARM: tegra: fdt: Add 'non-removable' property to all eMMC nodes During debug of the DM_MMC changes to the Tegra MMC driver, I noticed that the 'removable' property wasn't being set correctly for the eMMC parts on most Tegra boards. Since the kernel DTS has this property set correctly, it should be in U-Boot's Tegra DT too. Signed-off-by: Tom Warren Signed-off-by: Stephen Warren Reviewed-by: Simon Glass --- arch/arm/dts/tegra114-dalmore.dts | 1 + arch/arm/dts/tegra124-jetson-tk1.dts | 1 + arch/arm/dts/tegra124-venice2.dts | 1 + arch/arm/dts/tegra186-p2771-0000.dtsi | 1 + arch/arm/dts/tegra20-paz00.dts | 1 + arch/arm/dts/tegra20-whistler.dts | 1 + arch/arm/dts/tegra210-e2220-1170.dts | 1 + arch/arm/dts/tegra210-p2371-0000.dts | 1 + arch/arm/dts/tegra210-p2371-2180.dts | 1 + arch/arm/dts/tegra210-p2571.dts | 1 + arch/arm/dts/tegra30-beaver.dts | 1 + arch/arm/dts/tegra30-cardhu.dts | 1 + arch/arm/dts/tegra30-tamonten.dtsi | 1 + 13 files changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts index 49195c3..f0331a7 100644 --- a/arch/arm/dts/tegra114-dalmore.dts +++ b/arch/arm/dts/tegra114-dalmore.dts @@ -66,6 +66,7 @@ sdhci@78000600 { bus-width = <8>; status = "okay"; + non-removable; }; usb@7d000000 { diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts index 21ed1ae..4a63b6d 100644 --- a/arch/arm/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/dts/tegra124-jetson-tk1.dts @@ -312,6 +312,7 @@ sdhci@700b0600 { status = "okay"; bus-width = <8>; + non-removable; }; usb@7d000000 { diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts index 9de86c0..6c39563 100644 --- a/arch/arm/dts/tegra124-venice2.dts +++ b/arch/arm/dts/tegra124-venice2.dts @@ -81,6 +81,7 @@ sdhci@700b0600 { status = "okay"; bus-width = <8>; + non-removable; }; usb@7d000000 { diff --git a/arch/arm/dts/tegra186-p2771-0000.dtsi b/arch/arm/dts/tegra186-p2771-0000.dtsi index d867674..5550ac6 100644 --- a/arch/arm/dts/tegra186-p2771-0000.dtsi +++ b/arch/arm/dts/tegra186-p2771-0000.dtsi @@ -50,6 +50,7 @@ sdhci@3460000 { status = "okay"; bus-width = <8>; + non-removable; }; i2c@c240000 { diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 5c7e805..946862e 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -50,6 +50,7 @@ sdhci@c8000600 { status = "okay"; bus-width = <8>; + non-removable; }; clocks { diff --git a/arch/arm/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts index 358c582..d4577c9 100644 --- a/arch/arm/dts/tegra20-whistler.dts +++ b/arch/arm/dts/tegra20-whistler.dts @@ -58,6 +58,7 @@ sdhci@c8000600 { status = "okay"; bus-width = <8>; + non-removable; }; clocks { diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-e2220-1170.dts index 75efbba..c6e2176 100644 --- a/arch/arm/dts/tegra210-e2220-1170.dts +++ b/arch/arm/dts/tegra210-e2220-1170.dts @@ -31,6 +31,7 @@ sdhci@0,700b0600 { status = "okay"; bus-width = <8>; + non-removable; }; i2c@0,7000d000 { diff --git a/arch/arm/dts/tegra210-p2371-0000.dts b/arch/arm/dts/tegra210-p2371-0000.dts index 10172a2..3aa59d0 100644 --- a/arch/arm/dts/tegra210-p2371-0000.dts +++ b/arch/arm/dts/tegra210-p2371-0000.dts @@ -31,6 +31,7 @@ sdhci@0,700b0600 { status = "okay"; bus-width = <8>; + non-removable; }; i2c@0,7000d000 { diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts index bf35497..c4db2a4 100644 --- a/arch/arm/dts/tegra210-p2371-2180.dts +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -82,6 +82,7 @@ sdhci@0,700b0600 { status = "okay"; bus-width = <8>; + non-removable; }; i2c@0,7000d000 { diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts index de35bba..726c893 100644 --- a/arch/arm/dts/tegra210-p2571.dts +++ b/arch/arm/dts/tegra210-p2571.dts @@ -84,6 +84,7 @@ sdhci@0,700b0600 { status = "okay"; bus-width = <8>; + non-removable; }; usb@0,7d000000 { diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index ae83636..2ff7497 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -205,6 +205,7 @@ sdhci@78000600 { status = "okay"; bus-width = <8>; + non-removable; }; usb@7d000000 { diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts index 23ca141..3dc2043 100644 --- a/arch/arm/dts/tegra30-cardhu.dts +++ b/arch/arm/dts/tegra30-cardhu.dts @@ -194,6 +194,7 @@ sdhci@78000600 { status = "okay"; bus-width = <8>; + non-removable; }; usb@7d008000 { diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi index 8eff627..50ae9cc 100644 --- a/arch/arm/dts/tegra30-tamonten.dtsi +++ b/arch/arm/dts/tegra30-tamonten.dtsi @@ -64,6 +64,7 @@ sdhci@78000600 { status = "okay"; bus-width = <8>; + non-removable; }; usb@7d008000 { -- cgit v1.1 From 67748a73b14b239283bc1ace7564a124b714b75e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:43 -0600 Subject: mmc: tegra: use correct alias for SDHCI/MMC nodes The Tegra MMC driver currently honors "sdhci" entries in /aliases. The MMC core however uses "mmc" entries in /aliases. This difference will be relevant once the Tegra MMC driver is converted to DM, and the MMC core handles alias lookups. To avoid issues during that conversion, fix the Tegra MMC driver and all Tegra DTs to use the same alias name as the MMC core does. Cc: Jaehoon Chung Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Reviewed-by: Jaehoon Chung Signed-off-by: Tom Warren --- arch/arm/dts/tegra114-dalmore.dts | 4 ++-- arch/arm/dts/tegra124-cei-tk1-som.dts | 4 ++-- arch/arm/dts/tegra124-jetson-tk1.dts | 4 ++-- arch/arm/dts/tegra124-nyan-big.dts | 4 ++-- arch/arm/dts/tegra124-venice2.dts | 4 ++-- arch/arm/dts/tegra186-p2771-0000.dtsi | 4 ++-- arch/arm/dts/tegra20-colibri.dts | 2 +- arch/arm/dts/tegra20-harmony.dts | 4 ++-- arch/arm/dts/tegra20-medcom-wide.dts | 2 +- arch/arm/dts/tegra20-paz00.dts | 4 ++-- arch/arm/dts/tegra20-plutux.dts | 2 +- arch/arm/dts/tegra20-seaboard.dts | 4 ++-- arch/arm/dts/tegra20-tec.dts | 2 +- arch/arm/dts/tegra20-trimslice.dts | 4 ++-- arch/arm/dts/tegra20-ventana.dts | 4 ++-- arch/arm/dts/tegra20-whistler.dts | 4 ++-- arch/arm/dts/tegra210-e2220-1170.dts | 4 ++-- arch/arm/dts/tegra210-p2371-0000.dts | 4 ++-- arch/arm/dts/tegra210-p2371-2180.dts | 4 ++-- arch/arm/dts/tegra210-p2571.dts | 4 ++-- arch/arm/dts/tegra30-apalis.dts | 6 +++--- arch/arm/dts/tegra30-beaver.dts | 4 ++-- arch/arm/dts/tegra30-cardhu.dts | 4 ++-- arch/arm/dts/tegra30-colibri.dts | 4 ++-- arch/arm/dts/tegra30-tamonten.dtsi | 6 +++--- 25 files changed, 48 insertions(+), 48 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts index f0331a7..9325149 100644 --- a/arch/arm/dts/tegra114-dalmore.dts +++ b/arch/arm/dts/tegra114-dalmore.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - sdhci0 = "/sdhci@78000600"; - sdhci1 = "/sdhci@78000400"; + mmc0 = "/sdhci@78000600"; + mmc1 = "/sdhci@78000400"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d008000"; }; diff --git a/arch/arm/dts/tegra124-cei-tk1-som.dts b/arch/arm/dts/tegra124-cei-tk1-som.dts index d22c0ca..c4d4f9d 100644 --- a/arch/arm/dts/tegra124-cei-tk1-som.dts +++ b/arch/arm/dts/tegra124-cei-tk1-som.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - sdhci0 = "/sdhci@700b0600"; - sdhci1 = "/sdhci@700b0400"; + mmc0 = "/sdhci@700b0600"; + mmc1 = "/sdhci@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts index 4a63b6d..f1db952 100644 --- a/arch/arm/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/dts/tegra124-jetson-tk1.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - sdhci0 = "/sdhci@700b0600"; - sdhci1 = "/sdhci@700b0400"; + mmc0 = "/sdhci@700b0600"; + mmc1 = "/sdhci@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index 20e0be3..a0f1d09 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -17,8 +17,8 @@ i2c5 = "/i2c@7000d100"; rtc0 = "/i2c@0,7000d000/pmic@40"; rtc1 = "/rtc@0,7000e000"; - sdhci0 = "/sdhci@700b0600"; - sdhci1 = "/sdhci@700b0400"; + mmc0 = "/sdhci@700b0600"; + mmc1 = "/sdhci@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts index 6c39563..add9244 100644 --- a/arch/arm/dts/tegra124-venice2.dts +++ b/arch/arm/dts/tegra124-venice2.dts @@ -17,8 +17,8 @@ i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; i2c5 = "/i2c@7000d100"; - sdhci0 = "/sdhci@700b0600"; - sdhci1 = "/sdhci@700b0400"; + mmc0 = "/sdhci@700b0600"; + mmc1 = "/sdhci@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; diff --git a/arch/arm/dts/tegra186-p2771-0000.dtsi b/arch/arm/dts/tegra186-p2771-0000.dtsi index 5550ac6..6e07108 100644 --- a/arch/arm/dts/tegra186-p2771-0000.dtsi +++ b/arch/arm/dts/tegra186-p2771-0000.dtsi @@ -9,8 +9,8 @@ }; aliases { - sdhci0 = "/sdhci@3460000"; - sdhci1 = "/sdhci@3400000"; + mmc0 = "/sdhci@3460000"; + mmc1 = "/sdhci@3400000"; i2c0 = "/bpmp/i2c"; i2c1 = "/i2c@3160000"; i2c2 = "/i2c@c240000"; diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts index 2cf24d3..a291d93 100644 --- a/arch/arm/dts/tegra20-colibri.dts +++ b/arch/arm/dts/tegra20-colibri.dts @@ -17,7 +17,7 @@ usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; usb2 = "/usb@c5004000"; - sdhci0 = "/sdhci@c8000600"; + mmc0 = "/sdhci@c8000600"; }; host1x@50000000 { diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index 8e9fe5a..cace743 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -17,8 +17,8 @@ serial0 = &uartd; usb0 = "/usb@c5008000"; usb1 = "/usb@c5004000"; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000200"; + mmc0 = "/sdhci@c8000600"; + mmc1 = "/sdhci@c8000200"; }; memory { diff --git a/arch/arm/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts index 3d37257..1c79d75 100644 --- a/arch/arm/dts/tegra20-medcom-wide.dts +++ b/arch/arm/dts/tegra20-medcom-wide.dts @@ -12,7 +12,7 @@ aliases { usb0 = "/usb@c5008000"; - sdhci0 = "/sdhci@c8000600"; + mmc0 = "/sdhci@c8000600"; }; memory { diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 946862e..cf6bd70 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -12,8 +12,8 @@ aliases { usb0 = "/usb@c5008000"; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000000"; + mmc0 = "/sdhci@c8000600"; + mmc1 = "/sdhci@c8000000"; }; memory { diff --git a/arch/arm/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts index 7f57f1d..1b642be 100644 --- a/arch/arm/dts/tegra20-plutux.dts +++ b/arch/arm/dts/tegra20-plutux.dts @@ -12,7 +12,7 @@ aliases { usb0 = "/usb@c5008000"; - sdhci0 = "/sdhci@c8000600"; + mmc0 = "/sdhci@c8000600"; }; memory { diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 0a454f9..1421051 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -18,8 +18,8 @@ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uartd; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000400"; + mmc0 = "/sdhci@c8000600"; + mmc1 = "/sdhci@c8000400"; }; chosen { diff --git a/arch/arm/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts index 4f68077..4733c81 100644 --- a/arch/arm/dts/tegra20-tec.dts +++ b/arch/arm/dts/tegra20-tec.dts @@ -12,7 +12,7 @@ aliases { usb0 = "/usb@c5008000"; - sdhci0 = "/sdhci@c8000600"; + mmc0 = "/sdhci@c8000600"; }; memory { diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index db13ff9..be64e66 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -13,8 +13,8 @@ aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000000"; + mmc0 = "/sdhci@c8000600"; + mmc1 = "/sdhci@c8000000"; spi0 = "/spi@7000c380"; }; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 143e964..3714456 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -16,8 +16,8 @@ rtc1 = "/rtc@7000e000"; serial0 = &uartd; usb0 = "/usb@c5008000"; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000400"; + mmc0 = "/sdhci@c8000600"; + mmc1 = "/sdhci@c8000400"; }; memory { diff --git a/arch/arm/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts index d4577c9..4478746 100644 --- a/arch/arm/dts/tegra20-whistler.dts +++ b/arch/arm/dts/tegra20-whistler.dts @@ -13,8 +13,8 @@ aliases { i2c0 = "/i2c@7000d000"; usb0 = "/usb@c5008000"; - sdhci0 = "/sdhci@c8000600"; - sdhci1 = "/sdhci@c8000400"; + mmc0 = "/sdhci@c8000600"; + mmc1 = "/sdhci@c8000400"; }; memory { diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-e2220-1170.dts index c6e2176..69af9cf 100644 --- a/arch/arm/dts/tegra210-e2220-1170.dts +++ b/arch/arm/dts/tegra210-e2220-1170.dts @@ -12,8 +12,8 @@ aliases { i2c0 = "/i2c@0,7000d000"; - sdhci0 = "/sdhci@0,700b0600"; - sdhci1 = "/sdhci@0,700b0000"; + mmc0 = "/sdhci@0,700b0600"; + mmc1 = "/sdhci@0,700b0000"; usb0 = "/usb@0,7d000000"; }; diff --git a/arch/arm/dts/tegra210-p2371-0000.dts b/arch/arm/dts/tegra210-p2371-0000.dts index 3aa59d0..4431547 100644 --- a/arch/arm/dts/tegra210-p2371-0000.dts +++ b/arch/arm/dts/tegra210-p2371-0000.dts @@ -12,8 +12,8 @@ aliases { i2c0 = "/i2c@0,7000d000"; - sdhci0 = "/sdhci@0,700b0600"; - sdhci1 = "/sdhci@0,700b0000"; + mmc0 = "/sdhci@0,700b0600"; + mmc1 = "/sdhci@0,700b0000"; usb0 = "/usb@0,7d000000"; }; diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts index c4db2a4..aa18dd2 100644 --- a/arch/arm/dts/tegra210-p2371-2180.dts +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -12,8 +12,8 @@ aliases { i2c0 = "/i2c@0,7000d000"; - sdhci0 = "/sdhci@0,700b0600"; - sdhci1 = "/sdhci@0,700b0000"; + mmc0 = "/sdhci@0,700b0600"; + mmc1 = "/sdhci@0,700b0000"; usb0 = "/usb@0,7d000000"; }; diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts index 726c893..d2ad9ed 100644 --- a/arch/arm/dts/tegra210-p2571.dts +++ b/arch/arm/dts/tegra210-p2571.dts @@ -17,8 +17,8 @@ i2c3 = "/i2c@0,7000c500"; i2c4 = "/i2c@0,7000c700"; i2c5 = "/i2c@0,7000d100"; - sdhci0 = "/sdhci@0,700b0600"; - sdhci1 = "/sdhci@0,700b0000"; + mmc0 = "/sdhci@0,700b0600"; + mmc1 = "/sdhci@0,700b0000"; spi0 = "/spi@0,7000d400"; spi1 = "/spi@0,7000da00"; spi2 = "/spi@0,70410000"; diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 3e0545c..60e87a4 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -15,9 +15,9 @@ i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c500"; i2c3 = "/i2c@7000c700"; - sdhci0 = "/sdhci@78000600"; - sdhci1 = "/sdhci@78000400"; - sdhci2 = "/sdhci@78000000"; + mmc0 = "/sdhci@78000600"; + mmc1 = "/sdhci@78000400"; + mmc2 = "/sdhci@78000000"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000dc00"; spi2 = "/spi@7000de00"; diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index 2ff7497..340fcaf 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - sdhci0 = "/sdhci@78000600"; - sdhci1 = "/sdhci@78000000"; + mmc0 = "/sdhci@78000600"; + mmc1 = "/sdhci@78000000"; spi0 = "/spi@7000da00"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d008000"; diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts index 3dc2043..2237682 100644 --- a/arch/arm/dts/tegra30-cardhu.dts +++ b/arch/arm/dts/tegra30-cardhu.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - sdhci0 = "/sdhci@78000600"; - sdhci1 = "/sdhci@78000000"; + mmc0 = "/sdhci@78000600"; + mmc1 = "/sdhci@78000000"; spi0 = "/spi@7000da00"; usb0 = "/usb@7d008000"; }; diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts index 487e1f6..8784cd2 100644 --- a/arch/arm/dts/tegra30-colibri.dts +++ b/arch/arm/dts/tegra30-colibri.dts @@ -14,8 +14,8 @@ i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c700"; - sdhci0 = "/sdhci@78000600"; - sdhci1 = "/sdhci@78000200"; + mmc0 = "/sdhci@78000600"; + mmc1 = "/sdhci@78000200"; spi0 = "/spi@7000d400"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d004000"; /* on module only, for ASIX */ diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi index 50ae9cc..75c0f42 100644 --- a/arch/arm/dts/tegra30-tamonten.dtsi +++ b/arch/arm/dts/tegra30-tamonten.dtsi @@ -18,9 +18,9 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000d000"; - sdhci0 = "/sdhci@78000600"; - sdhci1 = "/sdhci@78000400"; - sdhci2 = "/sdhci@78000000"; + mmc0 = "/sdhci@78000600"; + mmc1 = "/sdhci@78000400"; + mmc2 = "/sdhci@78000000"; usb0 = "/usb@7d008000"; }; -- cgit v1.1 From 6b83588eea77c6fe69c11ba9e5eb2df071b1dadc Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:44 -0600 Subject: mmc: tegra: move pad_init_mmc() into MMC driver pad_init_mmc() is performing an SoC-specific operation, using registers within the MMC controller. There's no reason to implement this code outside the MMC driver, so move it inside the driver. Cc: Jaehoon Chung Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 -- arch/arm/mach-tegra/board186.c | 5 ----- arch/arm/mach-tegra/board2.c | 29 ----------------------------- 3 files changed, 36 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index 07ef4c0..fecb659 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -151,7 +151,5 @@ struct mmc_host { struct mmc_config cfg; /* mmc configuration */ }; -void pad_init_mmc(struct mmc_host *host); - #endif /* __ASSEMBLY__ */ #endif /* __TEGRA_MMC_H_ */ diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c index 1b9799f..8b76205 100644 --- a/arch/arm/mach-tegra/board186.c +++ b/arch/arm/mach-tegra/board186.c @@ -7,7 +7,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -31,10 +30,6 @@ int board_late_init(void) return 0; } -void pad_init_mmc(struct mmc_host *host) -{ -} - int board_mmc_init(bd_t *bd) { tegra_mmc_init(); diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 9158ace..e3cdb00 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -33,7 +33,6 @@ #include #endif #ifdef CONFIG_TEGRA_MMC -#include #include #endif #include @@ -248,34 +247,6 @@ int board_mmc_init(bd_t *bd) return 0; } - -void pad_init_mmc(struct mmc_host *host) -{ -#if defined(CONFIG_TEGRA30) - enum periph_id id = host->mmc_id; - u32 val; - - debug("%s: sdmmc address = %08x, id = %d\n", __func__, - (unsigned int)host->reg, id); - - /* Set the pad drive strength for SDMMC1 or 3 only */ - if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { - debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", - __func__); - return; - } - - val = readl(&host->reg->sdmemcmppadctl); - val &= 0xFFFFFFF0; - val |= MEMCOMP_PADCTRL_VREF; - writel(val, &host->reg->sdmemcmppadctl); - - val = readl(&host->reg->autocalcfg); - val &= 0xFFFF0000; - val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; - writel(val, &host->reg->autocalcfg); -#endif /* T30 */ -} #endif /* MMC */ /* -- cgit v1.1 From f53c4e4bbdb8e78a53141a3aec7bc80e7717a475 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:46 -0600 Subject: mmc: tegra: priv struct and naming cleanup struct mmc_host is a Tegra-specific structure, but the name implies it's something defined by core MMC code, which is confusing. Rename it to struct tegra_mmc_priv to make its purpose more obvious. The new name is also more appropriate for a DM driver private data structure, which will be relevant later in this series. Nothing needs access to this type except the MMC driver itself. Move the definition into the driver C file. Make sure all Tegra MMC functions are named tegra_mmc_*. Even though they're all static, it's useful to have good naming so that symbol tables are easy to interpret. A few functions aren't renamed by this patch since they'll be deleted by a subsequent patch in this series. Cc: Jaehoon Chung Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index fecb659..64c848a 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -132,24 +132,5 @@ struct tegra_mmc { #define AUTO_CAL_PD_OFFSET (0x70 << 8) #define AUTO_CAL_PU_OFFSET (0x62 << 0) -struct mmc_host { - struct tegra_mmc *reg; - int id; /* device id/number, 0-3 */ - int enabled; /* 1 to enable, 0 to disable */ - int width; /* Bus Width, 1, 4 or 8 */ -#ifdef CONFIG_TEGRA186 - struct reset_ctl reset_ctl; - struct clk clk; -#else - enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ -#endif - struct gpio_desc cd_gpio; /* Change Detect GPIO */ - struct gpio_desc pwr_gpio; /* Power GPIO */ - struct gpio_desc wp_gpio; /* Write Protect GPIO */ - unsigned int version; /* SDHCI spec. version */ - unsigned int clock; /* Current clock (MHz) */ - struct mmc_config cfg; /* mmc configuration */ -}; - #endif /* __ASSEMBLY__ */ #endif /* __TEGRA_MMC_H_ */ -- cgit v1.1 From c0be77dbdba504d24b6feb2f4669d8cac2497867 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:47 -0600 Subject: ARM: tegra: set MMC pin mux in board_init() Most other pin mux is configured in this function. This removes the need to do it in an MMC-specific initialization function, which is good since that function is going away later in this series. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/mach-tegra/board2.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index e3cdb00..3f87891 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -53,6 +53,7 @@ U_BOOT_DEVICE(tegra_gpios) = { __weak void pinmux_init(void) {} __weak void pin_mux_usb(void) {} __weak void pin_mux_spi(void) {} +__weak void pin_mux_mmc(void) {} __weak void gpio_early_init_uart(void) {} __weak void pin_mux_display(void) {} __weak void start_cpu_fan(void) {} @@ -127,6 +128,10 @@ int board_init(void) pin_mux_spi(); #endif +#ifdef CONFIG_TEGRA_MMC + pin_mux_mmc(); +#endif + /* Init is handled automatically in the driver-model case */ #if defined(CONFIG_DM_VIDEO) pin_mux_display(); @@ -230,18 +235,11 @@ int board_late_init(void) } #if defined(CONFIG_TEGRA_MMC) -__weak void pin_mux_mmc(void) -{ -} - /* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { debug("%s called\n", __func__); - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - debug("%s: init MMC\n", __func__); tegra_mmc_init(); -- cgit v1.1 From 6a474db4894d37f2edf4ed12e23b9e46f7a8aa3d Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 13 Sep 2016 10:45:48 -0600 Subject: mmc: tegra: Add DM_MMC support to Tegra MMC driver Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds. Cc: Jaehoon Chung Signed-off-by: Tom Warren (swarren, fixed some NULL pointer dereferences, removed extraneous changes, rebased on various other changes, removed non-DM support etc.) Signed-off-by: Stephen Warren --- arch/arm/include/asm/arch-tegra/mmc.h | 11 ----------- arch/arm/mach-tegra/Kconfig | 1 + arch/arm/mach-tegra/board186.c | 8 -------- arch/arm/mach-tegra/board2.c | 16 ---------------- 4 files changed, 1 insertion(+), 35 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/mmc.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/mmc.h b/arch/arm/include/asm/arch-tegra/mmc.h deleted file mode 100644 index c2d52b2..0000000 --- a/arch/arm/include/asm/arch-tegra/mmc.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2011, Google Inc. All rights reserved. - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_MMC_H_ -#define _TEGRA_MMC_H_ - -void tegra_mmc_init(void); - -#endif /* _TEGRA_MMC_H_ */ diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 76909ee..fb4b32e 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -27,6 +27,7 @@ config TEGRA_COMMON select DM_GPIO select DM_I2C select DM_KEYBOARD + select DM_MMC select DM_PCI select DM_PCI_COMPAT select DM_PWM diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c index 8b76205..a071758 100644 --- a/arch/arm/mach-tegra/board186.c +++ b/arch/arm/mach-tegra/board186.c @@ -6,7 +6,6 @@ #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -29,10 +28,3 @@ int board_late_init(void) { return 0; } - -int board_mmc_init(bd_t *bd) -{ - tegra_mmc_init(); - - return 0; -} diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 3f87891..cb9503f 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -32,9 +32,6 @@ #ifdef CONFIG_USB_EHCI_TEGRA #include #endif -#ifdef CONFIG_TEGRA_MMC -#include -#endif #include #include #include @@ -234,19 +231,6 @@ int board_late_init(void) return 0; } -#if defined(CONFIG_TEGRA_MMC) -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("%s called\n", __func__); - - debug("%s: init MMC\n", __func__); - tegra_mmc_init(); - - return 0; -} -#endif /* MMC */ - /* * In some SW environments, a memory carve-out exists to house a secure * monitor, a trusted OS, and/or various statically allocated media buffers. -- cgit v1.1 From eb631d7fb008201ce29200a649b0397c2f8536d2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:49 -0600 Subject: ARM: tegra: remove "0, " from DT unit addresses Apparently the unit address in a DT node name is now supposed to be a single integer value, rather than a comma-separated list of individual cell values. Fix the U-Boot DTs to comply with this naming convention. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/dts/tegra124-nyan-big.dts | 8 +++--- arch/arm/dts/tegra124-nyan.dtsi | 4 +-- arch/arm/dts/tegra210-e2220-1170.dts | 16 +++++------ arch/arm/dts/tegra210-p2371-0000.dts | 16 +++++------ arch/arm/dts/tegra210-p2371-2180.dts | 20 +++++++------- arch/arm/dts/tegra210-p2571.dts | 48 ++++++++++++++++----------------- arch/arm/dts/tegra210.dtsi | 52 ++++++++++++++++++------------------ 7 files changed, 82 insertions(+), 82 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index a0f1d09..3758395 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -15,8 +15,8 @@ i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; i2c5 = "/i2c@7000d100"; - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; mmc0 = "/sdhci@700b0600"; mmc1 = "/sdhci@700b0400"; spi0 = "/spi@7000d400"; @@ -58,7 +58,7 @@ ddc-i2c-bus = <&dpaux>; }; - sdhci@0,700b0400 { /* SD Card on this bus */ + sdhci@700b0400 { /* SD Card on this bus */ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; }; @@ -69,7 +69,7 @@ nvidia,model = "GoogleNyanBig"; }; - pinmux@0,70000868 { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi index 1b6931f..780131f 100644 --- a/arch/arm/dts/tegra124-nyan.dtsi +++ b/arch/arm/dts/tegra124-nyan.dtsi @@ -3,8 +3,8 @@ / { aliases { - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; serial0 = &uarta; }; diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-e2220-1170.dts index 69af9cf..70cd72b 100644 --- a/arch/arm/dts/tegra210-e2220-1170.dts +++ b/arch/arm/dts/tegra210-e2220-1170.dts @@ -11,35 +11,35 @@ }; aliases { - i2c0 = "/i2c@0,7000d000"; - mmc0 = "/sdhci@0,700b0600"; - mmc1 = "/sdhci@0,700b0000"; - usb0 = "/usb@0,7d000000"; + i2c0 = "/i2c@7000d000"; + mmc0 = "/sdhci@700b0600"; + mmc1 = "/sdhci@700b0000"; + usb0 = "/usb@7d000000"; }; memory { reg = <0x0 0x80000000 0x0 0xc0000000>; }; - sdhci@0,700b0000 { + sdhci@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; non-removable; }; - i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; }; - usb@0,7d000000 { + usb@7d000000 { status = "okay"; dr_mode = "peripheral"; }; diff --git a/arch/arm/dts/tegra210-p2371-0000.dts b/arch/arm/dts/tegra210-p2371-0000.dts index 4431547..d961296 100644 --- a/arch/arm/dts/tegra210-p2371-0000.dts +++ b/arch/arm/dts/tegra210-p2371-0000.dts @@ -11,35 +11,35 @@ }; aliases { - i2c0 = "/i2c@0,7000d000"; - mmc0 = "/sdhci@0,700b0600"; - mmc1 = "/sdhci@0,700b0000"; - usb0 = "/usb@0,7d000000"; + i2c0 = "/i2c@7000d000"; + mmc0 = "/sdhci@700b0600"; + mmc1 = "/sdhci@700b0000"; + usb0 = "/usb@7d000000"; }; memory { reg = <0x0 0x80000000 0x0 0xc0000000>; }; - sdhci@0,700b0000 { + sdhci@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; non-removable; }; - i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; }; - usb@0,7d000000 { + usb@7d000000 { status = "okay"; dr_mode = "otg"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts index aa18dd2..0dc06a4 100644 --- a/arch/arm/dts/tegra210-p2371-2180.dts +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -11,17 +11,17 @@ }; aliases { - i2c0 = "/i2c@0,7000d000"; - mmc0 = "/sdhci@0,700b0600"; - mmc1 = "/sdhci@0,700b0000"; - usb0 = "/usb@0,7d000000"; + i2c0 = "/i2c@7000d000"; + mmc0 = "/sdhci@700b0600"; + mmc1 = "/sdhci@700b0000"; + usb0 = "/usb@7d000000"; }; memory { reg = <0x0 0x80000000 0x0 0xc0000000>; }; - pcie-controller@0,01003000 { + pcie-controller@01003000 { status = "okay"; pci@1,0 { @@ -33,7 +33,7 @@ }; }; - padctl@0,7009f000 { + padctl@7009f000 { pinctrl-0 = <&padctl_default>; pinctrl-names = "default"; @@ -71,7 +71,7 @@ }; }; - sdhci@0,700b0000 { + sdhci@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; @@ -79,18 +79,18 @@ bus-width = <4>; }; - sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; non-removable; }; - i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; }; - usb@0,7d000000 { + usb@7d000000 { status = "okay"; dr_mode = "otg"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts index d2ad9ed..2afcde5 100644 --- a/arch/arm/dts/tegra210-p2571.dts +++ b/arch/arm/dts/tegra210-p2571.dts @@ -11,83 +11,83 @@ }; aliases { - i2c0 = "/i2c@0,7000d000"; - i2c1 = "/i2c@0,7000c000"; - i2c2 = "/i2c@0,7000c400"; - i2c3 = "/i2c@0,7000c500"; - i2c4 = "/i2c@0,7000c700"; - i2c5 = "/i2c@0,7000d100"; - mmc0 = "/sdhci@0,700b0600"; - mmc1 = "/sdhci@0,700b0000"; - spi0 = "/spi@0,7000d400"; - spi1 = "/spi@0,7000da00"; - spi2 = "/spi@0,70410000"; - usb0 = "/usb@0,7d000000"; + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + i2c5 = "/i2c@7000d100"; + mmc0 = "/sdhci@700b0600"; + mmc1 = "/sdhci@700b0000"; + spi0 = "/spi@7000d400"; + spi1 = "/spi@7000da00"; + spi2 = "/spi@70410000"; + usb0 = "/usb@7d000000"; }; memory { reg = <0x0 0x80000000 0x0 0xc0000000>; }; - i2c@0,7000c000 { + i2c@7000c000 { status = "okay"; clock-frequency = <100000>; }; - i2c@0,7000c400 { + i2c@7000c400 { status = "okay"; clock-frequency = <100000>; }; - i2c@0,7000c500 { + i2c@7000c500 { status = "okay"; clock-frequency = <100000>; }; - i2c@0,7000c700 { + i2c@7000c700 { status = "okay"; clock-frequency = <100000>; }; - i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; }; - i2c@0,7000d100 { + i2c@7000d100 { status = "okay"; clock-frequency = <400000>; }; - spi@0,7000d400 { + spi@7000d400 { status = "okay"; spi-max-frequency = <25000000>; }; - spi@0,7000da00 { + spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; }; - spi@0,70410000 { + spi@70410000 { status = "okay"; spi-max-frequency = <24000000>; }; - sdhci@0,700b0000 { + sdhci@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; non-removable; }; - usb@0,7d000000 { + usb@7d000000 { status = "okay"; dr_mode = "otg"; }; diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index a8c2f19..fd4cc79 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -12,7 +12,7 @@ #address-cells = <2>; #size-cells = <2>; - pcie-controller@0,01003000 { + pcie-controller@01003000 { compatible = "nvidia,tegra210-pcie"; device_type = "pci"; reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ @@ -78,7 +78,7 @@ }; }; - gic: interrupt-controller@0,50041000 { + gic: interrupt-controller@50041000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-controller; @@ -91,14 +91,14 @@ interrupt-parent = <&gic>; }; - tegra_car: clock@0,60006000 { + tegra_car: clock@60006000 { compatible = "nvidia,tegra210-car"; reg = <0x0 0x60006000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - gpio: gpio@0,6000d000 { + gpio: gpio@6000d000 { compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; interrupts = , @@ -115,7 +115,7 @@ interrupt-controller; }; - i2c@0,7000c000 { + i2c@7000c000 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = <0 38 0x04>; @@ -125,7 +125,7 @@ status = "disabled"; }; - i2c@0,7000c400 { + i2c@7000c400 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = <0 84 0x04>; @@ -135,7 +135,7 @@ status = "disabled"; }; - i2c@0,7000c500 { + i2c@7000c500 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = <0 92 0x04>; @@ -145,7 +145,7 @@ status = "disabled"; }; - i2c@0,7000c700 { + i2c@7000c700 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = <0 120 0x04>; @@ -155,7 +155,7 @@ status = "disabled"; }; - i2c@0,7000d000 { + i2c@7000d000 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = <0 53 0x04>; @@ -165,7 +165,7 @@ status = "disabled"; }; - i2c@0,7000d100 { + i2c@7000d100 { compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = <0 53 0x04>; @@ -175,7 +175,7 @@ status = "disabled"; }; - uarta: serial@0,70006000 { + uarta: serial@70006000 { compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006000 0x0 0x40>; reg-shift = <2>; @@ -186,7 +186,7 @@ status = "disabled"; }; - uartb: serial@0,70006040 { + uartb: serial@70006040 { compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006040 0x0 0x40>; reg-shift = <2>; @@ -197,7 +197,7 @@ status = "disabled"; }; - uartc: serial@0,70006200 { + uartc: serial@70006200 { compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006200 0x0 0x40>; reg-shift = <2>; @@ -208,7 +208,7 @@ status = "disabled"; }; - uartd: serial@0,70006300 { + uartd: serial@70006300 { compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006300 0x0 0x40>; reg-shift = <2>; @@ -219,7 +219,7 @@ status = "disabled"; }; - spi@0,7000d400 { + spi@7000d400 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d400 0x0 0x200>; interrupts = <0 59 0x04>; @@ -231,7 +231,7 @@ status = "disabled"; }; - spi@0,7000d600 { + spi@7000d600 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d600 0x0 0x200>; interrupts = <0 82 0x04>; @@ -243,7 +243,7 @@ status = "disabled"; }; - spi@0,7000d800 { + spi@7000d800 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d800 0x0 0x200>; interrupts = <0 83 0x04>; @@ -255,7 +255,7 @@ status = "disabled"; }; - spi@0,7000da00 { + spi@7000da00 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000da00 0x0 0x200>; interrupts = <0 93 0x04>; @@ -267,7 +267,7 @@ status = "disabled"; }; - spi@0,70410000 { + spi@70410000 { compatible = "nvidia,tegra210-qspi"; reg = <0x0 0x70410000 0x0 0x1000>; interrupts = <0 10 0x04>; @@ -277,7 +277,7 @@ status = "disabled"; }; - padctl: padctl@0,7009f000 { + padctl: padctl@7009f000 { compatible = "nvidia,tegra210-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; @@ -285,7 +285,7 @@ #phy-cells = <1>; }; - sdhci@0,700b0000 { + sdhci@700b0000 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = <0 14 0x04>; @@ -295,7 +295,7 @@ status = "disabled"; }; - sdhci@0,700b0200 { + sdhci@700b0200 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = <0 15 0x04>; @@ -305,7 +305,7 @@ status = "disabled"; }; - sdhci@0,700b0400 { + sdhci@700b0400 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = <0 19 0x04>; @@ -315,7 +315,7 @@ status = "disabled"; }; - sdhci@0,700b0600 { + sdhci@700b0600 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = <0 31 0x04>; @@ -325,7 +325,7 @@ status = "disabled"; }; - usb@0,7d000000 { + usb@7d000000 { compatible = "nvidia,tegra210-ehci"; reg = <0x0 0x7d000000 0x0 0x4000>; interrupts = <0 20 0x04>; @@ -336,7 +336,7 @@ status = "disabled"; }; - usb@0,7d004000 { + usb@7d004000 { compatible = "nvidia,tegra210-ehci"; reg = <0x0 0x7d004000 0x0 0x4000>; interrupts = < 53 >; -- cgit v1.1 From 50a303bdfa413f8387da32f428ea1f3829c94498 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:50 -0600 Subject: ARM: tegra: pull Tegra20 SoC DT from Linux v4.7 This brings in a few minor fixes since the last sync. The largest change is the removal of the definition for TEGRA20_CLK_PCIE_XCLK. This clock doesn't actually exist. Remaining deltas: * Addition of u-boot,dm-pre-reloc property to a couple of nodes. * Addition of the NAND controller, which Linux doesn't yet support. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/dts/tegra20.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 31223e4..84bb1b0 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -147,7 +147,7 @@ interrupt-parent = <&intc>; reg = <0x50040600 0x20>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; clocks = <&tegra_car TEGRA20_CLK_TWD>; }; @@ -311,7 +311,7 @@ * driver and APB DMA based serial driver for higher baudrate * and performace. To enable the 8250 based driver, the compatible * is "nvidia,tegra20-uart" and to enable the APB DMA based serial - * driver, the comptible is "nvidia,tegra20-hsuart". + * driver, the compatible is "nvidia,tegra20-hsuart". */ uarta: serial@70006000 { compatible = "nvidia,tegra20-uart"; -- cgit v1.1 From ce2f2d2ae7fd1350309e0680cd427258ddd8a26e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:51 -0600 Subject: ARM: tegra: pull Tegra30 SoC DT from Linux v4.7 The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Modification of PCIe memory region addresses. The HW memory layout is programmable, so this should work fine, and Beaver PCIe was tested without issue. * Removal of pcie_xclk from the PCIe node and clock binding header. This clock doesn't exist and isn't used; only a reset with this ID exists. * Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Changed the phy_type value for the second USB port. This required board DTs to be updated to keep the same configuration. * Boards need to define the clk32k_in clock that feeds the Tegra PMC. * Addition of tegra30-mc.h since tegra30.dtsi now includes it. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot. * Node sort order fixes. Remaining deltas relative to the Linux DT: * None. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/dts/tegra30-apalis.dts | 21 +- arch/arm/dts/tegra30-beaver.dts | 13 + arch/arm/dts/tegra30-cardhu.dts | 13 + arch/arm/dts/tegra30-colibri.dts | 14 +- arch/arm/dts/tegra30-tamonten.dtsi | 12 + arch/arm/dts/tegra30.dtsi | 828 ++++++++++++++++++++++++++++++------- 6 files changed, 758 insertions(+), 143 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 60e87a4..f83f094 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -277,7 +277,6 @@ status = "okay"; /* USBH_EN */ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; - phy_type = "utmi"; }; /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ @@ -287,6 +286,26 @@ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clk@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + clk16m: clk@1 { + compatible = "fixed-clock"; + reg=<1>; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "clk16m"; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index 340fcaf..4a32fcf 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -219,6 +219,19 @@ status = "okay"; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts index 2237682..70fd916 100644 --- a/arch/arm/dts/tegra30-cardhu.dts +++ b/arch/arm/dts/tegra30-cardhu.dts @@ -202,6 +202,19 @@ status = "okay"; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts index 8784cd2..3cff2f6 100644 --- a/arch/arm/dts/tegra30-colibri.dts +++ b/arch/arm/dts/tegra30-colibri.dts @@ -84,7 +84,6 @@ status = "okay"; /* VBUS_LAN */ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; - phy_type = "utmi"; }; /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ @@ -93,4 +92,17 @@ /* USBH_PEN */ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clk@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; }; diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi index 75c0f42..33da175 100644 --- a/arch/arm/dts/tegra30-tamonten.dtsi +++ b/arch/arm/dts/tegra30-tamonten.dtsi @@ -71,4 +71,16 @@ status = "okay"; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clk@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; }; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 5ea7e34..5030065 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -1,20 +1,14 @@ #include #include +#include +#include #include #include "skeleton.dtsi" / { compatible = "nvidia,tegra30"; - interrupt-parent = <&intc>; - - intc: interrupt-controller@50041000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; + interrupt-parent = <&lic>; pcie-controller@00003000 { compatible = "nvidia,tegra30-pcie"; @@ -24,7 +18,7 @@ 0x10000000 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = ; /* MSI interrupt */ + GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ interrupt-names = "intr", "msi"; #interrupt-cells = <1>; @@ -39,15 +33,18 @@ 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ - 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ + 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ + 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car TEGRA30_CLK_PCIE>, <&tegra_car TEGRA30_CLK_AFI>, - <&tegra_car TEGRA30_CLK_PCIEX>, <&tegra_car TEGRA30_CLK_PLL_E>, <&tegra_car TEGRA30_CLK_CML0>; - clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; status = "disabled"; pci@1,0 { @@ -90,48 +87,251 @@ }; }; - tegra_car: clock { + host1x@50000000 { + compatible = "nvidia,tegra30-host1x", "simple-bus"; + reg = <0x50000000 0x00024000>; + interrupts = , /* syncpt */ + ; /* general */ + clocks = <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + mpe@54040000 { + compatible = "nvidia,tegra30-mpe"; + reg = <0x54040000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; + }; + + vi@54080000 { + compatible = "nvidia,tegra30-vi"; + reg = <0x54080000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; + }; + + epp@540c0000 { + compatible = "nvidia,tegra30-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; + }; + + isp@54100000 { + compatible = "nvidia,tegra30-isp"; + reg = <0x54100000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; + }; + + gr2d@54140000 { + compatible = "nvidia,tegra30-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_GR2D>; + resets = <&tegra_car 21>; + reset-names = "2d"; + }; + + gr3d@54180000 { + compatible = "nvidia,tegra30-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_GR3D + &tegra_car TEGRA30_CLK_GR3D2>; + clock-names = "3d", "3d2"; + resets = <&tegra_car 24>, + <&tegra_car 98>; + reset-names = "3d", "3d2"; + }; + + dc@54200000 { + compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DC>; + + nvidia,head = <0>; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra30-dc"; + reg = <0x54240000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_DISP2>, + <&tegra_car TEGRA30_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DCB>; + + nvidia,head = <1>; + + rgb { + status = "disabled"; + }; + }; + + hdmi@54280000 { + compatible = "nvidia,tegra30-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_HDMI>, + <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + + tvo@542c0000 { + compatible = "nvidia,tegra30-tvo"; + reg = <0x542c0000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_TVO>; + status = "disabled"; + }; + + dsi@54300000 { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>; + resets = <&tegra_car 48>; + reset-names = "dsi"; + status = "disabled"; + }; + }; + + timer@50040600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x50040600 0x20>; + interrupt-parent = <&intc>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_TWD>; + }; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x50041000 0x1000 + 0x50040100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + }; + + cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <6 6 2>; + arm,tag-latency = <5 5 2>; + cache-unified; + cache-level = <2>; + }; + + lic: interrupt-controller@60004000 { + compatible = "nvidia,tegra30-ictlr"; + reg = <0x60004000 0x100>, + <0x60004100 0x50>, + <0x60004200 0x50>, + <0x60004300 0x50>, + <0x60004400 0x50>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + }; + + timer@60005000 { + compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + reg = <0x60005000 0x400>; + interrupts = , + , + , + , + , + ; + clocks = <&tegra_car TEGRA30_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { compatible = "nvidia,tegra30-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; + }; + + flow-controller@60007000 { + compatible = "nvidia,tegra30-flowctrl"; + reg = <0x60007000 0x1000>; }; - apbdma: dma { + apbdma: dma@6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; - interrupts = <0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 - 0 128 0x04 - 0 129 0x04 - 0 130 0x04 - 0 131 0x04 - 0 132 0x04 - 0 133 0x04 - 0 134 0x04 - 0 135 0x04 - 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04>; - clocks = <&tegra_car 34>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA30_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; + + ahb: ahb@6000c000 { + compatible = "nvidia,tegra30-ahb"; + reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ }; gpio: gpio@6000d000 { @@ -149,63 +349,31 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; + /* + gpio-ranges = <&pinmux 0 0 248>; + */ }; - i2c@7000c000 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 12>, <&tegra_car 182>; - clock-names = "div-clk", "fast-clk"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c400 0x100>; - interrupts = <0 84 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 54>, <&tegra_car 182>; - clock-names = "div-clk", "fast-clk"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c500 0x100>; - interrupts = <0 92 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 67>, <&tegra_car 182>; - clock-names = "div-clk", "fast-clk"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c700 0x100>; - interrupts = <0 120 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 103>, <&tegra_car 182>; - clock-names = "div-clk", "fast-clk"; - status = "disabled"; + apbmisc@70000800 { + compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64 /* Chip revision */ + 0x70000008 0x04>; /* Strapping options */ }; - i2c@7000d000 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000d000 0x100>; - interrupts = <0 53 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 47>, <&tegra_car 182>; - clock-names = "div-clk", "fast-clk"; - status = "disabled"; + pinmux: pinmux@70000868 { + compatible = "nvidia,tegra30-pinmux"; + reg = <0x70000868 0xd4 /* Pad control registers */ + 0x70003000 0x3e4>; /* Mux registers */ }; + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable + * the APB DMA based serial driver, the compatible is + * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". + */ uarta: serial@70006000 { compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; @@ -271,128 +439,506 @@ status = "disabled"; }; + pwm: pwm@7000a000 { + compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA30_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + + rtc@7000e000 { + compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_RTC>; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C1>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c400 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C2>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c500 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C3>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C4>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + resets = <&tegra_car 103>; + reset-names = "i2c"; + clock-names = "div-clk", "fast-clk"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000d000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA30_CLK_I2C5>, + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi@7000d400 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d400 0x200>; - interrupts = <0 59 0x04>; - nvidia,dma-request-selector = <&apbdma 15>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 41>; + clocks = <&tegra_car TEGRA30_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; }; spi@7000d600 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - nvidia,dma-request-selector = <&apbdma 16>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 44>; + clocks = <&tegra_car TEGRA30_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; }; spi@7000d800 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d480 0x200>; - interrupts = <0 83 0x04>; - nvidia,dma-request-selector = <&apbdma 17>; + reg = <0x7000d800 0x200>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 46>; + clocks = <&tegra_car TEGRA30_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; }; spi@7000da00 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000da00 0x200>; - interrupts = <0 93 0x04>; - nvidia,dma-request-selector = <&apbdma 18>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 68>; + clocks = <&tegra_car TEGRA30_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; }; spi@7000dc00 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000dc00 0x200>; - interrupts = <0 94 0x04>; - nvidia,dma-request-selector = <&apbdma 27>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 104>; + clocks = <&tegra_car TEGRA30_CLK_SBC5>; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; status = "disabled"; }; spi@7000de00 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000de00 0x200>; - interrupts = <0 79 0x04>; - nvidia,dma-request-selector = <&apbdma 28>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 105>; + clocks = <&tegra_car TEGRA30_CLK_SBC6>; + resets = <&tegra_car 106>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + kbc@7000e200 { + compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; + reg = <0x7000e200 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; + status = "disabled"; + }; + + pmc@7000e400 { + compatible = "nvidia,tegra30-pmc"; + reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + }; + + mc: memory-controller@7000f000 { + compatible = "nvidia,tegra30-mc"; + reg = <0x7000f000 0x400>; + clocks = <&tegra_car TEGRA30_CLK_MC>; + clock-names = "mc"; + + interrupts = ; + + #iommu-cells = <1>; + }; + + fuse@7000f800 { + compatible = "nvidia,tegra30-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA30_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + + hda@70030000 { + compatible = "nvidia,tegra30-hda"; + reg = <0x70030000 0x10000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_HDA>, + <&tegra_car TEGRA30_CLK_HDA2HDMI>, + <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; status = "disabled"; }; + ahub@70080000 { + compatible = "nvidia,tegra30-ahub"; + reg = <0x70080000 0x200 + 0x70080200 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, + <&tegra_car TEGRA30_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>; /* spdif */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70080300 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080300 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA30_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70080400 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080400 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA30_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70080500 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080500 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA30_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s3: i2s@70080600 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080600 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA30_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s4: i2s@70080700 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080700 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA30_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; + status = "disabled"; + }; + }; + sdhci@78000000 { - compatible = "nvidia,tegra30-sdhci"; + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000000 0x200>; - interrupts = <0 14 0x04>; - clocks = <&tegra_car 14>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; status = "disabled"; }; sdhci@78000200 { - compatible = "nvidia,tegra30-sdhci"; + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000200 0x200>; - interrupts = <0 15 0x04>; - clocks = <&tegra_car 9>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; status = "disabled"; }; sdhci@78000400 { - compatible = "nvidia,tegra30-sdhci"; + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000400 0x200>; - interrupts = <0 19 0x04>; - clocks = <&tegra_car 69>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; status = "disabled"; }; sdhci@78000600 { - compatible = "nvidia,tegra30-sdhci"; + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000600 0x200>; - interrupts = <0 31 0x04>; - clocks = <&tegra_car 15>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; status = "disabled"; }; usb@7d000000 { - compatible = "nvidia,tegra30-ehci"; + compatible = "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d000000 0x4000>; - interrupts = <52>; + interrupts = ; phy_type = "utmi"; - clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + clocks = <&tegra_car TEGRA30_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,needs-double-reset; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d000000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USBD>, + <&tegra_car TEGRA30_CLK_PLL_U>, + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 22>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <1>; + nvidia,xcvr-lsrslew = <1>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,has-utmi-pad-registers; status = "disabled"; }; usb@7d004000 { - compatible = "nvidia,tegra30-ehci"; + compatible = "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d004000 0x4000>; - interrupts = <53>; - phy_type = "hsic"; - clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; + nvidia,phy = <&phy2>; + status = "disabled"; + }; + + phy2: usb-phy@7d004000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d004000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USB2>, + <&tegra_car TEGRA30_CLK_PLL_U>, + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; status = "disabled"; }; usb@7d008000 { - compatible = "nvidia,tegra30-ehci"; + compatible = "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d008000 0x4000>; - interrupts = <129>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@7d008000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000 0x7d000000 0x4000>; phy_type = "utmi"; - clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + clocks = <&tegra_car TEGRA30_CLK_USB3>, + <&tegra_car TEGRA30_CLK_PLL_U>, + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; status = "disabled"; }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + , + , + ; + }; }; -- cgit v1.1 From 5c31e7abb4b1fcdedd0f9c340e4dda03537238c6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:52 -0600 Subject: ARM: tegra: pull Tegra114 SoC DT from Linux v4.7 The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Boards need to define the clk32k_in clock that feeds the Tegra PMC. * Addition of tegra114-mc.h since tegra114.dtsi now includes it. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot. * Node sort order fixes. Remaining deltas relative to the Linux DT: * USB node compatible values in U-Boot explicitly list Tegra114 values whereas the kernel does not. I'll send a kernel patch to correct this. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/dts/tegra114-dalmore.dts | 13 + arch/arm/dts/tegra114.dtsi | 743 +++++++++++++++++++++++++++++++------- 2 files changed, 627 insertions(+), 129 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts index 9325149..5f4df88 100644 --- a/arch/arm/dts/tegra114-dalmore.dts +++ b/arch/arm/dts/tegra114-dalmore.dts @@ -79,4 +79,17 @@ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; status = "okay"; }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; }; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 88bdc49..8932ea3 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -1,53 +1,222 @@ #include #include +#include +#include #include #include "skeleton.dtsi" / { compatible = "nvidia,tegra114"; + interrupt-parent = <&lic>; - tegra_car: clock { + host1x@50000000 { + compatible = "nvidia,tegra114-host1x", "simple-bus"; + reg = <0x50000000 0x00028000>; + interrupts = , /* syncpt */ + ; /* general */ + clocks = <&tegra_car TEGRA114_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x01000000>; + + gr2d@54140000 { + compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_GR2D>; + resets = <&tegra_car 21>; + reset-names = "2d"; + }; + + gr3d@54180000 { + compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_GR3D>; + resets = <&tegra_car 24>; + reset-names = "3d"; + }; + + dc@54200000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_DISP1>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DC>; + + nvidia,head = <0>; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + reg = <0x54240000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_DISP2>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DCB>; + + nvidia,head = <1>; + + rgb { + status = "disabled"; + }; + }; + + hdmi@54280000 { + compatible = "nvidia,tegra114-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_HDMI>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + + dsi@54300000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIA>, + <&tegra_car TEGRA114_CLK_DSIALP>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIB>, + <&tegra_car TEGRA114_CLK_DSIBLP>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gic: interrupt-controller@50041000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x50041000 0x1000>, + <0x50042000 0x1000>, + <0x50044000 0x2000>, + <0x50046000 0x2000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + lic: interrupt-controller@60004000 { + compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; + reg = <0x60004000 0x100>, + <0x60004100 0x50>, + <0x60004200 0x50>, + <0x60004300 0x50>, + <0x60004400 0x50>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + timer@60005000 { + compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + reg = <0x60005000 0x400>; + interrupts = , + , + , + , + , + ; + clocks = <&tegra_car TEGRA114_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { compatible = "nvidia,tegra114-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; - apbdma: dma { - compatible = "nvidia,tegra114-apbdma", "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; + flow-controller@60007000 { + compatible = "nvidia,tegra114-flowctrl"; + reg = <0x60007000 0x1000>; + }; + + apbdma: dma@6000a000 { + compatible = "nvidia,tegra114-apbdma"; reg = <0x6000a000 0x1400>; - interrupts = <0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 - 0 128 0x04 - 0 129 0x04 - 0 130 0x04 - 0 131 0x04 - 0 132 0x04 - 0 133 0x04 - 0 134 0x04 - 0 135 0x04 - 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA114_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; + + ahb: ahb@6000c000 { + compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; + reg = <0x6000c000 0x150>; }; gpio: gpio@6000d000 { @@ -65,58 +234,31 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; + /* + gpio-ranges = <&pinmux 0 0 246>; + */ }; - i2c@7000c000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 12>; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c400 0x100>; - interrupts = <0 84 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 54>; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c500 0x100>; - interrupts = <0 92 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 67>; - status = "disabled"; + apbmisc@70000800 { + compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64 /* Chip revision */ + 0x70000008 0x04>; /* Strapping options */ }; - i2c@7000c700 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c700 0x100>; - interrupts = <0 120 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 103>; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000d000 0x100>; - interrupts = <0 53 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 47>; - status = "disabled"; + pinmux: pinmux@70000868 { + compatible = "nvidia,tegra114-pinmux"; + reg = <0x70000868 0x148 /* Pad control registers */ + 0x70003000 0x40c>; /* Mux registers */ }; + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable + * the APB DMA based serial driver, the compatible is + * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". + */ uarta: serial@70006000 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; @@ -169,134 +311,477 @@ status = "disabled"; }; + pwm: pwm@7000a000 { + compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA114_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C1>; + clock-names = "div-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c400 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C2>; + clock-names = "div-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c500 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C3>; + clock-names = "div-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c700 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C4>; + clock-names = "div-clk"; + resets = <&tegra_car 103>; + reset-names = "i2c"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000d000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_I2C5>; + clock-names = "div-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi@7000d400 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; - interrupts = <0 59 0x04>; - nvidia,dma-request-selector = <&apbdma 15>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC1>; + clock-names = "spi"; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; - /* PERIPH_ID_SBC1, PLLP_OUT0 */ - clocks = <&tegra_car 41>; }; spi@7000d600 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - nvidia,dma-request-selector = <&apbdma 16>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC2>; + clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; - /* PERIPH_ID_SBC2, PLLP_OUT0 */ - clocks = <&tegra_car 44>; }; spi@7000d800 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d800 0x200>; - interrupts = <0 83 0x04>; - nvidia,dma-request-selector = <&apbdma 17>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC3>; + clock-names = "spi"; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; - /* PERIPH_ID_SBC3, PLLP_OUT0 */ - clocks = <&tegra_car 46>; }; spi@7000da00 { compatible = "nvidia,tegra114-spi"; reg = <0x7000da00 0x200>; - interrupts = <0 93 0x04>; - nvidia,dma-request-selector = <&apbdma 18>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC4>; + clock-names = "spi"; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; - /* PERIPH_ID_SBC4, PLLP_OUT0 */ - clocks = <&tegra_car 68>; }; spi@7000dc00 { compatible = "nvidia,tegra114-spi"; reg = <0x7000dc00 0x200>; - interrupts = <0 94 0x04>; - nvidia,dma-request-selector = <&apbdma 27>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC5>; + clock-names = "spi"; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; status = "disabled"; - /* PERIPH_ID_SBC5, PLLP_OUT0 */ - clocks = <&tegra_car 104>; }; spi@7000de00 { compatible = "nvidia,tegra114-spi"; reg = <0x7000de00 0x200>; - interrupts = <0 79 0x04>; - nvidia,dma-request-selector = <&apbdma 28>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car TEGRA114_CLK_SBC6>; + clock-names = "spi"; + resets = <&tegra_car 105>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + rtc@7000e000 { + compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_RTC>; + }; + + kbc@7000e200 { + compatible = "nvidia,tegra114-kbc"; + reg = <0x7000e200 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; status = "disabled"; - /* PERIPH_ID_SBC6, PLLP_OUT0 */ - clocks = <&tegra_car 105>; + }; + + pmc@7000e400 { + compatible = "nvidia,tegra114-pmc"; + reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + }; + + fuse@7000f800 { + compatible = "nvidia,tegra114-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA114_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + + mc: memory-controller@70019000 { + compatible = "nvidia,tegra114-mc"; + reg = <0x70019000 0x1000>; + clocks = <&tegra_car TEGRA114_CLK_MC>; + clock-names = "mc"; + + interrupts = ; + + #iommu-cells = <1>; + }; + + ahub@70080000 { + compatible = "nvidia,tegra114-ahub"; + reg = <0x70080000 0x200>, + <0x70080200 0x100>, + <0x70081000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, + <&tegra_car TEGRA114_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>, /* spdif */ + <&tegra_car 153>, /* amx */ + <&tegra_car 154>; /* adx */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif", "amx", "adx"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 6>, + <&apbdma 7>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 12>, + <&apbdma 13>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 14>, + <&apbdma 29>, <&apbdma 29>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", + "rx9", "tx9"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70080300 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080300 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA114_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70080400 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080400 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA114_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70080500 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080500 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA114_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s3: i2s@70080600 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080600 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA114_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s4: i2s@70080700 { + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; + reg = <0x70080700 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA114_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; + status = "disabled"; + }; + }; + + mipi: mipi@700e3000 { + compatible = "nvidia,tegra114-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; + #nvidia,mipi-calibrate-cells = <1>; }; sdhci@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; - interrupts = <0 14 0x04>; - clocks = <&tegra_car 14>; - status = "disable"; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + status = "disabled"; }; sdhci@78000200 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000200 0x200>; - interrupts = <0 15 0x04>; - clocks = <&tegra_car 9>; - status = "disable"; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + status = "disabled"; }; sdhci@78000400 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000400 0x200>; - interrupts = <0 19 0x04>; - clocks = <&tegra_car 69>; - status = "disable"; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + status = "disabled"; }; sdhci@78000600 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000600 0x200>; - interrupts = <0 31 0x04>; - clocks = <&tegra_car 15>; - status = "disable"; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disabled"; }; usb@7d000000 { - compatible = "nvidia,tegra114-ehci"; + compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d000000 0x4000>; - interrupts = <52>; + interrupts = ; phy_type = "utmi"; - clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + clocks = <&tegra_car TEGRA114_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,phy = <&phy1>; status = "disabled"; }; - usb@7d004000 { - compatible = "nvidia,tegra114-ehci"; - reg = <0x7d004000 0x4000>; - interrupts = <53>; - phy_type = "hsic"; - clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d000000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USBD>, + <&tegra_car TEGRA114_CLK_PLL_U>, + <&tegra_car TEGRA114_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 22>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + nvidia,has-utmi-pad-registers; status = "disabled"; }; usb@7d008000 { - compatible = "nvidia,tegra114-ehci"; + compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d008000 0x4000>; - interrupts = <129>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@7d008000 { + compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000 0x7d000000 0x4000>; phy_type = "utmi"; - clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + clocks = <&tegra_car TEGRA114_CLK_USB3>, + <&tegra_car TEGRA114_CLK_PLL_U>, + <&tegra_car TEGRA114_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; status = "disabled"; }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = + , + , + , + ; + interrupt-parent = <&gic>; + }; }; -- cgit v1.1 From 3b8c1b3b2220bcb78a7ce9b6d76d11ec43ec0006 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:53 -0600 Subject: ARM: tegra: pull Tegra124 SoC DT from Linux v4.7 The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * USB phy_type property is aligned with the kernel, so board files are updated so the final DT content doesn't change. I'm not convinved that Nyan uses HSIC phy_type. However, I'd rather this change be a no-op, and any DT bug-fixes be separate. * Sync misc changes from the kernel: missing DT content, minor compatible value fixes, typos. Remaining deltas relative to the Linux DT: * U-Boot uses #address-cells/#size-cells of 1 whereas the kernel uses 2. I believe U-Boot's DT parsing currently assumes that these values match the physical address size, so I didn't synchronize this part of the DT. * U-Boot uses the original XUSB PHY DT binding, wherease the kernel DT has moved to a newer version. Thus, XUSB client nodes include properties names phys and phy-names that do not appear in the kernel, and don't include pad definitions in the padctl node. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/dts/tegra124-nyan.dtsi | 2 ++ arch/arm/dts/tegra124.dtsi | 59 ++++++++++++++++++++++++++++++++++++----- 2 files changed, 54 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi index 780131f..51895e4 100644 --- a/arch/arm/dts/tegra124-nyan.dtsi +++ b/arch/arm/dts/tegra124-nyan.dtsi @@ -424,10 +424,12 @@ usb@7d004000 { /* Internal webcam. */ status = "okay"; + phy_type = "hsic"; }; usb-phy@7d004000 { status = "okay"; + phy_type = "hsic"; vbus-supply = <&vdd_run_cam>; }; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index 275a509..83d6348 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -196,13 +196,18 @@ lic: interrupt-controller@60004000 { compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; + reg = <0x0 0x60004000 0x0 0x100>, + <0x0 0x60004100 0x0 0x100>, + <0x0 0x60004200 0x0 0x100>, + <0x0 0x60004300 0x0 0x100>, + <0x0 0x60004400 0x0 0x100>; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; }; timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; reg = <0x60005000 0x400>; interrupts = , , @@ -316,7 +321,7 @@ * driver and APB DMA based serial driver for higher baudrate * and performace. To enable the 8250 based driver, the compatible * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the comptible is + * the APB DMA based serial driver, the compatible is * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". */ uarta: serial@70006000 { @@ -399,10 +404,15 @@ i2c@7000c400 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; reg = <0x7000c400 0x100>; - interrupts = <0 84 0x04>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car 54>; + clocks = <&tegra_car TEGRA124_CLK_I2C2>; + clock-names = "div-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -631,6 +641,41 @@ status = "disabled"; }; + usb@70090000 { + compatible = "nvidia,tegra124-xusb"; + reg = <0x70090000 0x8000>, + <0x70098000 0x1000>, + <0x70099000 0x1000>; + reg-names = "hcd", "fpci", "ipfs"; + + interrupts = , + ; + + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_host_src", + "xusb_falcon_src", "xusb_ss", + "xusb_ss_div2", "xusb_ss_src", + "xusb_hs_src", "xusb_fs_src", + "pll_u_480m", "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 156>, + <&tegra_car 143>; + reset-names = "xusb_host", "xusb_ss", "xusb_src"; + + nvidia,xusb-padctl = <&padctl>; + + status = "disabled"; + }; + padctl: padctl@7009f000 { compatible = "nvidia,tegra124-xusb-padctl"; reg = <0x7009f000 0x1000>; @@ -820,7 +865,7 @@ }; usb@7d000000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d000000 0x4000>; interrupts = ; phy_type = "utmi"; @@ -857,10 +902,10 @@ }; usb@7d004000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d004000 0x4000>; interrupts = ; - phy_type = "hsic"; + phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB2>; resets = <&tegra_car 58>; reset-names = "usb"; -- cgit v1.1 From ee562dc34e42667ec544be7e45b226a1bbe59134 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:54 -0600 Subject: ARM: tegra: pull Tegra210 SoC DT from Linux v4.7 The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Brought in the correct Tegra210 CAR binding; the old file in U-Boot appears to be a renamed version of the Tegra124 bindings rather than the real Tegra210 version. * Conversion of SPI and UART nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot, including separation of the Tegra LIC (Legacy IRQ controller) and GIC. * Node sort order fixes. Remaining deltas relative to the Linux DT: * U-Boot has enabled PCIe for Tegra210, but the kernel hasn't yet. * The GPIO node compatible value in the kernel explicitly includes Tegra124 values whereas U-Boot does not. I'll send a kernel patch to correct this. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/dts/tegra210.dtsi | 693 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 613 insertions(+), 80 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index fd4cc79..229fed0 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -1,14 +1,13 @@ #include #include +#include #include #include #include -#include "skeleton.dtsi" - / { compatible = "nvidia,tegra210"; - interrupt-parent = <&gic>; + interrupt-parent = <&lic>; #address-cells = <2>; #size-cells = <2>; @@ -78,6 +77,201 @@ }; }; + host1x@50000000 { + compatible = "nvidia,tegra210-host1x", "simple-bus"; + reg = <0x0 0x50000000 0x0 0x00034000>; + interrupts = , /* syncpt */ + ; /* general */ + clocks = <&tegra_car TEGRA210_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; + + dpaux1: dpaux@54040000 { + compatible = "nvidia,tegra210-dpaux"; + reg = <0x0 0x54040000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, + <&tegra_car TEGRA210_CLK_PLL_DP>; + clock-names = "dpaux", "parent"; + resets = <&tegra_car 207>; + reset-names = "dpaux"; + status = "disabled"; + }; + + vi@54080000 { + compatible = "nvidia,tegra210-vi"; + reg = <0x0 0x54080000 0x0 0x00040000>; + interrupts = ; + status = "disabled"; + }; + + tsec@54100000 { + compatible = "nvidia,tegra210-tsec"; + reg = <0x0 0x54100000 0x0 0x00040000>; + }; + + dc@54200000 { + compatible = "nvidia,tegra210-dc"; + reg = <0x0 0x54200000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DISP1>, + <&tegra_car TEGRA210_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DC>; + + nvidia,head = <0>; + }; + + dc@54240000 { + compatible = "nvidia,tegra210-dc"; + reg = <0x0 0x54240000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DISP2>, + <&tegra_car TEGRA210_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + iommus = <&mc TEGRA_SWGROUP_DCB>; + + nvidia,head = <1>; + }; + + dsi@54300000 { + compatible = "nvidia,tegra210-dsi"; + reg = <0x0 0x54300000 0x0 0x00040000>; + clocks = <&tegra_car TEGRA210_CLK_DSIA>, + <&tegra_car TEGRA210_CLK_DSIALP>, + <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + vic@54340000 { + compatible = "nvidia,tegra210-vic"; + reg = <0x0 0x54340000 0x0 0x00040000>; + status = "disabled"; + }; + + nvjpg@54380000 { + compatible = "nvidia,tegra210-nvjpg"; + reg = <0x0 0x54380000 0x0 0x00040000>; + status = "disabled"; + }; + + dsi@54400000 { + compatible = "nvidia,tegra210-dsi"; + reg = <0x0 0x54400000 0x0 0x00040000>; + clocks = <&tegra_car TEGRA210_CLK_DSIB>, + <&tegra_car TEGRA210_CLK_DSIBLP>, + <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + nvdec@54480000 { + compatible = "nvidia,tegra210-nvdec"; + reg = <0x0 0x54480000 0x0 0x00040000>; + status = "disabled"; + }; + + nvenc@544c0000 { + compatible = "nvidia,tegra210-nvenc"; + reg = <0x0 0x544c0000 0x0 0x00040000>; + status = "disabled"; + }; + + tsec@54500000 { + compatible = "nvidia,tegra210-tsec"; + reg = <0x0 0x54500000 0x0 0x00040000>; + status = "disabled"; + }; + + sor@54540000 { + compatible = "nvidia,tegra210-sor"; + reg = <0x0 0x54540000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_SOR0>, + <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, + <&tegra_car TEGRA210_CLK_PLL_DP>, + <&tegra_car TEGRA210_CLK_SOR_SAFE>; + clock-names = "sor", "parent", "dp", "safe"; + resets = <&tegra_car 182>; + reset-names = "sor"; + status = "disabled"; + }; + + sor@54580000 { + compatible = "nvidia,tegra210-sor1"; + reg = <0x0 0x54580000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_SOR1>, + <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, + <&tegra_car TEGRA210_CLK_PLL_DP>, + <&tegra_car TEGRA210_CLK_SOR_SAFE>; + clock-names = "sor", "parent", "dp", "safe"; + resets = <&tegra_car 183>; + reset-names = "sor"; + status = "disabled"; + }; + + dpaux: dpaux@545c0000 { + compatible = "nvidia,tegra124-dpaux"; + reg = <0x0 0x545c0000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DPAUX>, + <&tegra_car TEGRA210_CLK_PLL_DP>; + clock-names = "dpaux", "parent"; + resets = <&tegra_car 181>; + reset-names = "dpaux"; + status = "disabled"; + }; + + isp@54600000 { + compatible = "nvidia,tegra210-isp"; + reg = <0x0 0x54600000 0x0 0x00040000>; + interrupts = ; + status = "disabled"; + }; + + isp@54680000 { + compatible = "nvidia,tegra210-isp"; + reg = <0x0 0x54680000 0x0 0x00040000>; + interrupts = ; + status = "disabled"; + }; + + i2c@546c0000 { + compatible = "nvidia,tegra210-i2c-vi"; + reg = <0x0 0x546c0000 0x0 0x00040000>; + interrupts = ; + status = "disabled"; + }; + }; + gic: interrupt-controller@50041000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -91,6 +285,51 @@ interrupt-parent = <&gic>; }; + gpu@57000000 { + compatible = "nvidia,gm20b"; + reg = <0x0 0x57000000 0x0 0x01000000>, + <0x0 0x58000000 0x0 0x01000000>; + interrupts = , + ; + interrupt-names = "stall", "nonstall"; + clocks = <&tegra_car TEGRA210_CLK_GPU>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, + <&tegra_car TEGRA210_CLK_PLL_G_REF>; + clock-names = "gpu", "pwr", "ref"; + resets = <&tegra_car 184>; + reset-names = "gpu"; + + iommus = <&mc TEGRA_SWGROUP_GPU>; + + status = "disabled"; + }; + + lic: interrupt-controller@60004000 { + compatible = "nvidia,tegra210-ictlr"; + reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ + <0x0 0x60004100 0x0 0x40>, /* secondary controller */ + <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ + <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ + <0x0 0x60004400 0x0 0x40>, /* quinary controller */ + <0x0 0x60004500 0x0 0x40>; /* senary controller */ + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + timer@60005000 { + compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; + }; + tegra_car: clock@60006000 { compatible = "nvidia,tegra210-car"; reg = <0x0 0x60006000 0x0 0x1000>; @@ -98,6 +337,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra210-flowctrl"; + reg = <0x0 0x60007000 0x0 0x1000>; + }; + gpio: gpio@6000d000 { compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; @@ -115,74 +359,79 @@ interrupt-controller; }; - i2c@7000c000 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c000 0x0 0x100>; - interrupts = <0 38 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 12>; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c400 0x0 0x100>; - interrupts = <0 84 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 54>; - status = "disabled"; + apbdma: dma@60020000 { + compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; + reg = <0x0 0x60020000 0x0 0x1400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_APBDMA>; + clock-names = "dma"; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; }; - i2c@7000c500 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c500 0x0 0x100>; - interrupts = <0 92 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 67>; - status = "disabled"; + apbmisc@70000800 { + compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; + reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ + <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ }; - i2c@7000c700 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c700 0x0 0x100>; - interrupts = <0 120 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 103>; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d000 0x0 0x100>; - interrupts = <0 53 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 47>; - status = "disabled"; - }; - - i2c@7000d100 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d100 0x0 0x100>; - interrupts = <0 53 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 47>; - status = "disabled"; + pinmux: pinmux@700008d4 { + compatible = "nvidia,tegra210-pinmux"; + reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ + <0x0 0x70003000 0x0 0x294>; /* Mux registers */ }; + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performance. To enable the 8250 based driver, the compatible + * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable + * the APB DMA based serial driver, the compatible is + * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". + */ uarta: serial@70006000 { compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006000 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_UARTA>; + clock-names = "serial"; resets = <&tegra_car 6>; reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -192,8 +441,11 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_UARTB>; + clock-names = "serial"; resets = <&tegra_car 7>; reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -203,8 +455,11 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_UARTC>; + clock-names = "serial"; resets = <&tegra_car 55>; reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -214,66 +469,222 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_UARTD>; + clock-names = "serial"; resets = <&tegra_car 65>; reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pwm: pwm@7000a000 { + compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; + reg = <0x0 0x7000a000 0x0 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA210_CLK_PWM>; + clock-names = "pwm"; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000c000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_I2C1>; + clock-names = "div-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000c400 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_I2C2>; + clock-names = "div-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000c500 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_I2C3>; + clock-names = "div-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000c700 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_I2C4>; + clock-names = "div-clk"; + resets = <&tegra_car 103>; + reset-names = "i2c"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000d000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_I2C5>; + clock-names = "div-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d100 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000d100 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_I2C6>; + clock-names = "div-clk"; + resets = <&tegra_car 166>; + reset-names = "i2c"; + dmas = <&apbdma 30>, <&apbdma 30>; + dma-names = "rx", "tx"; status = "disabled"; }; spi@7000d400 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d400 0x0 0x200>; - interrupts = <0 59 0x04>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA210_CLK_SBC1>; + clock-names = "spi"; resets = <&tegra_car 41>; reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; }; spi@7000d600 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d600 0x0 0x200>; - interrupts = <0 82 0x04>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA210_CLK_SBC2>; + clock-names = "spi"; resets = <&tegra_car 44>; reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; }; spi@7000d800 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d800 0x0 0x200>; - interrupts = <0 83 0x04>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA210_CLK_SBC3>; + clock-names = "spi"; resets = <&tegra_car 46>; reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; }; spi@7000da00 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000da00 0x0 0x200>; - interrupts = <0 93 0x04>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA210_CLK_SBC4>; + clock-names = "spi"; resets = <&tegra_car 68>; reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; }; - spi@70410000 { - compatible = "nvidia,tegra210-qspi"; - reg = <0x0 0x70410000 0x0 0x1000>; - interrupts = <0 10 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 211>; + rtc@7000e000 { + compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; + reg = <0x0 0x7000e000 0x0 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_RTC>; + clock-names = "rtc"; + }; + + pmc: pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + }; + + fuse@7000f800 { + compatible = "nvidia,tegra210-efuse"; + reg = <0x0 0x7000f800 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; + + mc: memory-controller@70019000 { + compatible = "nvidia,tegra210-mc"; + reg = <0x0 0x70019000 0x0 0x1000>; + clocks = <&tegra_car TEGRA210_CLK_MC>; + clock-names = "mc"; + + interrupts = ; + + #iommu-cells = <1>; + }; + + hda@70030000 { + compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; + reg = <0x0 0x70030000 0x0 0x10000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_HDA>, + <&tegra_car TEGRA210_CLK_HDA2HDMI>, + <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; status = "disabled"; }; @@ -286,64 +697,186 @@ }; sdhci@700b0000 { - compatible = "nvidia,tegra210-sdhci"; + compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = <0 14 0x04>; + interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; }; sdhci@700b0200 { - compatible = "nvidia,tegra210-sdhci"; + compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; - interrupts = <0 15 0x04>; + interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; }; sdhci@700b0400 { - compatible = "nvidia,tegra210-sdhci"; + compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; - interrupts = <0 19 0x04>; + interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; }; sdhci@700b0600 { - compatible = "nvidia,tegra210-sdhci"; + compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; - interrupts = <0 31 0x04>; + interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra210-mipi"; + reg = <0x0 0x700e3000 0x0 0x100>; + clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; + clock-names = "mipi-cal"; + #nvidia,mipi-calibrate-cells = <1>; + }; + + spi@70410000 { + compatible = "nvidia,tegra210-qspi"; + reg = <0x0 0x70410000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_QSPI>; + clock-names = "qspi"; + resets = <&tegra_car 211>; + reset-names = "qspi"; + dmas = <&apbdma 5>, <&apbdma 5>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + usb@7d000000 { - compatible = "nvidia,tegra210-ehci"; + compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x0 0x7d000000 0x0 0x4000>; - interrupts = <0 20 0x04>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA210_CLK_USBD>; + clock-names = "usb"; resets = <&tegra_car 22>; reset-names = "usb"; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x0 0x7d000000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA210_CLK_USBD>, + <&tegra_car TEGRA210_CLK_PLL_U>, + <&tegra_car TEGRA210_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 22>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + nvidia,has-utmi-pad-registers; status = "disabled"; }; usb@7d004000 { - compatible = "nvidia,tegra210-ehci"; + compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x0 0x7d004000 0x0 0x4000>; - interrupts = < 53 >; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA210_CLK_USB2>; + clock-names = "usb"; resets = <&tegra_car 58>; reset-names = "usb"; + nvidia,phy = <&phy2>; status = "disabled"; }; + + phy2: usb-phy@7d004000 { + compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x0 0x7d004000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA210_CLK_USB2>, + <&tegra_car TEGRA210_CLK_PLL_U>, + <&tegra_car TEGRA210_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + status = "disabled"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <3>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; }; -- cgit v1.1 From 6dbcc962e48e4f2395806469ba59f19fb18aa64a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:55 -0600 Subject: ARM: tegra: add peripheral clock init table Currently, Tegra peripheral drivers control two aspects of their HW module clock(s): 1) The clock enable/rate for the peripheral clock itself. 2) The system-level clock tree setup, i.e. the clock parent. Aspect 1 is reasonable, but aspect 2 is a system-level decision, not something that an individual peripheral driver should in general know about or influence. Such system-level knowledge ties the driver to a specific SoC implementation, even when they use generic APIs for clock manipulation, since they must have SoC-specific knowledge such as parent clock IDs. Limited exceptions exist, such as where peripheral HW is expected to dynamically switch between clock sources at run-time, such as CPU clock scaling or display clock conflict management in a multi-head scenario. This patch enhances the Tegra core code to perform system-level clock tree setup, in a similar fashion to the Linux kernel Tegra clock driver. This will allow future patches to simplify peripheral drivers by removing the clock parent setup logic. This change is required prior to converting peripheral drivers to use the standard clock APIs, since: 1) The clock uclass doesn't currently support a set_parent() operation. Adding one is possible, but not necessary at the moment. 2) The clock APIs retrieve all clock IDs from device tree, and the DT bindings for almost all peripherals only includes information about the relevant peripheral clocks, and not any potential parent clocks. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/clock.h | 6 ++++++ arch/arm/mach-tegra/clock.c | 15 +++++++++++++++ arch/arm/mach-tegra/tegra114/clock.c | 23 +++++++++++++++++++++++ arch/arm/mach-tegra/tegra124/clock.c | 23 +++++++++++++++++++++++ arch/arm/mach-tegra/tegra20/clock.c | 21 +++++++++++++++++++++ arch/arm/mach-tegra/tegra210/clock.c | 23 +++++++++++++++++++++++ arch/arm/mach-tegra/tegra30/clock.c | 23 +++++++++++++++++++++++ 7 files changed, 134 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 7daf8bc..e0737f5 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -362,6 +362,12 @@ struct clk_pll_info { }; extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; +struct periph_clk_init { + enum periph_id periph_id; + enum clock_id parent_clock_id; +}; +extern struct periph_clk_init periph_clk_init_table[]; + /** * Enable output clock for external peripherals * diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 36eabc8..597f628 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -612,6 +612,8 @@ int clock_verify(void) void clock_init(void) { + int i; + pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); @@ -630,6 +632,19 @@ void clock_init(void) debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]); debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); + + for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) { + enum periph_id periph_id; + enum clock_id parent; + int source, mux_bits, divider_bits; + + periph_id = periph_clk_init_table[i].periph_id; + parent = periph_clk_init_table[i].parent_clock_id; + + source = get_periph_clock_source(periph_id, parent, &mux_bits, + ÷r_bits); + clock_ll_set_source_bits(periph_id, mux_bits, source); + } } static void set_avp_clock_source(u32 src) diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index e6ef873..6620206 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -699,3 +699,26 @@ void arch_timer_init(void) writel(val, &sysctr->cntcr); debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); } + +struct periph_clk_init periph_clk_init_table[] = { + { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, + { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, + { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, + { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ }, + { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C2, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C3, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C4, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C5, CLOCK_ID_PERIPH }, + { -1, }, +}; diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 1e71146..84b679c 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -1107,3 +1107,26 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) return NULL; } + +struct periph_clk_init periph_clk_init_table[] = { + { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, + { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, + { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, + { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ }, + { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C2, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C3, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C4, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C5, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C6, CLOCK_ID_PERIPH }, + { -1, }, +}; diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index cd9fb9a..d11e89b 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -717,3 +717,24 @@ int tegra_plle_enable(void) return 0; } + +struct periph_clk_init periph_clk_init_table[] = { + { PERIPH_ID_SPI1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, + { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, + { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ }, + { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C2, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C3, CLOCK_ID_PERIPH }, + { -1, }, +}; diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index f0052e7..d51c148 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1225,3 +1225,26 @@ int tegra_plle_enable(void) return 0; } + +struct periph_clk_init periph_clk_init_table[] = { + { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, + { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, + { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, + { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ }, + { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C2, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C3, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C4, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C5, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C6, CLOCK_ID_PERIPH }, + { -1, }, +}; diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 1f104f2..52a6dce 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -763,3 +763,26 @@ int tegra_plle_enable(void) return 0; } + +struct periph_clk_init periph_clk_init_table[] = { + { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, + { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, + { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, + { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, + { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, + { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, + { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ }, + { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C2, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C3, CLOCK_ID_PERIPH }, + { PERIPH_ID_I2C4, CLOCK_ID_PERIPH }, + { -1, }, +}; -- cgit v1.1 From d0ad8a5cbfe8d52339ac5bea3617af21d2fd079a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:45:56 -0600 Subject: ARM: tegra: add APIs the clock uclass driver will need A future patch will implement a clock uclass driver for Tegra. That driver will call into Tegra's existing clock code to simplify the transition; this avoids tieing the clock uclass patches into significant refactoring of the existing custom clock API implementation. Some of the Tegra clock APIs that manipulate peripheral clocks require both the peripheral clock ID and parent clock ID to be passed in together. However, the clock uclass API does not require any such "parent" parameter, so the clock driver must determine this information itself. This patch implements new Tegra- specific clock API clock_get_periph_parent() for this purpose. The new API is implemented in the core Tegra clock code rather than SoC- specific clock code. The implementation uses various SoC-/clock-specific data. That data is only available in SoC-specific clock code. Consequently, two new internal APIs are added that enable the core clock code to retrieve this information from the SoC-specific clock code. Due to the structure of the Tegra clock code, this leads to some unfortunate code duplication. However, this situation predates this patch. Ideally, future work will de-duplicate the Tegra clock code, and migrate it into drivers/clk/tegra. However, such refactoring is kept separate from this series. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/clock.h | 40 +++++++++++++++++ arch/arm/mach-tegra/clock.c | 37 ++++++++++++++++ arch/arm/mach-tegra/tegra114/clock.c | 64 ++++++++++++++++++++------- arch/arm/mach-tegra/tegra124/clock.c | 64 ++++++++++++++++++++------- arch/arm/mach-tegra/tegra20/clock.c | 76 +++++++++++++++++++++++---------- arch/arm/mach-tegra/tegra210/clock.c | 64 ++++++++++++++++++++------- arch/arm/mach-tegra/tegra30/clock.c | 64 ++++++++++++++++++++------- 7 files changed, 323 insertions(+), 86 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index e0737f5..388afcb 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -187,6 +187,16 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, unsigned divisor); /** + * Returns the current parent clock ID of a given peripheral. This can be + * useful in order to call clock_*_periph_*() from generic code that has no + * specific knowledge of system-level clock tree structure. + * + * @param periph_id peripheral to query + * @return clock ID of the peripheral's current parent clock + */ +enum clock_id clock_get_periph_parent(enum periph_id periph_id); + +/** * Start a peripheral PLL clock at the given rate. This also resets the * peripheral. * @@ -284,6 +294,36 @@ u32 *get_periph_source_reg(enum periph_id periph_id); /* Returns a pointer to the given 'simple' PLL */ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); +/* + * Given a peripheral ID, determine where the mux bits are in the peripheral + * clock's register, the number of divider bits the clock has, and the SoC- + * specific clock type. + * + * This is an internal API between the core Tegra clock code and the SoC- + * specific clock code. + * + * @param periph_id peripheral to query + * @param mux_bits Set to number of bits in mux register + * @param divider_bits Set to the relevant MASK_BITS_* value + * @param type Set to the SoC-specific clock type + * @return 0 on success, -1 on error + */ +int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, + int *divider_bits, int *type); + +/* + * Given a peripheral ID and clock source mux value, determine the clock_id + * of that peripheral's parent. + * + * This is an internal API between the core Tegra clock code and the SoC- + * specific clock code. + * + * @param periph_id peripheral to query + * @param source raw clock source mux value + * @return the CLOCK_ID_* value @source represents + */ +enum clock_id get_periph_clock_id(enum periph_id periph_id, int source); + /** * Given a peripheral ID and the required source clock, this returns which * value should be programmed into the source mux for that peripheral. diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 597f628..cf8bc38 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -206,6 +206,29 @@ int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, return 0; } +static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits) +{ + u32 *reg = get_periph_source_reg(periph_id); + u32 val = readl(reg); + + switch (mux_bits) { + case MASK_BITS_31_30: + val >>= OUT_CLK_SOURCE_31_30_SHIFT; + val &= OUT_CLK_SOURCE_31_30_MASK; + return val; + case MASK_BITS_31_29: + val >>= OUT_CLK_SOURCE_31_29_SHIFT; + val &= OUT_CLK_SOURCE_31_29_MASK; + return val; + case MASK_BITS_31_28: + val >>= OUT_CLK_SOURCE_31_28_SHIFT; + val &= OUT_CLK_SOURCE_31_28_MASK; + return val; + default: + return -1; + } +} + void clock_ll_set_source(enum periph_id periph_id, unsigned source) { clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source); @@ -363,6 +386,20 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, return 0; } +enum clock_id clock_get_periph_parent(enum periph_id periph_id) +{ + int err, mux_bits, divider_bits, type; + int source; + + err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type); + if (err) + return CLOCK_ID_NONE; + + source = clock_ll_get_source_bits(periph_id, mux_bits); + + return get_periph_clock_id(periph_id, source); +} + unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, enum clock_id parent, unsigned rate, int *extra_div) { diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 6620206..177ab6b 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -496,6 +496,51 @@ u32 *get_periph_source_reg(enum periph_id periph_id) return &clkrst->crc_clk_src[internal_id]; } +int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, + int *divider_bits, int *type) +{ + enum periphc_internal_id internal_id; + + if (!clock_periph_id_isvalid(periph_id)) + return -1; + + internal_id = periph_id_to_internal_id[periph_id]; + if (!periphc_internal_id_isvalid(internal_id)) + return -1; + + *type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(*type)) + return -1; + + *mux_bits = clock_source[*type][CLOCK_MAX_MUX]; + + if (*type == CLOCK_TYPE_PCMT16) + *divider_bits = 16; + else + *divider_bits = 8; + + return 0; +} + +enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) +{ + enum periphc_internal_id internal_id; + int type; + + if (!clock_periph_id_isvalid(periph_id)) + return CLOCK_ID_NONE; + + internal_id = periph_id_to_internal_id[periph_id]; + if (!periphc_internal_id_isvalid(internal_id)) + return CLOCK_ID_NONE; + + type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(type)) + return CLOCK_ID_NONE; + + return clock_source[type][source]; +} + /** * Given a peripheral ID and the required source clock, this returns which * value should be programmed into the source mux for that peripheral. @@ -512,23 +557,10 @@ int get_periph_clock_source(enum periph_id periph_id, enum clock_id parent, int *mux_bits, int *divider_bits) { enum clock_type_id type; - enum periphc_internal_id internal_id; - int mux; - - assert(clock_periph_id_isvalid(periph_id)); + int mux, err; - internal_id = periph_id_to_internal_id[periph_id]; - assert(periphc_internal_id_isvalid(internal_id)); - - type = clock_periph_type[internal_id]; - assert(clock_type_id_isvalid(type)); - - *mux_bits = clock_source[type][CLOCK_MAX_MUX]; - - if (type == CLOCK_TYPE_PCMT16) - *divider_bits = 16; - else - *divider_bits = 8; + err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type); + assert(!err); for (mux = 0; mux < CLOCK_MAX_MUX; mux++) if (clock_source[type][mux] == parent) diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 84b679c..5e44061 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -642,6 +642,51 @@ u32 *get_periph_source_reg(enum periph_id periph_id) } } +int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, + int *divider_bits, int *type) +{ + enum periphc_internal_id internal_id; + + if (!clock_periph_id_isvalid(periph_id)) + return -1; + + internal_id = periph_id_to_internal_id[periph_id]; + if (!periphc_internal_id_isvalid(internal_id)) + return -1; + + *type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(*type)) + return -1; + + *mux_bits = clock_source[*type][CLOCK_MAX_MUX]; + + if (*type == CLOCK_TYPE_PC2CC3M_T16) + *divider_bits = 16; + else + *divider_bits = 8; + + return 0; +} + +enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) +{ + enum periphc_internal_id internal_id; + int type; + + if (!clock_periph_id_isvalid(periph_id)) + return CLOCK_ID_NONE; + + internal_id = periph_id_to_internal_id[periph_id]; + if (!periphc_internal_id_isvalid(internal_id)) + return CLOCK_ID_NONE; + + type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(type)) + return CLOCK_ID_NONE; + + return clock_source[type][source]; +} + /** * Given a peripheral ID and the required source clock, this returns which * value should be programmed into the source mux for that peripheral. @@ -658,23 +703,10 @@ int get_periph_clock_source(enum periph_id periph_id, enum clock_id parent, int *mux_bits, int *divider_bits) { enum clock_type_id type; - enum periphc_internal_id internal_id; - int mux; - - assert(clock_periph_id_isvalid(periph_id)); - - internal_id = periph_id_to_internal_id[periph_id]; - assert(periphc_internal_id_isvalid(internal_id)); - - type = clock_periph_type[internal_id]; - assert(clock_type_id_isvalid(type)); + int mux, err; - *mux_bits = clock_source[type][CLOCK_MAX_MUX]; - - if (type == CLOCK_TYPE_PC2CC3M_T16) - *divider_bits = 16; - else - *divider_bits = 8; + err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type); + assert(!err); for (mux = 0; mux < CLOCK_MAX_MUX; mux++) if (clock_source[type][mux] == parent) diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index d11e89b..ec04cf5 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -413,46 +413,78 @@ u32 *get_periph_source_reg(enum periph_id periph_id) return &clkrst->crc_clk_src[internal_id]; } -/** - * Given a peripheral ID and the required source clock, this returns which - * value should be programmed into the source mux for that peripheral. - * - * There is special code here to handle the one source type with 5 sources. - * - * @param periph_id peripheral to start - * @param source PLL id of required parent clock - * @param mux_bits Set to number of bits in mux register: 2 or 4 - * @param divider_bits Set to number of divider bits (8 or 16) - * @return mux value (0-4, or -1 if not found) - */ -int get_periph_clock_source(enum periph_id periph_id, - enum clock_id parent, int *mux_bits, int *divider_bits) +int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, + int *divider_bits, int *type) { - enum clock_type_id type; enum periphc_internal_id internal_id; - int mux; - assert(clock_periph_id_isvalid(periph_id)); + if (!clock_periph_id_isvalid(periph_id)) + return -1; internal_id = periph_id_to_internal_id[periph_id]; - assert(periphc_internal_id_isvalid(internal_id)); + if (!periphc_internal_id_isvalid(internal_id)) + return -1; - type = clock_periph_type[internal_id]; - assert(clock_type_id_isvalid(type)); + *type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(*type)) + return -1; /* * Special cases here for the clock with a 4-bit source mux and I2C * with its 16-bit divisor */ - if (type == CLOCK_TYPE_PCXTS) + if (*type == CLOCK_TYPE_PCXTS) *mux_bits = MASK_BITS_31_28; else *mux_bits = MASK_BITS_31_30; - if (type == CLOCK_TYPE_PCMT16) + if (*type == CLOCK_TYPE_PCMT16) *divider_bits = 16; else *divider_bits = 8; + return 0; +} + +enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) +{ + enum periphc_internal_id internal_id; + int type; + + if (!clock_periph_id_isvalid(periph_id)) + return CLOCK_ID_NONE; + + internal_id = periph_id_to_internal_id[periph_id]; + if (!periphc_internal_id_isvalid(internal_id)) + return CLOCK_ID_NONE; + + type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(type)) + return CLOCK_ID_NONE; + + return clock_source[type][source]; +} + +/** + * Given a peripheral ID and the required source clock, this returns which + * value should be programmed into the source mux for that peripheral. + * + * There is special code here to handle the one source type with 5 sources. + * + * @param periph_id peripheral to start + * @param source PLL id of required parent clock + * @param mux_bits Set to number of bits in mux register: 2 or 4 + * @param divider_bits Set to number of divider bits (8 or 16) + * @return mux value (0-4, or -1 if not found) + */ +int get_periph_clock_source(enum periph_id periph_id, + enum clock_id parent, int *mux_bits, int *divider_bits) +{ + enum clock_type_id type; + int mux, err; + + err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type); + assert(!err); + for (mux = 0; mux < CLOCK_MAX_MUX; mux++) if (clock_source[type][mux] == parent) return mux; diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index d51c148..c8bb946 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -732,6 +732,51 @@ u32 *get_periph_source_reg(enum periph_id periph_id) return &clkrst->crc_clk_src_y[internal_id]; } +int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, + int *divider_bits, int *type) +{ + enum periphc_internal_id internal_id; + + if (!clock_periph_id_isvalid(periph_id)) + return -1; + + internal_id = periph_id_to_internal_id[periph_id]; + if (!periphc_internal_id_isvalid(internal_id)) + return -1; + + *type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(*type)) + return -1; + + *mux_bits = clock_source[*type][CLOCK_MAX_MUX]; + + if (*type == CLOCK_TYPE_PC2CC3M_T16) + *divider_bits = 16; + else + *divider_bits = 8; + + return 0; +} + +enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) +{ + enum periphc_internal_id internal_id; + int type; + + if (!clock_periph_id_isvalid(periph_id)) + return CLOCK_ID_NONE; + + internal_id = periph_id_to_internal_id[periph_id]; + if (!periphc_internal_id_isvalid(internal_id)) + return CLOCK_ID_NONE; + + type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(type)) + return CLOCK_ID_NONE; + + return clock_source[type][source]; +} + /** * Given a peripheral ID and the required source clock, this returns which * value should be programmed into the source mux for that peripheral. @@ -748,23 +793,10 @@ int get_periph_clock_source(enum periph_id periph_id, enum clock_id parent, int *mux_bits, int *divider_bits) { enum clock_type_id type; - enum periphc_internal_id internal_id; - int mux; - - assert(clock_periph_id_isvalid(periph_id)); + int mux, err; - internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); - assert(periphc_internal_id_isvalid(internal_id)); - - type = clock_periph_type[internal_id]; - assert(clock_type_id_isvalid(type)); - - *mux_bits = clock_source[type][CLOCK_MAX_MUX]; - - if (type == CLOCK_TYPE_PC2CC3M_T16) - *divider_bits = 16; - else - *divider_bits = 8; + err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type); + assert(!err); for (mux = 0; mux < CLOCK_MAX_MUX; mux++) if (clock_source[type][mux] == parent) diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 52a6dce..4fd8b8a 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -476,6 +476,51 @@ u32 *get_periph_source_reg(enum periph_id periph_id) return &clkrst->crc_clk_src[internal_id]; } +int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, + int *divider_bits, int *type) +{ + enum periphc_internal_id internal_id; + + if (!clock_periph_id_isvalid(periph_id)) + return -1; + + internal_id = periph_id_to_internal_id[periph_id]; + if (!periphc_internal_id_isvalid(internal_id)) + return -1; + + *type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(*type)) + return -1; + + *mux_bits = clock_source[*type][CLOCK_MAX_MUX]; + + if (*type == CLOCK_TYPE_PCMT16) + *divider_bits = 16; + else + *divider_bits = 8; + + return 0; +} + +enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) +{ + enum periphc_internal_id internal_id; + int type; + + if (!clock_periph_id_isvalid(periph_id)) + return CLOCK_ID_NONE; + + internal_id = periph_id_to_internal_id[periph_id]; + if (!periphc_internal_id_isvalid(internal_id)) + return CLOCK_ID_NONE; + + type = clock_periph_type[internal_id]; + if (!clock_type_id_isvalid(type)) + return CLOCK_ID_NONE; + + return clock_source[type][source]; +} + /** * Given a peripheral ID and the required source clock, this returns which * value should be programmed into the source mux for that peripheral. @@ -492,23 +537,10 @@ int get_periph_clock_source(enum periph_id periph_id, enum clock_id parent, int *mux_bits, int *divider_bits) { enum clock_type_id type; - enum periphc_internal_id internal_id; - int mux; - - assert(clock_periph_id_isvalid(periph_id)); - - internal_id = periph_id_to_internal_id[periph_id]; - assert(periphc_internal_id_isvalid(internal_id)); - - type = clock_periph_type[internal_id]; - assert(clock_type_id_isvalid(type)); + int mux, err; - *mux_bits = clock_source[type][CLOCK_MAX_MUX]; - - if (type == CLOCK_TYPE_PCMT16) - *divider_bits = 16; - else - *divider_bits = 8; + err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type); + assert(!err); for (mux = 0; mux < CLOCK_MAX_MUX; mux++) if (clock_source[type][mux] == parent) -- cgit v1.1 From 74686766847146e4408486c5e3ca8a1681b145c0 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 23 Sep 2016 16:44:51 -0600 Subject: ARM: tegra: fix clock_get_periph_rate() for UART clocks Make clock_get_periph_rate() return the correct value for UART clocks. This change needs to be applied before the patches that enable CONFIG_CLK for Tegra SoCs before Tegra186, since enabling that option causes ns16550_serial_ofdata_to_platdata() to rely on clk_get_rate() for UART clocks, and clk_get_rate() eventually calls clock_get_periph_rate(). This change is a rather horrible hack, as explained in the comment added to the clock driver. I've tried fixing this correctly for all clocks as described in that comment, but there's too much fallout elsewhere. I believe the clock driver has a number of bugs which all cancel each-other out, and unravelling that chain is too complex at present. This change is the smallest change that fixes clock_get_periph_rate() for UART clocks while guaranteeing no change in behaviour for any other clock, which avoids other regressions. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/mach-tegra/clock.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index cf8bc38..3bb7233 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -311,9 +311,43 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, enum clock_id parent) { u32 *reg = get_periph_source_reg(periph_id); + unsigned parent_rate = pll_rate[parent]; + int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT; + + switch (periph_id) { + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + case PERIPH_ID_UART5: +#ifdef CONFIG_TEGRA20 + /* There's no divider for these clocks in this SoC. */ + return parent_rate; +#else + /* + * This undoes the +2 in get_rate_from_divider() which I + * believe is incorrect. Ideally we would fix + * get_rate_from_divider(), but... Removing the +2 from + * get_rate_from_divider() would probably require remove the -2 + * from the tail of clk_get_divider() since I believe that's + * only there to invert get_rate_from_divider()'s +2. Observe + * how find_best_divider() uses those two functions together. + * However, doing so breaks other stuff, such as Seaboard's + * display, likely due to clock_set_pllout()'s call to + * clk_get_divider(). Attempting to fix that by making + * clock_set_pllout() subtract 2 from clk_get_divider()'s + * return value doesn't help. In summary this clock driver is + * quite broken but I'm afraid I have no idea how to fix it + * without completely replacing it. + */ + div -= 2; + break; +#endif + default: + break; + } - return get_rate_from_divider(pll_rate[parent], - (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT); + return get_rate_from_divider(parent_rate, div); } /** -- cgit v1.1 From 140a9eaff1f25fb0c19dae52a9431c109c45daa7 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 13 Sep 2016 10:46:00 -0600 Subject: ARM: tegra: enable standard clock/reset APIs everywhere Implementations of the standard clock and reset APIs are available on all Tegra SoCs now, so enable compilation of those uclasses. Enable the Tegra CAR drivers for all SoCs prior to the BPMP being available. This provides an implementation of those APIs everywhere. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/mach-tegra/Kconfig | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index fb4b32e..316feba 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -22,6 +22,7 @@ config TEGRA_IVC config TEGRA_COMMON bool "Tegra common options" + select CLK select DM select DM_ETH select DM_GPIO @@ -31,12 +32,20 @@ config TEGRA_COMMON select DM_PCI select DM_PCI_COMPAT select DM_PWM + select DM_RESET select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select MISC select OF_CONTROL select VIDCONSOLE_AS_LCD if DM_VIDEO +config TEGRA_NO_BPMP + bool "Tegra common options for SoCs without BPMP" + select TEGRA_CAR + select TEGRA_CAR_CLOCK + select TEGRA_CAR_RESET + config TEGRA_ARMV7_COMMON bool "Tegra 32-bit common options" select CPU_V7 @@ -44,6 +53,7 @@ config TEGRA_ARMV7_COMMON select SUPPORT_SPL select TEGRA_COMMON select TEGRA_GPIO + select TEGRA_NO_BPMP config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" @@ -74,13 +84,11 @@ config TEGRA210 bool "Tegra210 family" select TEGRA_GPIO select TEGRA_ARMV8_COMMON + select TEGRA_NO_BPMP config TEGRA186 bool "Tegra186 family" - select CLK select DM_MAILBOX - select DM_RESET - select MISC select TEGRA186_BPMP select TEGRA186_CLOCK select TEGRA186_GPIO -- cgit v1.1 From 2f6a7e8ce5df8b99d84bfd486c6f99d92322ce04 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 15 Sep 2016 12:19:37 -0600 Subject: ARM: tegra: fix USB ULPI PHY reset signal inversion confusion USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot. This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW. Cc: Marcel Ziswiler Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/dts/tegra20-colibri.dts | 3 ++- arch/arm/dts/tegra20-harmony.dts | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts index a291d93..777f63e 100644 --- a/arch/arm/dts/tegra20-colibri.dts +++ b/arch/arm/dts/tegra20-colibri.dts @@ -39,7 +39,8 @@ usb@c5004000 { statuc = "okay"; /* VBUS_LAN */ - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index cace743..5aec150 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -626,7 +626,8 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { -- cgit v1.1 From 002ddbffb6e51ea3291d7bf22eca6f847b40fa90 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 15 Sep 2016 12:19:38 -0600 Subject: ARM: tegra: fix USB controller aliases Some boards have a different set of USB controllers enabled in DT than the set referenced by /alias entries. This patch fixes that. For example, this avoids the following message while booting on Ventana, which is caused by the fact that the USB0 controller had no alias, and defaulted to wanting a sequence number of 0, which was later explicitly requested by the alias for USB controller 2. USB2: Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000' This didn't affect USB operation in any way though. Related, there's no need for the USB controller aliases to have an order that's different from the HW order, so re-order any aliases to match the HW ordering. This has the benefit that since USB controller 0 is the only one that supports device-mode in HW, and U-Boot only supports enabling device move on controller 0, there's now good synergy in the ordering! For Tegra20, that's not relevant at present since USB device mode doesn't work correctly on that SoC, but it will save some head-scratching later. This patch doesn't fix the colibri_t20 board, even though it has the same issue, since Marcel already sent a patch for that. Cc: Marcel Ziswiler Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren Tested-by: Marcel Ziswiler Tested-on: Harmony and Ventana --- arch/arm/dts/tegra20-harmony.dts | 3 ++- arch/arm/dts/tegra20-seaboard.dts | 5 +++-- arch/arm/dts/tegra20-trimslice.dts | 3 +-- arch/arm/dts/tegra20-ventana.dts | 4 +++- 4 files changed, 9 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index 5aec150..dcbde7c 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -15,8 +15,9 @@ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uartd; - usb0 = "/usb@c5008000"; + usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; + usb2 = "/usb@c5008000"; mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000200"; }; diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 1421051..77f5bb5 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -9,8 +9,9 @@ aliases { /* This defines the order of our ports */ - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; + usb0 = "/usb@c5000000"; + usb1 = "/usb@c5004000"; + usb2 = "/usb@c5008000"; i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index be64e66..7fb7dd0 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -11,8 +11,7 @@ }; aliases { - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; + usb0 = "/usb@c5000000"; mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000000"; spi0 = "/spi@7000c380"; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 3714456..85cd1e3 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -15,7 +15,9 @@ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uartd; - usb0 = "/usb@c5008000"; + usb0 = "/usb@c5000000"; + usb1 = "/usb@c5004000"; + usb2 = "/usb@c5008000"; mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000400"; }; -- cgit v1.1 From 6dca554f238d23d2c67873d850b7576e5971c5fd Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 15 Sep 2016 12:19:39 -0600 Subject: ARM: tegra: fix ULPI PHY on Ventana and Seaboard Commit ce02a71c2374 "tegra: dts: Sync tegra20 device tree files with Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure that U-Boot code could handle this. In practice, various code is missing, and various configuration options are not enabled, which causes U-Boot to hang when attempting to initialize this USB port. This patch enables ULPI PHY support on Ventana, and adds the required pinmux setup for the port to operate. Note that Ventana is so similar to Seaboard that this change is made in the Seaboard board file, which is shared with Ventana. Seaboard also has the ULPI USB port wired up in hardware, although to an internal port that often doesn't have anything attached to it. However, the DT nodes for the USB controller and PHY had different status property values, so the port was not initialized by U-Boot. Fix this inconsistency, and enable the ULPI port, just like in the Linux kernel DT. This likewise requires enabling ULPI support in the Seaboard defconfig. Cc: Marcel Ziswiler Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/dts/tegra20-seaboard.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 77f5bb5..341c7f3 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -784,7 +784,7 @@ }; usb@c5004000 { - status = "disabled"; + status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; }; -- cgit v1.1 From 8e5d804f890b32959cc9d9f9349ccd2ff4a744a0 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 23 Sep 2016 17:43:49 -0600 Subject: ARM: tegra: flush caches via SMC call On Tegra186, it is necessary to perform an SMC to fully flush all caches; flushing/cleaning by set/way is not enough. Implement the required hook to make this happen. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra186/Makefile | 1 + arch/arm/mach-tegra/tegra186/cache.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 arch/arm/mach-tegra/tegra186/cache.c (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile index 033d600..7f46a05 100644 --- a/arch/arm/mach-tegra/tegra186/Makefile +++ b/arch/arm/mach-tegra/tegra186/Makefile @@ -3,5 +3,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += ../board186.o +obj-y += cache.o obj-y += nvtboot_ll.o obj-y += nvtboot_mem.o diff --git a/arch/arm/mach-tegra/tegra186/cache.c b/arch/arm/mach-tegra/tegra186/cache.c new file mode 100644 index 0000000..adaed89 --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/cache.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#define SMC_SIP_INVOKE_MCE 0x82FFFF00 +#define MCE_SMC_ROC_FLUSH_CACHE 11 + +int __asm_flush_l3_cache(void) +{ + struct pt_regs regs = {0}; + + isb(); + + regs.regs[0] = SMC_SIP_INVOKE_MCE | MCE_SMC_ROC_FLUSH_CACHE; + smc_call(®s); + + return 0; +} -- cgit v1.1