From b699b01e5cf0f74f123dcc7090df232214dddf93 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Tue, 21 Oct 2014 13:51:58 +0800 Subject: arm: ls102xa: fixed a bus frequency setting error The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 4ce3808..989780d 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -91,7 +91,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) } do_fixup_by_prop_u32(blob, "device_type", "soc", - 4, "bus-frequency", busclk / 2, 1); + 4, "bus-frequency", busclk, 1); ft_fixup_enet_phy_connect_type(blob); -- cgit v1.1 From 306fa012794e68e568bd51b829d1754323e0b8aa Mon Sep 17 00:00:00 2001 From: chenhui zhao Date: Wed, 22 Oct 2014 18:20:22 +0800 Subject: arm: ls102xa: clear EPU registers for deep sleep After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +++++++ arch/arm/cpu/armv7/ls102xa/fsl_epu.c | 57 +++++++++++++++++++++++++ arch/arm/cpu/armv7/ls102xa/fsl_epu.h | 68 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + 5 files changed, 143 insertions(+) create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.c create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.h (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index d82ce8d..ae4f25d 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -7,6 +7,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o +obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index b7dde45..fae6c68 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -12,6 +12,8 @@ #include #include +#include "fsl_epu.h" + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_DISPLAY_CPUINFO) @@ -101,3 +103,17 @@ int cpu_eth_init(bd_t *bis) return 0; } + +int arch_cpu_init(void) +{ + void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + + /* + * After wakeup from deep sleep, Clear EPU registers + * as early as possible to prevent from possible issue. + * It's also safe to clear at normal boot. + */ + fsl_epu_clean(epu_base); + + return 0; +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c new file mode 100644 index 0000000..6212640 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c @@ -0,0 +1,57 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "fsl_epu.h" + +/** + * fsl_epu_clean - Clear EPU registers + */ +void fsl_epu_clean(void *epu_base) +{ + u32 offset; + + /* follow the exact sequence to clear the registers */ + /* Clear EPACRn */ + for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPEVTCRn */ + for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPGCR */ + out_be32(epu_base + EPGCR, 0); + + /* Clear EPSMCRn */ + for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCCRn */ + for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCMPRn */ + for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCTRn */ + for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPIMCRn */ + for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPXTRIGCRn */ + out_be32(epu_base + EPXTRIGCR, 0); + + /* Clear EPECRn */ + for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE) + out_be32(epu_base + offset, 0); +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h new file mode 100644 index 0000000..d658aad --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h @@ -0,0 +1,68 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_EPU_H +#define __FSL_EPU_H + +#include + +#define FSL_STRIDE_4B 4 +#define FSL_STRIDE_8B 8 + +/* Block offsets */ +#define EPU_BLOCK_OFFSET 0x00000000 + +/* EPGCR (Event Processor Global Control Register) */ +#define EPGCR 0x000 + +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */ +#define EPEVTCR0 0x050 +#define EPEVTCR9 0x074 +#define EPEVTCR_STRIDE FSL_STRIDE_4B + +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ +#define EPXTRIGCR 0x090 + +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */ +#define EPIMCR0 0x100 +#define EPIMCR31 0x17C +#define EPIMCR_STRIDE FSL_STRIDE_4B + +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */ +#define EPSMCR0 0x200 +#define EPSMCR15 0x278 +#define EPSMCR_STRIDE FSL_STRIDE_8B + +/* EPECR0-15 (Event Processor Event Control Registers) */ +#define EPECR0 0x300 +#define EPECR15 0x33C +#define EPECR_STRIDE FSL_STRIDE_4B + +/* EPACR0-15 (Event Processor Action Control Registers) */ +#define EPACR0 0x400 +#define EPACR15 0x43C +#define EPACR_STRIDE FSL_STRIDE_4B + +/* EPCCRi0-15 (Event Processor Counter Control Registers) */ +#define EPCCR0 0x800 +#define EPCCR15 0x83C +#define EPCCR31 0x87C +#define EPCCR_STRIDE FSL_STRIDE_4B + +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */ +#define EPCMPR0 0x900 +#define EPCMPR15 0x93C +#define EPCMPR31 0x97C +#define EPCMPR_STRIDE FSL_STRIDE_4B + +/* EPCTR0-31 (Event Processor Counter Register) */ +#define EPCTR0 0xA00 +#define EPCTR31 0xA7C +#define EPCTR_STRIDE FSL_STRIDE_4B + +void fsl_epu_clean(void *epu_base); + +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ba86eea..7d70c7b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -13,6 +13,7 @@ #define OCRAM_SIZE 0x00020000 #define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) -- cgit v1.1 From da419027afe8336284f5db9867a880dfb3b3ab26 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 31 Oct 2014 13:43:44 +0800 Subject: arm: ls102xa: Update PCIe dts node status The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 3 +++ arch/arm/include/asm/pcie_layerscape.h | 13 +++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm/include/asm/pcie_layerscape.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 7d70c7b..704d683 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -53,6 +53,9 @@ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h new file mode 100644 index 0000000..fb08578 --- /dev/null +++ b/arch/arm/include/asm/pcie_layerscape.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PCIE_LAYERSCAPE_H_ +#define __PCIE_LAYERSCAPE_H_ + +void pci_init_board(void); +void ft_pcie_setup(void *blob, bd_t *bd); + +#endif -- cgit v1.1 From 14d54dec1ba55d1b12c1fe17855d2ec5fd69734e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:43 +0800 Subject: arm: spl: Add I2C linker list in generic .lds On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/cpu/u-boot-spl.lds | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index a69b006..a8be204 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -32,6 +32,9 @@ SECTIONS } . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + } . = .; #ifdef CONFIG_SPL_DM -- cgit v1.1 From 50f0c6632527cbdc3c67f60a7f51ccba2564b567 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:45 +0800 Subject: kconfig: ls1021a: add SUPPORT_SPL Add SUPPORT_SPL feature for SD and NAND boot on LS1021AQDS and LS1021ATWR. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7a64b66..11ae5f8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -730,10 +730,12 @@ config TARGET_LS2085A_SIMU config TARGET_LS1021AQDS bool "Support ls1021aqds_nor" select CPU_V7 + select SUPPORT_SPL config TARGET_LS1021ATWR bool "Support ls1021atwr_nor" select CPU_V7 + select SUPPORT_SPL config TARGET_BALLOON3 bool "Support balloon3" -- cgit v1.1 From 86949c2b7c94542c20767c405fc458346bd3975b Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:47 +0800 Subject: arm: ls102xa: Add SD boot support for LS1021AQDS board This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang Signed-off-by: Jason Jin Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/spl.c | 33 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/spl.h | 20 ++++++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 arch/arm/cpu/armv7/ls102xa/spl.c create mode 100644 arch/arm/include/asm/arch-ls102xa/spl.h (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index ae4f25d..2e6a207 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -11,3 +11,4 @@ obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o +obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c new file mode 100644 index 0000000..1dfbf54 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#endif + return BOOT_DEVICE_NAND; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + case BOOT_DEVICE_NAND: + return 0; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} diff --git a/arch/arm/include/asm/arch-ls102xa/spl.h b/arch/arm/include/asm/arch-ls102xa/spl.h new file mode 100644 index 0000000..26e4ea1 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/spl.h @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_SPL_H__ +#define __ASM_ARCH_SPL_H__ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONENAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 +#define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10 + +#endif /* __ASM_ARCH_SPL_H__ */ -- cgit v1.1 From d612f0ab34b27be4ad50b1236fbd6c84450997f1 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:38:02 +0800 Subject: arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index b0c267c..98b268d 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -98,6 +98,7 @@ struct ccsr_gur { #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 +#define SCFG_QSPI_CLKSEL 0xc0100000 /* Supplemental Configuration Unit */ struct ccsr_scfg { -- cgit v1.1 From 8ab967b6c6007adbd30e58dfa9ef69154a351484 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:38:14 +0800 Subject: arm: ls102xa: Add NAND boot support for LS1021AQDS board This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 2 ++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +++++ 2 files changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 704d683..ef775cf 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -15,6 +15,8 @@ #define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_DCSRBAR 0x20000000 +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) + #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 98b268d..5abc3a1 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -29,6 +29,11 @@ #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) +#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 +#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 + +#define DCFG_DCSR_PORCR1 0 + struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; -- cgit v1.1 From a1c04e2785fe9843abcaeaa5d46f819215550d90 Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Mon, 20 Oct 2014 16:50:49 +0530 Subject: drivers: usb: Make usb device-tree fixup code architecture independent move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/" so that it works independent of architecture it is running on Signed-off-by: Ramneek Mehresh Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- arch/powerpc/cpu/mpc8xxx/fdt.c | 104 ----------------------------------------- 1 file changed, 104 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index c6b4d95..1c63f93 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -73,110 +73,6 @@ void ft_fixup_num_cores(void *blob) { } #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, - const char *phy_type, int start_offset) -{ - const char *compat_dr = "fsl-usb2-dr"; - const char *compat_mph = "fsl-usb2-mph"; - const char *prop_mode = "dr_mode"; - const char *prop_type = "phy_type"; - const char *node_type = NULL; - int node_offset; - int err; - - node_offset = fdt_node_offset_by_compatible(blob, - start_offset, compat_mph); - if (node_offset < 0) { - node_offset = fdt_node_offset_by_compatible(blob, - start_offset, compat_dr); - if (node_offset < 0) { - printf("WARNING: could not find compatible" - " node %s or %s: %s.\n", compat_mph, - compat_dr, fdt_strerror(node_offset)); - return -1; - } else - node_type = compat_dr; - } else - node_type = compat_mph; - - if (mode) { - err = fdt_setprop(blob, node_offset, prop_mode, mode, - strlen(mode) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_mode, node_type, fdt_strerror(err)); - } - - if (phy_type) { - err = fdt_setprop(blob, node_offset, prop_type, phy_type, - strlen(phy_type) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_type, node_type, fdt_strerror(err)); - } - - return node_offset; -} - -void fdt_fixup_dr_usb(void *blob, bd_t *bd) -{ - const char *modes[] = { "host", "peripheral", "otg" }; - const char *phys[] = { "ulpi", "utmi" }; - int usb_mode_off = -1; - int usb_phy_off = -1; - char str[5]; - int i, j; - - for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) { - const char *dr_mode_type = NULL; - const char *dr_phy_type = NULL; - int mode_idx = -1, phy_idx = -1; - snprintf(str, 5, "%s%d", "usb", i); - if (hwconfig(str)) { - for (j = 0; j < ARRAY_SIZE(modes); j++) { - if (hwconfig_subarg_cmp(str, "dr_mode", - modes[j])) { - mode_idx = j; - break; - } - } - - for (j = 0; j < ARRAY_SIZE(phys); j++) { - if (hwconfig_subarg_cmp(str, "phy_type", - phys[j])) { - phy_idx = j; - break; - } - } - - if (mode_idx < 0 && phy_idx < 0) { - printf("WARNING: invalid phy or mode\n"); - return; - } - - if (mode_idx > -1) - dr_mode_type = modes[mode_idx]; - - if (phy_idx > -1) - dr_phy_type = phys[phy_idx]; - } - - usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, - dr_mode_type, NULL, usb_mode_off); - - if (usb_mode_off < 0) - return; - - usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, - NULL, dr_phy_type, usb_phy_off); - - if (usb_phy_off < 0) - return; - } -} -#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */ - /* * update crypto node properties to a specified revision of the SEC * called with sec_rev == 0 if not on an E processor -- cgit v1.1 From b8e5c7f94af6b178946ae01ba36ac7fac1e86ec7 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:54 +0800 Subject: ARM: HYP/non-sec: add the pen address BE mode support. For some SoCs, the pen address register maybe in BE mode and the CPUs are in LE mode. This patch adds BE mode support for smp pen address. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/cpu/armv7/nonsec_virt.S | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 745670e..1ab5d54 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -191,6 +191,9 @@ ENTRY(smp_waitloop) wfi ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address ldr r1, [r1] +#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN + rev r1, r1 +#endif cmp r0, r1 @ make sure we dont execute this code beq smp_waitloop @ again (due to a spurious wakeup) mov r0, r1 -- cgit v1.1 From 73a1cb27c0d9e93d97cd7a344fd341f638ba3a2a Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:55 +0800 Subject: ARM: HYP/non-sec: Fix the ARCH Timer frequency setting. For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 1ab5d54..30d81db 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -169,11 +169,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) - ldreq r1, =CONFIG_SYS_CLK_FREQ + ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif -- cgit v1.1 From 290e6e921f255fdee072d21539bbad16b9a3e714 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:56 +0800 Subject: ls1021a: adding a secondary core boot address and kick functions Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index fae6c68..ce2d92f 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -117,3 +117,21 @@ int arch_cpu_init(void) return 0; } + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +/* Set the address at which the secondary core starts from.*/ +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->scratchrw[0], addr); +} + +/* Release the secondary core from holdoff state and kick it */ +void smp_kick_all_cpus(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->brrl, 0x2); +} +#endif -- cgit v1.1 From 1a2826f6e02d0d3ec97b77b5b13c13d2ac27fb9d Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:57 +0800 Subject: ls102xa: changing a few targets' configurations. Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 2 ++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++ 2 files changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ef775cf..0533a83 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -11,6 +11,8 @@ #define OCRAM_BASE_ADDR 0x10000000 #define OCRAM_SIZE 0x00020000 +#define OCRAM_BASE_S_ADDR 0x10010000 +#define OCRAM_S_SIZE 0x00010000 #define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_DCSRBAR 0x20000000 diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 5abc3a1..697d4ca 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -17,6 +17,9 @@ #define SOC_VER_LS1021 0x11 #define SOC_VER_LS1022 0x12 +#define CCSR_BRR_OFFSET 0xe4 +#define CCSR_SCRATCHRW1_OFFSET 0x200 + #define RCWSR0_SYS_PLL_RAT_SHIFT 25 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f #define RCWSR0_MEM_PLL_RAT_SHIFT 16 -- cgit v1.1 From e87f3b308c454f6e78b02da857936c7d012c385b Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:58 +0800 Subject: ARM: ls102xa: allow all the peripheral access permission as R/W. The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/arch-ls102xa/ns_access.h | 118 ++++++++++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 arch/arm/include/asm/arch-ls102xa/ns_access.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 0533a83..5e934da 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -21,6 +21,7 @@ #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h new file mode 100644 index 0000000..b53f699 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -0,0 +1,118 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_NS_ACCESS_H_ +#define __FSL_NS_ACCESS_H_ + +enum csu_cslx_access { + CSU_NS_SUP_R = 0x08, + CSU_NS_SUP_W = 0x80, + CSU_NS_SUP_RW = 0x88, + CSU_NS_USER_R = 0x04, + CSU_NS_USER_W = 0x40, + CSU_NS_USER_RW = 0x44, + CSU_S_SUP_R = 0x02, + CSU_S_SUP_W = 0x20, + CSU_S_SUP_RW = 0x22, + CSU_S_USER_R = 0x01, + CSU_S_USER_W = 0x10, + CSU_S_USER_RW = 0x11, + CSU_ALL_RW = 0xff, +}; + +enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB3, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI2 = 40, + CSU_CSLX_DSPI1, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_2D_ACE, + CSU_CSLX_IFC, + CSU_CSLX_I2C1, + CSU_CSLX_USB2, + CSU_CSLX_I2C3, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_RESERVED0, + CSU_CSLX_ETSEC1, + CSU_CSLX_SEC5_5, + CSU_CSLX_ETSEC3, + CSU_CSLX_ETSEC2, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_ASRC, + CSU_CSLX_SPDIF, + CSU_CSLX_FLEXCAN2, + CSU_CSLX_FLEXCAN1, + CSU_CSLX_FLEXCAN4 = 80, + CSU_CSLX_FLEXCAN3, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, + CSU_CSLX_FTM2, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_COP_DCSR, + CSU_CSLX_EPU, + CSU_CSLX_GDI, + CSU_CSLX_DDI, + CSU_CSLX_RESERVED1, + CSU_CSLX_USB3_PHY = 117, + CSU_CSLX_RESERVED2, + CSU_CSLX_MAX, +}; + +struct csu_ns_dev { + unsigned long ind; + uint32_t val; +}; + +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num); + +#endif -- cgit v1.1 From 660673af4fd10c544ceeedeb524ba92c27dbc586 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:59 +0800 Subject: ARM: ls102xa: Setting device's stream id for SMMUs. LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h new file mode 100644 index 0000000..abd70fc --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -0,0 +1,17 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_STREAM_ID_H_ +#define __FSL_LS102XA_STREAM_ID_H_ + +struct smmu_stream_id { + uint16_t offset; + uint16_t stream_id; + char dev_name[32]; +}; + +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num); +#endif -- cgit v1.1 From 0de15707a71ec64dbc1ead2831457f1550179ea7 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 16:18:09 +0800 Subject: kconfig: ls102xa: Change the prompt messages As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR boards, the prompt message "Support ls1021aqds_nor" in Kconfig is not clear. This patch changes it to "Support ls1021aqds". Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 11ae5f8..c026dec 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -728,12 +728,12 @@ config TARGET_LS2085A_SIMU select ARM64 config TARGET_LS1021AQDS - bool "Support ls1021aqds_nor" + bool "Support ls1021aqds" select CPU_V7 select SUPPORT_SPL config TARGET_LS1021ATWR - bool "Support ls1021atwr_nor" + bool "Support ls1021atwr" select CPU_V7 select SUPPORT_SPL -- cgit v1.1