From 1c1b7c3739095da7d73fef3adbe9f187791ca9ff Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Fri, 11 Jan 2013 00:53:31 +0000 Subject: pcm051: Add support for Phytec phyCORE-AM335x The board is named pcm051 and has this hardware: SOC: TI AM3359 DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB ETH 1: LAN8710AI SPI-Flash: W25Q64BVSSIG RTC: RV-4162-C7 I2C-EEPROM: CAT32WC32 NAND: MT29F4G08_VFPGA63 PMIC: TPS65910A3 LCD Supported: UART 1 MMC/SD ETH 1 USB I2C SPI Not yet supported: NAND RTC LCD Signed-off-by: Lars Poeschel [trini: Add #define CONFIG_PHY_ADDR 0 to config] Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 8e69fb6..f95b332 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -65,6 +65,24 @@ #define MT41J128MJT125_PHY_FIFO_WE 0x100 #define MT41J128MJT125_IOCTRL_VALUE 0x18B +/* Micron MT41J256M8HX-15E */ +#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06 +#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B +#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA +#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F +#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 +#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B +#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 +#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1 +#define MT41J256M8HX15E_RATIO 0x40 +#define MT41J256M8HX15E_INVERT_CLKOUT 0x1 +#define MT41J256M8HX15E_RD_DQS 0x3B +#define MT41J256M8HX15E_WR_DQS 0x85 +#define MT41J256M8HX15E_PHY_WR_DATA 0xC1 +#define MT41J256M8HX15E_PHY_FIFO_WE 0x100 +#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B + + /** * Configure SDRAM */ -- cgit v1.1