From 661edaafd44c6a7001a95d3a93a7dc03acc18a39 Mon Sep 17 00:00:00 2001 From: Andreas Wass Date: Wed, 14 Aug 2013 23:45:03 +0200 Subject: ARM: mxs: Added application UART driver The driver makes it possible to use an application UART as the U-Boot output console for Freescale i.MX23/i.MX28 devices. Signed-off-by: Andreas Wass Cc: Fabio Estevam Cc: Marek Vasut Acked-by: Marek Vasut --- arch/arm/include/asm/arch-mxs/regs-uartapp.h | 220 +++++++++++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h new file mode 100644 index 0000000..7ceb810 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h @@ -0,0 +1,220 @@ +/* + * Freescale MXS UARTAPP Register Definitions + * + * Copyright (C) 2013 Andreas Wass + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ARM___MXS_UARTAPP_H +#define __ARCH_ARM___MXS_UARTAPP_H + +#include + +#ifndef __ASSEMBLY__ +struct mxs_uartapp_regs { + mxs_reg_32(hw_uartapp_ctrl0) + mxs_reg_32(hw_uartapp_ctrl1) + mxs_reg_32(hw_uartapp_ctrl2) + mxs_reg_32(hw_uartapp_linectrl) + mxs_reg_32(hw_uartapp_linectrl2) + mxs_reg_32(hw_uartapp_intr) + mxs_reg_32(hw_uartapp_data) + mxs_reg_32(hw_uartapp_stat) + mxs_reg_32(hw_uartapp_debug) + mxs_reg_32(hw_uartapp_version) + mxs_reg_32(hw_uartapp_autobaud) +}; +#endif + +#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) +#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) +#define UARTAPP_CTRL0_RUN_MASK (1 << 29) +#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) +#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) +#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 +#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) +#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF + +#define UARTAPP_CTRL1_RUN_MASK (1 << 28) + +#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF + +#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) +#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) +#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) +#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) +#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) +#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) +#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) +#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) +#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 +#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) + +#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) +#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 +#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) +#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) +#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) +#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) +#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) +#define UARTAPP_CTRL2_RTS_MASK (1 << 11) +#define UARTAPP_CTRL2_DTR_MASK (1 << 10) +#define UARTAPP_CTRL2_RXE_MASK (1 << 9) +#define UARTAPP_CTRL2_TXE_MASK (1 << 8) +#define UARTAPP_CTRL2_LBE_MASK (1 << 7) +#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) + +#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) +#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) +#define UARTAPP_CTRL2_UARTEN_MASK 0x01 + +#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F + +#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) +#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) + +#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) +#define UARTAPP_LINECTRL_BRK_MASK 1 + +#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F + +#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) +#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) + +#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) + +#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) +#define UARTAPP_INTR_OEIEN_MASK (1 << 26) +#define UARTAPP_INTR_BEIEN_MASK (1 << 25) +#define UARTAPP_INTR_PEIEN_MASK (1 << 24) +#define UARTAPP_INTR_FEIEN_MASK (1 << 23) +#define UARTAPP_INTR_RTIEN_MASK (1 << 22) +#define UARTAPP_INTR_TXIEN_MASK (1 << 21) +#define UARTAPP_INTR_RXIEN_MASK (1 << 20) +#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) +#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) +#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) +#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) + +#define UARTAPP_INTR_ABDIS_MASK (1 << 11) +#define UARTAPP_INTR_OEIS_MASK (1 << 10) +#define UARTAPP_INTR_BEIS_MASK (1 << 9) +#define UARTAPP_INTR_PEIS_MASK (1 << 8) +#define UARTAPP_INTR_FEIS_MASK (1 << 7) +#define UARTAPP_INTR_RTIS_MASK (1 << 6) +#define UARTAPP_INTR_TXIS_MASK (1 << 5) +#define UARTAPP_INTR_RXIS_MASK (1 << 4) +#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) +#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) +#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) +#define UARTAPP_INTR_RIMIS_MASK 0x1 + +#define UARTAPP_DATA_DATA_OFFSET 0 +#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF +#define UARTAPP_STAT_PRESENT_MASK (1 << 31) +#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) +#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) + +#define UARTAPP_STAT_HISPEED_MASK (1 << 30) +#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) +#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) + +#define UARTAPP_STAT_BUSY_MASK (1 << 29) +#define UARTAPP_STAT_CTS_MASK (1 << 28) +#define UARTAPP_STAT_TXFE_MASK (1 << 27) +#define UARTAPP_STAT_RXFF_MASK (1 << 26) +#define UARTAPP_STAT_TXFF_MASK (1 << 25) +#define UARTAPP_STAT_RXFE_MASK (1 << 24) +#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 +#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) + +#define UARTAPP_STAT_OERR_MASK (1 << 19) +#define UARTAPP_STAT_BERR_MASK (1 << 18) +#define UARTAPP_STAT_PERR_MASK (1 << 17) +#define UARTAPP_STAT_FERR_MASK (1 << 16) +#define UARTAPP_STAT_RXCOUNT_OFFSET 0 +#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF + +#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 +#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) + +#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 +#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) + +#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) +#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) +#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) +#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) +#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) +#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 + +#define UARTAPP_VERSION_MAJOR_OFFSET 24 +#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) + +#define UARTAPP_VERSION_MINOR_OFFSET 16 +#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) + +#define UARTAPP_VERSION_STEP_OFFSET 0 +#define UARTAPP_VERSION_STEP_MASK 0xFFFF + +#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 +#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) + +#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 +#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) + +#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) +#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) +#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) +#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) +#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 +#endif /* __ARCH_ARM___UARTAPP_H */ -- cgit v1.1 From b83c709e8d3f29721f32d66f19f953a2f818afbc Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 28 Jun 2013 00:20:21 +0200 Subject: imx: add status reporting for HAB status Add functions to report the HAB (High Assurance Boot) status of e.g. i.MX6 CPUs. This is taken from git://git.freescale.com/imx/uboot-imx.git branch imx_v2009.08_3.0.35_4.0.0 cpu/arm_cortexa8/mx6/generic.c include/asm-arm/arch-mx6/mx6_secure.h Signed-off-by: Stefano Babic --- arch/arm/cpu/armv7/mx6/Makefile | 7 ++- arch/arm/cpu/armv7/mx6/hab.c | 104 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/hab.h | 67 ++++++++++++++++++++ arch/arm/include/asm/arch-mx6/imx-regs.h | 8 ++- 4 files changed, 182 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/hab.c create mode 100644 arch/arm/include/asm/arch-mx6/hab.h (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index c5e9858..6d73617 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -11,10 +11,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = soc.o clock.o +COBJS-y = soc.o clock.o +COBJS-$(CONFIG_SECURE_BOOT) += hab.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) all: $(obj).depend $(LIB) diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c new file mode 100644 index 0000000..5187775 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/hab.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* -------- start of HAB API updates ------------*/ +#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) +#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) +#define hab_rvt_authenticate_image \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) +#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY) +#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT) +#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT + +bool is_hab_enabled(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + uint32_t reg = readl(&fuse->cfg5); + + return (reg & 0x2) == 0x2; +} + +void display_event(uint8_t *event_data, size_t bytes) +{ + uint32_t i; + + if (!(event_data && bytes > 0)) + return; + + for (i = 0; i < bytes; i++) { + if (i == 0) + printf("\t0x%02x", event_data[i]); + else if ((i % 8) == 0) + printf("\n\t0x%02x", event_data[i]); + else + printf(" 0x%02x", event_data[i]); + } +} + +int get_hab_status(void) +{ + uint32_t index = 0; /* Loop index */ + uint8_t event_data[128]; /* Event data buffer */ + size_t bytes = sizeof(event_data); /* Event size in bytes */ + enum hab_config config = 0; + enum hab_state state = 0; + + if (is_hab_enabled()) + puts("\nSecure boot enabled\n"); + else + puts("\nSecure boot disabled\n"); + + /* Check HAB status */ + if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) { + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + + /* Display HAB Error events */ + while (hab_rvt_report_event(HAB_FAILURE, index, event_data, + &bytes) == HAB_SUCCESS) { + puts("\n"); + printf("--------- HAB Event %d -----------------\n", + index + 1); + puts("event data:\n"); + display_event(event_data, bytes); + puts("\n"); + bytes = sizeof(event_data); + index++; + } + } + /* Display message if no HAB events are found */ + else { + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + puts("No HAB Events Found!\n\n"); + } + return 0; +} + +int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if ((argc != 1)) { + cmd_usage(cmdtp); + return 1; + } + + get_hab_status(); + + return 0; +} + +U_BOOT_CMD( + hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, + "display HAB status", + "" + ); diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h new file mode 100644 index 0000000..d724f20 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/hab.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + * +*/ + +#ifndef __SECURE_MX6Q_H__ +#define __SECURE_MX6Q_H__ + +#include + +/* -------- start of HAB API updates ------------*/ +/* The following are taken from HAB4 SIS */ + +/* Status definitions */ +enum hab_status { + HAB_STS_ANY = 0x00, + HAB_FAILURE = 0x33, + HAB_WARNING = 0x69, + HAB_SUCCESS = 0xf0 +}; + +/* Security Configuration definitions */ +enum hab_config { + HAB_CFG_RETURN = 0x33, /**< Field Return IC */ + HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */ + HAB_CFG_CLOSED = 0xcc /**< Secure IC */ +}; + +/* State definitions */ +enum hab_state { + HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */ + HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */ + HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */ + HAB_STATE_TRUSTED = 0x99, /**< Trusted state */ + HAB_STATE_SECURE = 0xaa, /**< Secure state */ + HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */ + HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */ + HAB_STATE_NONE = 0xf0, /**< No security state machine */ + HAB_STATE_MAX +}; + +/*Function prototype description*/ +typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t, + uint8_t* , size_t*); +typedef enum hab_status hab_rvt_report_status_t(enum hab_config *, + enum hab_state *); +typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*); +typedef enum hab_status hab_rvt_entry_t(void); +typedef enum hab_status hab_rvt_exit_t(void); +typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, + void **, size_t *, hab_loader_callback_f_t); +typedef void hapi_clock_init_t(void); + +#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4) +#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4) +#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098) +#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C) +#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D) + +#define HAB_CID_ROM 0 /**< ROM Caller ID */ +#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ +/* ----------- end of HAB API updates ------------*/ + +#endif diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d6bccb..621919f 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -456,7 +456,13 @@ struct fuse_bank0_regs { u32 uid_low; u32 rsvd1[3]; u32 uid_high; - u32 rsvd2[0x17]; + u32 rsvd2[3]; + u32 rsvd3[4]; + u32 rsvd4[4]; + u32 rsvd5[4]; + u32 cfg5; + u32 rsvd6[3]; + u32 rsvd7[4]; }; struct fuse_bank4_regs { -- cgit v1.1 From bce8837071617a13f8e28f60400ee826b3f8a308 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Aug 2013 20:43:33 +0200 Subject: ARM: mxs: tools: Add mkimage support for MXS bootstream Add mkimage support for generating and verifying MXS bootstream. The implementation here is mostly a glue code between MXSSB v0.4 and mkimage, but the long-term goal is to rectify this and merge MXSSB with mkimage more tightly. Once this code is properly in U-Boot, MXSSB shall be deprecated in favor of mkimage-mxsimage support. Note that the mxsimage generator needs libcrypto from OpenSSL, I therefore enabled the libcrypto/libssl unconditionally. MXSSB: http://git.denx.de/?p=mxssb.git;a=summary The code is based on research presented at: http://www.rockbox.org/wiki/SbFileFormat Signed-off-by: Marek Vasut Cc: Tom Rini Cc: Fabio Estevam Cc: Stefano Babic Cc: Otavio Salvador --- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 6 ++++++ arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg | 8 ++++++++ 2 files changed, 14 insertions(+) create mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg create mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg new file mode 100644 index 0000000..8118767 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -0,0 +1,6 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x0 spl/u-boot-spl.bin + CALL 0x14 0x0 + LOAD 0x40000100 u-boot.bin + CALL 0x40000100 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg new file mode 100644 index 0000000..ea772f0 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -0,0 +1,8 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x0 spl/u-boot-spl.bin + LOAD IVT 0x8000 0x14 + CALL HAB 0x8000 0x0 + LOAD 0x40000100 u-boot.bin + LOAD IVT 0x8000 0x40000100 + CALL HAB 0x8000 0x0 -- cgit v1.1 From 6f6059e0f102809bcba1ea3b7d500c3e4f5f9581 Mon Sep 17 00:00:00 2001 From: Hector Palacios Date: Wed, 24 Jul 2013 16:01:39 +0200 Subject: ARM: mxs: rename function that sets AUTO_RESTART flag The AUTO_RESTART flag of HW_RTC_PERSISTENT0 register will power up the chip automatically 180ms after power down. This bit must be enabled by the boot loader to ensure the target can start upon hardware reset or watchdog reset even when powered from a battery. Currently the function named 'mxs_power_clear_auto_restart()' is setting this flag although the 'clear' in its name suggest the opposite. This patch renames the function to 'mxs_power_set_auto_restart()' and removes the comment about EVK revision A which was confusing because the function indeed was setting the flag. Signed-off-by: Hector Palacios --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index e3b6cd9..f357959 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -36,7 +36,7 @@ static void mxs_power_clock2pll(void) CLKCTRL_CLKSEQ_BYPASS_CPU); } -static void mxs_power_clear_auto_restart(void) +static void mxs_power_set_auto_restart(void) { struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE; @@ -49,10 +49,7 @@ static void mxs_power_clear_auto_restart(void) while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) ; - /* - * Due to the hardware design bug of mx28 EVK-A - * we need to set the AUTO_RESTART bit. - */ + /* Do nothing if flag already set */ if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) return; @@ -911,7 +908,7 @@ void mxs_power_init(void) mxs_ungate_power(); mxs_power_clock2xtal(); - mxs_power_clear_auto_restart(); + mxs_power_set_auto_restart(); mxs_power_set_linreg(); mxs_power_setup_5v_detect(); -- cgit v1.1 From 1ca244ded50de4b5f39ded2793a02fe5f17f9ba6 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 29 Aug 2013 10:57:10 -0700 Subject: i.MX6: Add convenience macros cpu_type(rev) and is_cpu_type(cpu) Signed-off-by: Eric Nelson Acked-by: Stefano Babic --- arch/arm/include/asm/arch-mx6/sys_proto.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index bfdfd29..8c21364 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -19,6 +19,13 @@ #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); + +/* returns MXC_CPU_ value */ +#define cpu_type(rev) (((rev) >> 12)&0xff) + +/* use with MXC_CPU_ constants */ +#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu) + const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); -- cgit v1.1 From 3fc4176dc4b61bc50b0d90f10eef48f7b2e28203 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 29 Aug 2013 12:37:35 -0700 Subject: i.MX6: Correct ANATOP_PFD (Phase Fractional Divider) register declarations Some _CLKGATE_MASK and _FRAC_MASK macros were wrong for PFD_480 and the PFD_528 macros were missing. Fortunately, the incorrect macros weren't being used. Since both the PFD_480 and PFD_528 registers have the same structure, and the fields are identical for [0..3] in bytes [0..3], so a single set of macros will suffice. Signed-off-by: Eric Nelson --- arch/arm/include/asm/arch-mx6/imx-regs.h | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 621919f..7ef7152 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -635,29 +635,12 @@ struct anatop_regs { u32 digprog_sololite; /* 0x280 */ }; -#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 -#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f< Date: Thu, 29 Aug 2013 12:41:46 -0700 Subject: i.MX6: Set and clear the gating bits for Phase Fractional Dividers This addresses silicon errata ERR006282 as described in this document: https://community.freescale.com/docs/DOC-94581 Also implemented in Freescale's 2009.08-based release: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/ Commit id: b7c5badf94ffbe6cd0845efbb75e16e05e3af404 Signed-off-by: Eric Nelson Acked-by: Stefano Babic --- arch/arm/cpu/armv7/mx6/soc.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 8150bff..a390296 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -213,6 +213,34 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int is_6q = is_cpu_type(MXC_CPU_MX6Q); + u32 mask480; + u32 mask528; + + /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs + * to make sure PFD is working right, otherwise, PFDs may + * not output clock after reset, MX6DL and MX6SL have added 396M pfd + * workaround in ROM code, as bus clock need it + */ + + mask480 = ANATOP_PFD_CLKGATE_MASK(0) | + ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(2) | + ANATOP_PFD_CLKGATE_MASK(3); + mask528 = ANATOP_PFD_CLKGATE_MASK(0) | + ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(3); + + /* + * Don't reset PFD2 on DL/S + */ + if (is_6q) + mask528 |= ANATOP_PFD_CLKGATE_MASK(2); + writel(mask480, &anatop->pfd_480_set); + writel(mask528, &anatop->pfd_528_set); + writel(mask480, &anatop->pfd_480_clr); + writel(mask528, &anatop->pfd_528_clr); } #ifdef CONFIG_IMX_HDMI -- cgit v1.1