From 17de114f9f925eb740d813476fe486154fa8df91 Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <reinauer@chromium.org>
Date: Sun, 2 Dec 2012 04:49:53 +0000
Subject: x86: Clean up MTRR 7 right before jumping to the kernel

This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/x86/cpu/coreboot/coreboot.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'arch')

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index b942a3e..f262800 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -26,6 +26,8 @@
 #include <asm/u-boot-x86.h>
 #include <flash.h>
 #include <netdev.h>
+#include <asm/msr.h>
+#include <asm/cache.h>
 #include <asm/arch-coreboot/tables.h>
 #include <asm/arch-coreboot/sysinfo.h>
 #include <asm/arch/timestamp.h>
@@ -89,3 +91,19 @@ int board_eth_init(bd_t *bis)
 void setup_pcat_compatibility()
 {
 }
+
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+int board_final_cleanup(void)
+{
+	/* Un-cache the ROM so the kernel has one
+	 * more MTRR available.
+	 */
+	disable_caches();
+	wrmsrl(MTRRphysBase_MSR(7), 0);
+	wrmsrl(MTRRphysMask_MSR(7), 0);
+	enable_caches();
+
+	return 0;
+}
-- 
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