From 86fdb1619a1ad495dcabc9f356e1bbd268e3565e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 12 Apr 2013 12:38:16 -0400 Subject: am335x: Really correct DDR timings on new BeagleBone part The previous timings were done on the internal-only A1 board which has different DDR part than all later revs. The timings need a slight adjustment to be correct in all cases with later revs. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 914df01..fb4e78e 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -86,18 +86,18 @@ /* Micron MT41K256M16HA-125E */ #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB -#define MT41K256M16HA125E_EMIF_TIM2 0x26437FDA -#define MT41K256M16HA125E_EMIF_TIM3 0x501F83FF -#define MT41K256M16HA125E_EMIF_SDCFG 0x61C052B2 +#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA +#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F +#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 #define MT41K256M16HA125E_EMIF_SDREF 0xC30 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 #define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1 #define MT41K256M16HA125E_RATIO 0x80 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0 -#define MT41K256M16HA125E_RD_DQS 0x3A -#define MT41K256M16HA125E_WR_DQS 0x42 -#define MT41K256M16HA125E_PHY_WR_DATA 0x7E -#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B +#define MT41K256M16HA125E_RD_DQS 0x38 +#define MT41K256M16HA125E_WR_DQS 0x44 +#define MT41K256M16HA125E_PHY_WR_DATA 0x7D +#define MT41K256M16HA125E_PHY_FIFO_WE 0x94 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B /* Micron MT41J512M8RH-125 on EVM v1.5 */ -- cgit v1.1 From 9d0fd10ca1931e5a32c7bfb500a471599a60ddbe Mon Sep 17 00:00:00 2001 From: "man.huber@arcor.de" Date: Wed, 10 Apr 2013 12:12:17 +0000 Subject: omap3: Display MHz instead of mHz on the console The processor is hopefully running with M(ega)Hz and not with m(illi)Hz. Signed-off-by: Manfred Huber --- arch/arm/cpu/armv7/omap3/sys_info.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 3c80113..08a63d2 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -299,9 +299,9 @@ int print_cpuinfo (void) } if ((get_cpu_rev() >= CPU_3XX_ES31) && (get_sku_id() == SKUID_CLK_720MHZ)) - max_clk = "720 mHz"; + max_clk = "720 MHz"; else - max_clk = "600 mHz"; + max_clk = "600 MHz"; break; case CPU_AM35XX: -- cgit v1.1