From c978b52410016b0ab5a213f235596340af8d45f7 Mon Sep 17 00:00:00 2001 From: Chris Zankel Date: Wed, 10 Aug 2016 18:36:44 +0300 Subject: xtensa: add support for the xtensa processor architecture [2/2] The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel Signed-off-by: Max Filippov Reviewed-by: Simon Glass Reviewed-by: Tom Rini --- arch/xtensa/lib/cache.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 arch/xtensa/lib/cache.c (limited to 'arch/xtensa/lib/cache.c') diff --git a/arch/xtensa/lib/cache.c b/arch/xtensa/lib/cache.c new file mode 100644 index 0000000..2680839 --- /dev/null +++ b/arch/xtensa/lib/cache.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2008 - 2013 Tensilica Inc. + * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +/* + * We currently run always with caches enabled when running from memory. + * Xtensa version D or later will support changing cache behavior, so + * we could implement it if necessary. + */ + +int dcache_status(void) +{ + return 1; +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +void flush_cache(ulong start_addr, ulong size) +{ + __flush_invalidate_dcache_range(start_addr, size); + __invalidate_icache_range(start_addr, size); +} + +void flush_dcache_all(void) +{ + __flush_dcache_all(); + __invalidate_icache_all(); +} + +void flush_dcache_range(ulong start_addr, ulong end_addr) +{ + __flush_invalidate_dcache_range(start_addr, end_addr - start_addr); +} + +void invalidate_dcache_range(ulong start, ulong stop) +{ + __invalidate_dcache_range(start, stop - start); +} + +void invalidate_dcache_all(void) +{ + __invalidate_dcache_all(); +} + +void invalidate_icache_all(void) +{ + __invalidate_icache_all(); +} -- cgit v1.1