From c978b52410016b0ab5a213f235596340af8d45f7 Mon Sep 17 00:00:00 2001 From: Chris Zankel Date: Wed, 10 Aug 2016 18:36:44 +0300 Subject: xtensa: add support for the xtensa processor architecture [2/2] The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel Signed-off-by: Max Filippov Reviewed-by: Simon Glass Reviewed-by: Tom Rini --- arch/xtensa/dts/Makefile | 13 +++++++++++++ arch/xtensa/dts/include/dt-bindings | 1 + 2 files changed, 14 insertions(+) create mode 100644 arch/xtensa/dts/Makefile create mode 120000 arch/xtensa/dts/include/dt-bindings (limited to 'arch/xtensa/dts') diff --git a/arch/xtensa/dts/Makefile b/arch/xtensa/dts/Makefile new file mode 100644 index 0000000..eacf6f3 --- /dev/null +++ b/arch/xtensa/dts/Makefile @@ -0,0 +1,13 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +targets += $(dtb-y) + +DTC_FLAGS += + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/xtensa/dts/include/dt-bindings b/arch/xtensa/dts/include/dt-bindings new file mode 120000 index 0000000..0cecb3d --- /dev/null +++ b/arch/xtensa/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings \ No newline at end of file -- cgit v1.1