From adfe3b247a7a281931f0fd865e9d00600e9dd384 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 17 Dec 2014 15:50:44 +0800
Subject: x86: crownbay: Add SPI flash support

The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
 arch/x86/cpu/queensbay/tnc.c              | 26 +++++++++++++++++++++++++-
 arch/x86/include/asm/arch-queensbay/tnc.h | 15 +++++++++++++++
 2 files changed, 40 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/include/asm/arch-queensbay/tnc.h

(limited to 'arch/x86')

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 8b9815f..8637cdc 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -6,18 +6,42 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/pci.h>
 #include <asm/post.h>
+#include <asm/arch/tnc.h>
 #include <asm/arch/fsp/fsp_support.h>
 #include <asm/processor.h>
 
+static void unprotect_spi_flash(void)
+{
+	u32 bc;
+
+	bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
+	bc |= 0x1;	/* unprotect the flash */
+	pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
+}
+
 int arch_cpu_init(void)
 {
+	struct pci_controller *hose;
+	int ret;
+
 	post_code(POST_CPU_INIT);
 #ifdef CONFIG_SYS_X86_TSC_TIMER
 	timer_set_base(rdtsc());
 #endif
 
-	return x86_cpu_init_f();
+	ret = x86_cpu_init_f();
+	if (ret)
+		return ret;
+
+	ret = pci_early_init_hose(&hose);
+	if (ret)
+		return ret;
+
+	unprotect_spi_flash();
+
+	return 0;
 }
 
 int print_cpuinfo(void)
diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h
new file mode 100644
index 0000000..67c5e05
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/tnc.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_TNC_H_
+#define _X86_ARCH_TNC_H_
+
+#include <pci.h>
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV	PCI_BDF(0, 0x1f, 0)
+
+#endif /* _X86_ARCH_TNC_H_ */
-- 
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