From 1f124eba11cb1619e6d575770756230484e47bf7 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 1 Oct 2015 00:36:04 -0700 Subject: x86: Allow disabling IGD on Intel Queensbay Add a Kconfig option to disable the Integrated Graphics Device (IGD) so that it does not show in the PCI configuration space as a VGA disaplay controller. This gives a chance for U-Boot to run PCI/PCIe based graphics card's VGA BIOS and use that for the graphics console. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/arch-queensbay/tnc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/x86/include') diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h index ad9a6c4..2365394 100644 --- a/arch/x86/include/asm/arch-queensbay/tnc.h +++ b/arch/x86/include/asm/arch-queensbay/tnc.h @@ -7,6 +7,11 @@ #ifndef _X86_ARCH_TNC_H_ #define _X86_ARCH_TNC_H_ +/* IGD Control Register */ +#define IGD_GC 0x50 +#define VGA_DISABLE 0x00020000 +#define GMS_MASK 0x00700000 + /* Memory BAR Enable */ #define MEM_BAR_EN 0x00000001 -- cgit v1.1 From 59ec719df62bcb397066aeee66fdbd8f042ca3c7 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 7 Oct 2015 20:19:10 -0700 Subject: x86: Move install_e820_map() out of zimage.c install_e820_map() has nothing to do with zimage related codes. Move it to a dedicated place. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/e820.h | 3 +++ arch/x86/include/asm/zimage.h | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/x86/include') diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index 21bc633..351f021 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -23,4 +23,7 @@ struct e820entry { #endif /* __ASSEMBLY__ */ +/* Implementation defined function to install an e820 map */ +unsigned install_e820_map(unsigned max_entries, struct e820entry *); + #endif /* _ASM_X86_E820_H */ diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index bf351ed..94fa2a7 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -31,9 +31,6 @@ #define BZIMAGE_LOAD_ADDR 0x100000 #define ZIMAGE_LOAD_ADDR 0x10000 -/* Implementation defined function to install an e820 map. */ -unsigned install_e820_map(unsigned max_entries, struct e820entry *); - struct boot_params *load_zimage(char *image, unsigned long kernel_size, ulong *load_addressp); int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, -- cgit v1.1 From 721e992a8af5e80b2a95a0bc92c9880f2056190b Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 12 Oct 2015 05:23:41 -0700 Subject: x86: Add SMBIOS table support System Management BIOS (SMBIOS) is a specification for how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. As of today the latest spec is 3.0 and can be downloaded from DMTF website. This commit adds a simple and minimum required implementation. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/smbios.h | 236 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 236 insertions(+) create mode 100644 arch/x86/include/asm/smbios.h (limited to 'arch/x86/include') diff --git a/arch/x86/include/asm/smbios.h b/arch/x86/include/asm/smbios.h new file mode 100644 index 0000000..623a703 --- /dev/null +++ b/arch/x86/include/asm/smbios.h @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * Adapted from coreboot src/include/smbios.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SMBIOS_H_ +#define _SMBIOS_H_ + +/* SMBIOS spec version implemented */ +#define SMBIOS_MAJOR_VER 3 +#define SMBIOS_MINOR_VER 0 + +/* SMBIOS structure types */ +enum { + SMBIOS_BIOS_INFORMATION = 0, + SMBIOS_SYSTEM_INFORMATION = 1, + SMBIOS_BOARD_INFORMATION = 2, + SMBIOS_SYSTEM_ENCLOSURE = 3, + SMBIOS_PROCESSOR_INFORMATION = 4, + SMBIOS_CACHE_INFORMATION = 7, + SMBIOS_SYSTEM_SLOTS = 9, + SMBIOS_PHYS_MEMORY_ARRAY = 16, + SMBIOS_MEMORY_DEVICE = 17, + SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19, + SMBIOS_SYSTEM_BOOT_INFORMATION = 32, + SMBIOS_END_OF_TABLE = 127 +}; + +#define SMBIOS_INTERMEDIATE_OFFSET 16 +#define SMBIOS_STRUCT_EOS_BYTES 2 + +struct __packed smbios_entry { + u8 anchor[4]; + u8 checksum; + u8 length; + u8 major_ver; + u8 minor_ver; + u16 max_struct_size; + u8 entry_point_rev; + u8 formatted_area[5]; + u8 intermediate_anchor[5]; + u8 intermediate_checksum; + u16 struct_table_length; + u32 struct_table_address; + u16 struct_count; + u8 bcd_rev; +}; + +/* BIOS characteristics */ +#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) +#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) +#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) + +#define BIOS_CHARACTERISTICS_EXT1_ACPI (1 << 0) +#define BIOS_CHARACTERISTICS_EXT2_TARGET (1 << 2) + +struct __packed smbios_type0 { + u8 type; + u8 length; + u16 handle; + u8 vendor; + u8 bios_ver; + u16 bios_start_segment; + u8 bios_release_date; + u8 bios_rom_size; + u64 bios_characteristics; + u8 bios_characteristics_ext1; + u8 bios_characteristics_ext2; + u8 bios_major_release; + u8 bios_minor_release; + u8 ec_major_release; + u8 ec_minor_release; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type1 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 uuid[16]; + u8 wakeup_type; + u8 sku_number; + u8 family; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +#define SMBIOS_BOARD_FEATURE_HOSTING (1 << 0) +#define SMBIOS_BOARD_MOTHERBOARD 10 + +struct __packed smbios_type2 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 asset_tag_number; + u8 feature_flags; + u8 chassis_location; + u16 chassis_handle; + u8 board_type; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +#define SMBIOS_ENCLOSURE_DESKTOP 3 +#define SMBIOS_STATE_SAFE 3 +#define SMBIOS_SECURITY_NONE 3 + +struct __packed smbios_type3 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 chassis_type; + u8 version; + u8 serial_number; + u8 asset_tag_number; + u8 bootup_state; + u8 power_supply_state; + u8 thermal_state; + u8 security_status; + u32 oem_defined; + u8 height; + u8 number_of_power_cords; + u8 element_count; + u8 element_record_length; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +#define SMBIOS_PROCESSOR_TYPE_CENTRAL 3 +#define SMBIOS_PROCESSOR_STATUS_ENABLED 1 +#define SMBIOS_PROCESSOR_UPGRADE_NONE 6 + +struct __packed smbios_type4 { + u8 type; + u8 length; + u16 handle; + u8 socket_designation; + u8 processor_type; + u8 processor_family; + u8 processor_manufacturer; + u32 processor_id[2]; + u8 processor_version; + u8 voltage; + u16 external_clock; + u16 max_speed; + u16 current_speed; + u8 status; + u8 processor_upgrade; + u16 l1_cache_handle; + u16 l2_cache_handle; + u16 l3_cache_handle; + u8 serial_number; + u8 asset_tag; + u8 part_number; + u8 core_count; + u8 core_enabled; + u8 thread_count; + u16 processor_characteristics; + u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type32 { + u8 type; + u8 length; + u16 handle; + u8 reserved[6]; + u8 boot_status; + u8 eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type127 { + u8 type; + u8 length; + u16 handle; + u8 eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_header { + u8 type; + u8 length; + u16 handle; +}; + +/** + * fill_smbios_header() - Fill the header of an SMBIOS table + * + * This fills the header of an SMBIOS table structure. + * + * @table: start address of the structure + * @type: the type of structure + * @length: the length of the formatted area of the structure + * @handle: the structure's handle, a unique 16-bit number + */ +static inline void fill_smbios_header(void *table, int type, + int length, int handle) +{ + struct smbios_header *header = table; + + header->type = type; + header->length = length - SMBIOS_STRUCT_EOS_BYTES; + header->handle = handle; +} + +/** + * Function prototype to write a specific type of SMBIOS structure + * + * @addr: start address to write the structure + * @handle: the structure's handle, a unique 16-bit number + * @return: size of the structure + */ +typedef int (*smbios_write_type)(u32 *addr, int handle); + +/** + * write_smbios_table() - Write SMBIOS table + * + * This writes SMBIOS table at a given address. + * + * @addr: start address to write SMBIOS table + * @return: end address of SMBIOS table + */ +u32 write_smbios_table(u32 addr); + +#endif /* _SMBIOS_H_ */ -- cgit v1.1 From f6220f1a86109f88950fd42e3af54314de24365a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 11 Oct 2015 21:37:36 -0700 Subject: x86: Move mrccache.[c|h] to a common place mrccache implementation can be common for all boards. Move it from ivybridge cpu directory to the common lib directory. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/arch-ivybridge/mrccache.h | 51 -------------------------- arch/x86/include/asm/mrccache.h | 51 ++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 51 deletions(-) delete mode 100644 arch/x86/include/asm/arch-ivybridge/mrccache.h create mode 100644 arch/x86/include/asm/mrccache.h (limited to 'arch/x86/include') diff --git a/arch/x86/include/asm/arch-ivybridge/mrccache.h b/arch/x86/include/asm/arch-ivybridge/mrccache.h deleted file mode 100644 index 1d50ebb..0000000 --- a/arch/x86/include/asm/arch-ivybridge/mrccache.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_MRCCACHE_H -#define _ASM_ARCH_MRCCACHE_H - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | ('C' << 16) | \ - ('D'<<24)) - -__packed struct mrc_data_container { - u32 signature; /* "MRCD" */ - u32 data_size; /* Size of the 'data' field */ - u32 checksum; /* IP style checksum */ - u32 reserved; /* For header alignment */ - u8 data[0]; /* Variable size, platform/run time dependent */ -}; - -struct fmap_entry; -struct udevice; - -/** - * mrccache_find_current() - find the latest MRC cache record - * - * This searches the MRC cache region looking for the latest record to use - * for setting up SDRAM - * - * @entry: Information about the position and size of the MRC cache - * @return pointer to latest record, or NULL if none - */ -struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); - -/** - * mrccache_update() - update the MRC cache with a new record - * - * This writes a new record to the end of the MRC cache. If the new record is - * the same as the latest record then the write is skipped - * - * @sf: SPI flash to write to - * @entry: Position and size of MRC cache in SPI flash - * @cur: Record to write - * @return 0 if updated, -EEXIST if the record is the same as the latest - * record, other error if SPI write failed - */ -int mrccache_update(struct udevice *sf, struct fmap_entry *entry, - struct mrc_data_container *cur); - -#endif diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h new file mode 100644 index 0000000..1d50ebb --- /dev/null +++ b/arch/x86/include/asm/mrccache.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_MRCCACHE_H +#define _ASM_ARCH_MRCCACHE_H + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | ('C' << 16) | \ + ('D'<<24)) + +__packed struct mrc_data_container { + u32 signature; /* "MRCD" */ + u32 data_size; /* Size of the 'data' field */ + u32 checksum; /* IP style checksum */ + u32 reserved; /* For header alignment */ + u8 data[0]; /* Variable size, platform/run time dependent */ +}; + +struct fmap_entry; +struct udevice; + +/** + * mrccache_find_current() - find the latest MRC cache record + * + * This searches the MRC cache region looking for the latest record to use + * for setting up SDRAM + * + * @entry: Information about the position and size of the MRC cache + * @return pointer to latest record, or NULL if none + */ +struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); + +/** + * mrccache_update() - update the MRC cache with a new record + * + * This writes a new record to the end of the MRC cache. If the new record is + * the same as the latest record then the write is skipped + * + * @sf: SPI flash to write to + * @entry: Position and size of MRC cache in SPI flash + * @cur: Record to write + * @return 0 if updated, -EEXIST if the record is the same as the latest + * record, other error if SPI write failed + */ +int mrccache_update(struct udevice *sf, struct fmap_entry *entry, + struct mrc_data_container *cur); + +#endif -- cgit v1.1 From 2fe66dbcbc1793dc199d90c4d66acaad981f9820 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 11 Oct 2015 21:37:37 -0700 Subject: x86: Do sanity test on the cache record in mrccache_update() For the cache record to write in mrccache_update(), we should perform a sanity test to see if it is a valid one. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/mrccache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/x86/include') diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index 1d50ebb..ff41b8a 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -43,7 +43,7 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); * @entry: Position and size of MRC cache in SPI flash * @cur: Record to write * @return 0 if updated, -EEXIST if the record is the same as the latest - * record, other error if SPI write failed + * record, -EINVAL if the record is not valid, other error if SPI write failed */ int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur); -- cgit v1.1 From bfa95c538b8b7d9384141f3c88021aa9d941ba54 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 11 Oct 2015 21:37:38 -0700 Subject: x86: Add various minor tidy-ups in mrccache codes Fix some nits, improve some comments and reorder some codes a little bit. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/mrccache.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/x86/include') diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index ff41b8a..2fd9082 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -1,17 +1,17 @@ /* - * Copyright (c) 2014 Google, Inc + * Copyright (C) 2014 Google, Inc * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _ASM_ARCH_MRCCACHE_H -#define _ASM_ARCH_MRCCACHE_H +#ifndef _ASM_MRCCACHE_H +#define _ASM_MRCCACHE_H #define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | ('C' << 16) | \ - ('D'<<24)) +#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \ + ('C' << 16) | ('D'<<24)) -__packed struct mrc_data_container { +struct __packed mrc_data_container { u32 signature; /* "MRCD" */ u32 data_size; /* Size of the 'data' field */ u32 checksum; /* IP style checksum */ @@ -28,7 +28,7 @@ struct udevice; * This searches the MRC cache region looking for the latest record to use * for setting up SDRAM * - * @entry: Information about the position and size of the MRC cache + * @entry: Position and size of MRC cache in SPI flash * @return pointer to latest record, or NULL if none */ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); @@ -36,8 +36,8 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); /** * mrccache_update() - update the MRC cache with a new record * - * This writes a new record to the end of the MRC cache. If the new record is - * the same as the latest record then the write is skipped + * This writes a new record to the end of the MRC cache region. If the new + * record is the same as the latest record then the write is skipped * * @sf: SPI flash to write to * @entry: Position and size of MRC cache in SPI flash @@ -48,4 +48,4 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur); -#endif +#endif /* _ASM_MRCCACHE_H */ -- cgit v1.1 From ed800961a019240208de4ee5662d6f02381a18aa Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 11 Oct 2015 21:37:39 -0700 Subject: x86: Add more common routines to manipulate mrc cache This adds mrccache_reserve(), mrccache_get_region() and mrccache_save() APIs to the mrccache codes. They are ported from the ivybridge implementation, but with some changes. For example, in the mrccache_reserve(), ivybridge version only reserves the pure MRC data, which causes additional malloc() when saving the cache as the save API needs some meta data. Now we change it to save the whole MRC date plus the meta data to elinimate the need for the malloc() later. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/mrccache.h | 51 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'arch/x86/include') diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index 2fd9082..bcf7117 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2014 Google, Inc + * Copyright (C) 2015 Bin Meng * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,6 +12,8 @@ #define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \ ('C' << 16) | ('D'<<24)) +#define MRC_DATA_HEADER_SIZE 32 + struct __packed mrc_data_container { u32 signature; /* "MRCD" */ u32 data_size; /* Size of the 'data' field */ @@ -48,4 +51,52 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur); +/** + * mrccache_reserve() - reserve MRC data on the stack + * + * This copies MRC data pointed by gd->arch.mrc_output to a new place on the + * stack with length gd->arch.mrc_output_len, and updates gd->arch.mrc_output + * to point to the new place once the migration is done. + * + * This routine should be called by reserve_arch() before U-Boot is relocated + * when MRC cache is enabled. + * + * @return 0 always + */ +int mrccache_reserve(void); + +/** + * mrccache_get_region() - get MRC region on the SPI flash + * + * This gets MRC region whose offset and size are described in the device tree + * as a subnode to the SPI flash. If a non-NULL device pointer is supplied, + * this also probes the SPI flash device and returns its device pointer for + * the caller to use later. + * + * Be careful when calling this routine with a non-NULL device pointer: + * - driver model initialization must be complete + * - calling in the pre-relocation phase may bring some side effects during + * the SPI flash device probe (eg: for SPI controllers on a PCI bus, it + * triggers PCI bus enumeration during which insufficient memory issue + * might be exposed and it causes subsequent SPI flash probe fails). + * + * @devp: Returns pointer to the SPI flash device + * @entry: Position and size of MRC cache in SPI flash + * @return 0 if success, -ENOENT if SPI flash node does not exist in the + * device tree, -EPERM if MRC region subnode does not exist in the device + * tree, -EINVAL if MRC region properties format is incorrect, other error + * if SPI flash probe failed. + */ +int mrccache_get_region(struct udevice **devp, struct fmap_entry *entry); + +/** + * mrccache_save() - save MRC data to the SPI flash + * + * This saves MRC data stored previously by gd->arch.mrc_output to a proper + * place within the MRC region on the SPI flash. + * + * @return 0 if saved to SPI flash successfully, other error if failed + */ +int mrccache_save(void); + #endif /* _ASM_MRCCACHE_H */ -- cgit v1.1 From 4b9f6a669ee22ac4694a3a339e94e8fe30bfad1f Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 11 Oct 2015 21:37:41 -0700 Subject: x86: Use struct mrc_region to describe a mrc region Currently struct fmap_entry is used to describe a mrc region. However this structure contains some other fields that are not related to mrc cache and causes confusion. Besides, it does not include a base address field to store SPI flash's base address. Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to calculate the SPI flash base address, which unfortunately is not 100% correct as CONFIG_ROM_SIZE may not match the whole SPI flash size. Define a new struct mrc_region and use it instead. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/mrccache.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch/x86/include') diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index bcf7117..e35b5ed 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -22,7 +22,12 @@ struct __packed mrc_data_container { u8 data[0]; /* Variable size, platform/run time dependent */ }; -struct fmap_entry; +struct mrc_region { + u32 base; + u32 offset; + u32 length; +}; + struct udevice; /** @@ -34,7 +39,7 @@ struct udevice; * @entry: Position and size of MRC cache in SPI flash * @return pointer to latest record, or NULL if none */ -struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); +struct mrc_data_container *mrccache_find_current(struct mrc_region *entry); /** * mrccache_update() - update the MRC cache with a new record @@ -48,7 +53,7 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); * @return 0 if updated, -EEXIST if the record is the same as the latest * record, -EINVAL if the record is not valid, other error if SPI write failed */ -int mrccache_update(struct udevice *sf, struct fmap_entry *entry, +int mrccache_update(struct udevice *sf, struct mrc_region *entry, struct mrc_data_container *cur); /** @@ -87,7 +92,7 @@ int mrccache_reserve(void); * tree, -EINVAL if MRC region properties format is incorrect, other error * if SPI flash probe failed. */ -int mrccache_get_region(struct udevice **devp, struct fmap_entry *entry); +int mrccache_get_region(struct udevice **devp, struct mrc_region *entry); /** * mrccache_save() - save MRC data to the SPI flash -- cgit v1.1