From f2b85ab5e6a91e29c1d64304be371753d75ed172 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 18 Jan 2016 20:19:21 -0700 Subject: dm: x86: spi: Convert ICH SPI driver to driver model PCI API At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass Signed-off-by: Bin Meng Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/dts/galileo.dts | 99 +++++++++++++++++++++++++----------------------- 1 file changed, 52 insertions(+), 47 deletions(-) (limited to 'arch/x86/dts/galileo.dts') diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 55165e1..9d82bb3 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -79,37 +79,59 @@ current-speed = <115200>; }; - irq-router@1f,0 { + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; - compatible = "intel,irq-router"; - intel,pirq-config = "pci"; - intel,pirq-link = <0x60 8>; - intel,pirq-mask = <0xdef8>; - intel,pirq-routing = < - PCI_BDF(0, 20, 0) INTA PIRQE - PCI_BDF(0, 20, 1) INTB PIRQF - PCI_BDF(0, 20, 2) INTC PIRQG - PCI_BDF(0, 20, 3) INTD PIRQH - PCI_BDF(0, 20, 4) INTA PIRQE - PCI_BDF(0, 20, 5) INTB PIRQF - PCI_BDF(0, 20, 6) INTC PIRQG - PCI_BDF(0, 20, 7) INTD PIRQH - PCI_BDF(0, 21, 0) INTA PIRQE - PCI_BDF(0, 21, 1) INTB PIRQF - PCI_BDF(0, 21, 2) INTC PIRQG - PCI_BDF(0, 23, 0) INTA PIRQA - PCI_BDF(0, 23, 1) INTB PIRQB - - /* PCIe root ports downstream interrupts */ - PCI_BDF(1, 0, 0) INTA PIRQA - PCI_BDF(1, 0, 0) INTB PIRQB - PCI_BDF(1, 0, 0) INTC PIRQC - PCI_BDF(1, 0, 0) INTD PIRQD - PCI_BDF(2, 0, 0) INTA PIRQB - PCI_BDF(2, 0, 0) INTB PIRQC - PCI_BDF(2, 0, 0) INTC PIRQD - PCI_BDF(2, 0, 0) INTD PIRQA - >; + compatible = "intel,pch7"; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xdef8>; + intel,pirq-routing = < + PCI_BDF(0, 20, 0) INTA PIRQE + PCI_BDF(0, 20, 1) INTB PIRQF + PCI_BDF(0, 20, 2) INTC PIRQG + PCI_BDF(0, 20, 3) INTD PIRQH + PCI_BDF(0, 20, 4) INTA PIRQE + PCI_BDF(0, 20, 5) INTB PIRQF + PCI_BDF(0, 20, 6) INTC PIRQG + PCI_BDF(0, 20, 7) INTD PIRQH + PCI_BDF(0, 21, 0) INTA PIRQE + PCI_BDF(0, 21, 1) INTB PIRQF + PCI_BDF(0, 21, 2) INTC PIRQG + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 23, 1) INTB PIRQB + + /* PCIe root ports downstream interrupts */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + >; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x00010000 0x00010000>; + }; + }; + }; }; }; @@ -127,21 +149,4 @@ bank-name = "B"; }; - spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich-spi"; - spi-flash@0 { - #size-cells = <1>; - #address-cells = <1>; - reg = <0>; - compatible = "winbond,w25q64", "spi-flash"; - memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { - label = "rw-mrc-cache"; - reg = <0x00010000 0x00010000>; - }; - }; - }; - }; -- cgit v1.1