From faa832329932c4559a8d03d4212881b6146da5df Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 2 Feb 2015 22:35:24 +0800 Subject: x86: quark: Add routines to access message bus registers In the Quark SoC, some chipset commands are accomplished by utilizing the internal message network within the host bridge (D0:F0). Accesses to this network are accomplished by populating the message control register (MCR), Message Control Register eXtension (MCRX) and the message data register (MDR). Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/quark/msg_port.c | 77 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 arch/x86/cpu/quark/msg_port.c (limited to 'arch/x86/cpu') diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c new file mode 100644 index 0000000..31713e3 --- /dev/null +++ b/arch/x86/cpu/quark/msg_port.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void msg_port_setup(int op, int port, int reg) +{ + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, + (((op) << 24) | ((port) << 16) | + (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE)); +} + +u32 msg_port_read(u8 port, u32 reg) +{ + u32 value; + + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + msg_port_setup(MSG_OP_READ, port, reg); + pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); + + return value; +} + +void msg_port_write(u8 port, u32 reg, u32 value) +{ + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + msg_port_setup(MSG_OP_WRITE, port, reg); +} + +u32 msg_port_alt_read(u8 port, u32 reg) +{ + u32 value; + + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + msg_port_setup(MSG_OP_ALT_READ, port, reg); + pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); + + return value; +} + +void msg_port_alt_write(u8 port, u32 reg, u32 value) +{ + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + msg_port_setup(MSG_OP_ALT_WRITE, port, reg); +} + +u32 msg_port_io_read(u8 port, u32 reg) +{ + u32 value; + + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + msg_port_setup(MSG_OP_IO_READ, port, reg); + pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); + + return value; +} + +void msg_port_io_write(u8 port, u32 reg, u32 value) +{ + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); + pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, + reg & 0xffffff00); + msg_port_setup(MSG_OP_IO_WRITE, port, reg); +} -- cgit v1.1