From 191c008a2155f99fc6476539878640b4032a457b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 19 Jan 2015 22:16:14 -0700 Subject: x86: Implement a cache for Memory Reference Code parameters The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/x86/cpu/ivybridge/Makefile') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 0c7efae..3576b83 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -14,6 +14,7 @@ obj-y += lpc.o obj-y += me_status.o obj-y += model_206ax.o obj-y += microcode_intel.o +obj-y += mrccache.o obj-y += northbridge.o obj-y += pch.o obj-y += pci.o -- cgit v1.1