From e46fedfeb214d118b9983d11fcc929ed49f5ccd7 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Thu, 4 Aug 2011 18:03:41 -0500 Subject: powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7de8f74..691c075 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -23,6 +23,10 @@ /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ +#ifdef CONFIG_SYS_CCSRBAR_DEFAULT +#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." +#endif + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 @@ -34,34 +38,41 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8540) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8541) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8544) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8560) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8568) #define CONFIG_MAX_CPUS 1 @@ -70,6 +81,7 @@ #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8569) #define CONFIG_MAX_CPUS 1 @@ -78,11 +90,13 @@ #define QE_MURAM_SIZE 0x20000UL #define MAX_QE_RISC 4 #define QE_NUM_OF_SNUM 46 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 @@ -106,6 +120,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -116,6 +131,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -128,6 +144,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 @@ -151,6 +168,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -166,6 +184,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) @@ -179,6 +198,7 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -186,6 +206,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -195,6 +216,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -206,6 +228,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 @@ -221,6 +244,7 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -229,6 +253,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -239,6 +264,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -250,6 +276,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -257,6 +284,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -271,6 +299,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -288,6 +317,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -305,6 +335,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -318,6 +349,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -333,6 +365,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -359,6 +392,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -376,6 +410,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -385,4 +420,8 @@ #error Processor type not defined for this platform #endif +#ifndef CONFIG_SYS_CCSRBAR_DEFAULT +#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ -- cgit v1.1