From c1ab75c7d4e5d080c630335b78681c50aa3569a5 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 26 Aug 2010 17:14:51 +0200 Subject: ppc4xx: Fix 440EPx bug in reconfigure_pll() This patch fixes a bug in reconfigure_pll(), where the detection of the current bootstrap option is wrong. The ICS bits where incorrectly shifted. This bug was found on the lwmon5 board, which uses bootstrap option H (I2C bootstrap EEPROM). Additionally a bit of code was moved into the if statement, since its only used after later on. No need to run this code all the time. Also, a few empty lines are added to make the code better readable. Signed-off-by: Stefan Roese Cc: Rupjyoti Sarmah Cc: Victor Gallardo --- arch/powerpc/cpu/ppc4xx/cpu_init.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede..b31bd0b 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq) * modify it. */ if (temp == 1) { - mfcpr(CPR0_PLLD, reg); - /* Get current value of fbdv. */ - temp = (reg & PLLD_FBDV_MASK) >> 24; - fbdv = temp ? temp : 32; - /* Get current value of lfbdv. */ - temp = (reg & PLLD_LFBDV_MASK); - lfbdv = temp ? temp : 64; /* * Load register that contains current boot strapping option. */ mfcpr(CPR0_ICFG, reg); - /* Shift strapping option into low 3 bits.*/ - reg = (reg >> 28); + /* + * Strapping option bits (ICS) are already in correct position, + * only masking needed. + */ + reg &= CPR0_ICFG_ICS_MASK; if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { + mfcpr(CPR0_PLLD, reg); + + /* Get current value of fbdv. */ + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + + /* Get current value of lfbdv. */ + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + /* * Get current value of FWDVA. Assign current FWDVA to * new FWDVB. @@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq) mfcpr(CPR0_PLLD, reg); target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; fwdvb = target_fwdvb ? target_fwdvb : 8; + /* * Get current value of FWDVB. Assign current FWDVB to * new FWDVA. */ target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; fwdva = target_fwdva ? target_fwdva : 16; + /* * Update CPR0_PLLD with switched FWDVA and FWDVB. */ @@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq) ((fbdv == 32 ? 0 : fbdv) << 24) | (lfbdv == 64 ? 0 : lfbdv); mtcpr(CPR0_PLLD, reg); + /* Acknowledge that a reset is required. */ reset_needed = 1; } -- cgit v1.1 From f3cac5384074f3c20b5bcbbdbccbe1e2e25ffc76 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 31 Aug 2010 11:27:14 +0200 Subject: ppc4xx: Invalidate d-cache when used as init-ram We need to invalidate the data cache after it has been used as init-ram. This problem was detected on the lwmon5 update. Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/start.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 5296dad..4bad32f 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1459,6 +1459,11 @@ relocate_code: mtspr SPRN_DTV3,r6 msync isync + + /* Invalidate data cache, now no longer our stack */ + dccci 0,0 + sync + isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ /* -- cgit v1.1