From 06f60ae3e454e15a410a0d4e96769bf938af8fcb Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Thu, 6 Dec 2012 13:33:17 +0000
Subject: powerpc/mpc83xx: add support for new SPL

This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs
using the new infrastructure.

Existing nand_spl targets are updated to deal with the name change
from nand_init.c to spl_minimal.c (as in theory this isn't limited
to NAND anymore).

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 arch/powerpc/cpu/mpc83xx/Makefile       |  16 +++++
 arch/powerpc/cpu/mpc83xx/nand_init.c    | 112 --------------------------------
 arch/powerpc/cpu/mpc83xx/spl_minimal.c  | 112 ++++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc83xx/start.S        |  31 +++++----
 arch/powerpc/cpu/mpc83xx/u-boot-spl.lds |  55 ++++++++++++++++
 arch/powerpc/lib/Makefile               |   3 +-
 6 files changed, 204 insertions(+), 125 deletions(-)
 delete mode 100644 arch/powerpc/cpu/mpc83xx/nand_init.c
 create mode 100644 arch/powerpc/cpu/mpc83xx/spl_minimal.c
 create mode 100644 arch/powerpc/cpu/mpc83xx/u-boot-spl.lds

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 687f5e9..8a470b8 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -27,8 +27,22 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
 START	= start.o
 
+ifdef MINIMAL
+
+COBJS-y	+= spl_minimal.o
+
+else
+
 COBJS-y += traps.o
 COBJS-y += cpu.o
 COBJS-y += cpu_init.o
@@ -51,6 +65,8 @@ COBJS-y += spd_sdram.o
 endif
 COBJS-$(CONFIG_FSL_DDR2) += law.o
 
+endif # not minimal
+
 COBJS	:= $(COBJS-y)
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
diff --git a/arch/powerpc/cpu/mpc83xx/nand_init.c b/arch/powerpc/cpu/mpc83xx/nand_init.c
deleted file mode 100644
index d1648b7..0000000
--- a/arch/powerpc/cpu/mpc83xx/nand_init.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Breathe some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f (volatile immap_t * im)
-{
-	int i;
-
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-	/* Clear initial global data */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-
-	/* system performance tweaking */
-
-#ifdef CONFIG_SYS_ACR_PIPE_DEP
-	/* Arbiter pipeline depth */
-	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
-			  (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_ACR_RPTCNT
-	/* Arbiter repeat count */
-	im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
-			  (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
-#endif
-
-#ifdef CONFIG_SYS_SPCR_OPT
-	/* Optimize transactions between CSB and other devices */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
-			   (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
-#endif
-
-	/* Enable Time Base & Decrimenter (so we will have udelay()) */
-	im->sysconf.spcr |= SPCR_TBEN;
-
-	/* DDR control driver register */
-#ifdef CONFIG_SYS_DDRCDR
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
-#endif
-	/* Output buffer impedance register */
-#ifdef CONFIG_SYS_OBIR
-	im->sysconf.obir = CONFIG_SYS_OBIR;
-#endif
-
-	/*
-	 * Memory Controller:
-	 */
-
-	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
-	 * addresses - these have to be modified later when FLASH size
-	 * has been determined
-	 */
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM)  \
-	&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
-	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
-	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
-	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
-#else
-#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
-#endif
-}
-
-/*
- * Get timebase clock frequency (like cpu_clk in Hz)
- */
-unsigned long get_tbclk(void)
-{
-	return (gd->bus_clk + 3L) / 4L;
-}
-
-void puts(const char *str)
-{
-	while (*str)
-		putc(*str++);
-}
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
new file mode 100644
index 0000000..d1648b7
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f (volatile immap_t * im)
+{
+	int i;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+	/* Clear initial global data */
+	for (i = 0; i < sizeof(gd_t); i++)
+		((char *)gd)[i] = 0;
+
+	/* system performance tweaking */
+
+#ifdef CONFIG_SYS_ACR_PIPE_DEP
+	/* Arbiter pipeline depth */
+	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
+			  (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+#endif
+
+#ifdef CONFIG_SYS_ACR_RPTCNT
+	/* Arbiter repeat count */
+	im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
+			  (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+#endif
+
+#ifdef CONFIG_SYS_SPCR_OPT
+	/* Optimize transactions between CSB and other devices */
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
+			   (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
+#endif
+
+	/* Enable Time Base & Decrimenter (so we will have udelay()) */
+	im->sysconf.spcr |= SPCR_TBEN;
+
+	/* DDR control driver register */
+#ifdef CONFIG_SYS_DDRCDR
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
+#endif
+	/* Output buffer impedance register */
+#ifdef CONFIG_SYS_OBIR
+	im->sysconf.obir = CONFIG_SYS_OBIR;
+#endif
+
+	/*
+	 * Memory Controller:
+	 */
+
+	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
+	 * addresses - these have to be modified later when FLASH size
+	 * has been determined
+	 */
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM)  \
+	&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
+	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
+	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
+	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
+#else
+#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
+#endif
+}
+
+/*
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ */
+unsigned long get_tbclk(void)
+{
+	return (gd->bus_clk + 3L) / 4L;
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index b70b4ca..44a64b7 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -58,7 +58,13 @@
 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
 #endif
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_NAND_SPL) || \
+	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+#define MINIMAL_SPL
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
+	!defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_FLASHBOOT
 #endif
 
@@ -72,7 +78,7 @@
 	GOT_ENTRY(__bss_start)
 	GOT_ENTRY(__bss_end__)
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	GOT_ENTRY(_FIXUP_TABLE_)
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
@@ -206,7 +212,8 @@ _start: /* time t 0 */
 	/* Initialise the E300 processor core		*/
 	/*------------------------------------------*/
 
-#ifdef CONFIG_NAND_SPL
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
+		defined(CONFIG_NAND_SPL)
 	/* The FCM begins execution after only the first page
 	 * is loaded.  Wait for the rest before branching
 	 * to another flash page.
@@ -292,7 +299,7 @@ in_flash:
 
 	/* NOTREACHED - board_init_f() does not return */
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 /*
  * Vector Table
  */
@@ -467,7 +474,7 @@ int_return:
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfi
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
 
 /*
  * This code initialises the E300 processor core
@@ -724,7 +731,7 @@ setup_bats:
  * Note: requires that all cache bits in
  * HID0 are in the low half word.
  */
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	.globl	icache_enable
 icache_enable:
 	mfspr	r3, HID0
@@ -753,7 +760,7 @@ icache_status:
 	mfspr	r3, HID0
 	rlwinm	r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
 	blr
-#endif	/* !CONFIG_NAND_SPL */
+#endif	/* !MINIMAL_SPL */
 
 	.globl	dcache_enable
 dcache_enable:
@@ -936,7 +943,7 @@ in_ram:
 	stw	r0,0(r3)
 2:	bdnz	1b
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	/*
 	 * Now adjust the fixups and the pointers to the fixups
 	 * in case we need to move ourselves again.
@@ -991,7 +998,7 @@ clear_bss:
 	mr	r4, r10		/* Destination Address		*/
 	bl	board_init_r
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	/*
 	 * Copy exception vector code to low memory
 	 *
@@ -1061,7 +1068,7 @@ trap_init:
 	mtlr	r4			/* restore link register    */
 	blr
 
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
 
 #ifdef CONFIG_SYS_INIT_RAM_LOCK
 lock_ram_in_cache:
@@ -1085,7 +1092,7 @@ lock_ram_in_cache:
 	sync
 	blr
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
@@ -1111,7 +1118,7 @@ unlock_ram_in_cache:
 	sync
 	mtspr	HID0, r3		/* no invalidate, unlock */
 	blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
 
 #ifdef CONFIG_SYS_FLASHBOOT
diff --git a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
new file mode 100644
index 0000000..d140453
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+	. = 0xfff00000;
+	.text : {
+		*(.text*)
+		. = ALIGN(16);
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(8);
+	.data : {
+		*(.data*)
+		*(.sdata*)
+		_GOT2_TABLE_ = .;
+		KEEP(*(.got2))
+		KEEP(*(.got))
+		PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+	}
+	__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+
+	. = ALIGN(8);
+	__bss_start = .;
+	.bss (NOLOAD) : {
+		*(.*bss)
+	}
+	__bss_end__ = .;
+}
+ENTRY(_start)
+ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big");
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 844fe86..86cf02a 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -47,7 +47,8 @@ endif
 endif
 
 ifdef MINIMAL
-COBJS-y += cache.o
+COBJS-y += cache.o time.o
+SOBJS-y += ticks.o
 else
 
 SOBJS-y	+= ppcstring.o
-- 
cgit v1.1


From 2d9f26b69377b3a5953d4422724069d9456c2684 Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Fri, 14 Dec 2012 06:21:58 +0000
Subject: powerpc/mpc85xx: Reserve default boot page

The boot page in memory is already reserved so OS won't overwrite.
As long as the boot page translation is active, the default boot page
also needs to be reserved in case the memory is 4GB or more.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/fdt.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index ab09330..16d7f6a 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -100,6 +100,22 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 			printf("Failed to reserve memory for bootpg: %s\n",
 				fdt_strerror(off));
 	}
+
+#ifndef CONFIG_MPC8xxx_DISABLE_BPTR
+	/*
+	 * Reserve the default boot page so OSes dont use it.
+	 * The default boot page is always mapped to bootpg above using
+	 * boot page translation.
+	 */
+	if (0xfffff000ull < memory_limit) {
+		off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
+		if (off < 0) {
+			printf("Failed to reserve memory for 0xfffff000: %s\n",
+				fdt_strerror(off));
+		}
+	}
+#endif
+
 	/* Reserve spin table page */
 	if (spin_tbl_addr < memory_limit) {
 		off = fdt_add_mem_rsv(blob,
-- 
cgit v1.1


From e394ceb17f93545e6b89b6d04df348dc435e2d4f Mon Sep 17 00:00:00 2001
From: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Date: Sun, 23 Dec 2012 19:22:33 +0000
Subject: powerpc/mpc85xx: Few updates for B4860 cpu changes

- Added some more serdes1 and serdes2 combinations
  serdes1= 0x2c, 0x2d, 0x2e
  serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/b4860_serdes.c   | 15 +++++++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h |  2 +-
 2 files changed, 16 insertions(+), 1 deletion(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index 9990202..0028280 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -41,6 +41,12 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x30, {AURORA, AURORA,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
@@ -84,6 +90,8 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 	{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
 	{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2, AURORA, AURORA,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
@@ -94,6 +102,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 		SRIO2, SRIO2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
 	{0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
@@ -111,6 +122,10 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 	{0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
 	{}
 };
 static struct serdes_config *serdes_cfg_tbl[] = {
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 0b9638b..856ae95 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -537,7 +537,7 @@
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
 #define CONFIG_SYS_NUM_FM1_10GEC	2
-#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
-- 
cgit v1.1


From e1dbdd81523c7c7de1ac5dee03dd9e4587e808af Mon Sep 17 00:00:00 2001
From: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Date: Sun, 23 Dec 2012 19:24:16 +0000
Subject: powerpc/mpc85xx:Add support of B4420 SoC

B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.

Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/Makefile         |  3 +++
 arch/powerpc/cpu/mpc85xx/b4860_ids.c      |  6 +++++
 arch/powerpc/cpu/mpc85xx/b4860_serdes.c   | 45 +++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h | 21 +++++++++++++++
 arch/powerpc/include/asm/immap_85xx.h     |  2 +-
 5 files changed, 76 insertions(+), 1 deletion(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 4c2b104..95994d3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -83,6 +83,7 @@ COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5040)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_T4240)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_B4420)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4860)	+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
 
@@ -100,6 +101,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
 
 COBJS-$(CONFIG_QE)	+= qe_io.o
@@ -134,6 +136,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
 
 COBJS-y	+= cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 7d33731..0f4e82e 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -55,11 +55,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
 };
 #endif
 
+#ifdef CONFIG_SYS_SRIO
 struct srio_liodn_id_table srio_liodn_tbl[] = {
 	SET_SRIO_LIODN_1(1, 307),
 	SET_SRIO_LIODN_1(2, 387),
 };
 int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
 
 struct liodn_id_table liodn_tbl[] = {
 #ifdef CONFIG_SYS_DPAA_QBMAN
@@ -76,10 +78,12 @@ struct liodn_id_table liodn_tbl[] = {
 	SET_DMA_LIODN(1, 147),
 	SET_DMA_LIODN(2, 227),
 
+#ifndef CONFIG_PPC_B4420
 	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
 	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
 	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
 	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+#endif
 
 	/* SET_NEXUS_LIODN(557), -- not yet implemented */
 };
@@ -93,8 +97,10 @@ struct liodn_id_table fman1_liodn_tbl[] = {
 	SET_FMAN_RX_1G_LIODN(1, 3, 91),
 	SET_FMAN_RX_1G_LIODN(1, 4, 92),
 	SET_FMAN_RX_1G_LIODN(1, 5, 93),
+#ifndef CONFIG_PPC_B4420
 	SET_FMAN_RX_10G_LIODN(1, 0, 94),
 	SET_FMAN_RX_10G_LIODN(1, 1, 95),
+#endif
 };
 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index 0028280..bd32342 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -31,6 +31,7 @@ struct serdes_config {
 	u8 lanes[SRDS_MAX_LANES];
 };
 
+#ifdef CONFIG_PPC_B4860
 static struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
 	{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
@@ -128,6 +129,50 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
 	{}
 };
+#endif
+
+#ifdef CONFIG_PPC_B4420
+static struct serdes_config serdes1_cfg_tbl[] = {
+	{0x0D, {NONE, NONE, CPRI6, CPRI5,
+		CPRI4, CPRI3, NONE, NONE} },
+	{0x0E, {NONE, NONE, CPRI8, CPRI5,
+		CPRI4, CPRI3, NONE, NONE} },
+	{0x0F, {NONE, NONE, CPRI6, CPRI5,
+		CPRI4, CPRI3, NONE, NONE} },
+	{0x18, {NONE, NONE,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
+	{0x1B, {NONE, NONE,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
+	{0x1E, {NONE, NONE, AURORA, AURORA,
+		NONE, NONE, NONE, NONE} },
+	{0x21, {NONE, NONE, AURORA, AURORA,
+		NONE, NONE, NONE, NONE} },
+	{0x3E, {NONE, NONE, CPRI6, CPRI5,
+		CPRI4, CPRI3, NONE, NONE} },
+	{}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		NONE, NONE, NONE, NONE} },
+	{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		NONE, NONE, NONE, NONE} },
+	{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
+	{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
+	{0x9A, {PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
+	{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
+		NONE, NONE, NONE, NONE} },
+	{}
+};
+#endif
+
 static struct serdes_config *serdes_cfg_tbl[] = {
 	serdes1_cfg_tbl,
 	serdes2_cfg_tbl,
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 856ae95..f957fa3 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -525,6 +525,27 @@
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
+#elif defined(CONFIG_PPC_B4420)
+#define CONFIG_SYS_PPC64		/* 64-bit core */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+
 #elif defined(CONFIG_PPC_B4860)
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 296b549..6a818c4 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1840,7 +1840,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT	11
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL		0x000000f8
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT	3
-#elif defined(CONFIG_PPC_B4860)
+#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xfe000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
-- 
cgit v1.1


From db9a807054ec82f4f6352677ea8b5d8176050a8a Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar@freescale.com>
Date: Sun, 23 Dec 2012 19:25:18 +0000
Subject: powerpc/mpc85xx:Fix Core cluster configuration loop

Different personalities/derivatives of SoC may have reduced cluster. But it is
not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have
DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters".

EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC
which may not be valid for the personality.
So add initiator type check to find valid cluster.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c | 30 ++++++++++++++++++++++--------
 1 file changed, 22 insertions(+), 8 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d1155e8..cc09300 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -312,19 +312,33 @@ int enable_cluster_l2(void)
 
 	/* Look through the remaining clusters, and set up their caches */
 	do {
+		int j, cluster_valid = 0;
+
 		l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+
 		cluster = in_be32(&gur->tp_cluster[i].lower);
 
-		/* set stash ID to (cluster) * 2 + 32 + 1 */
-		clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+		/* check that at least one core/accel is enabled in cluster */
+		for (j = 0; j < 4; j++) {
+			u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
+			u32 type = in_be32(&gur->tp_ityp[idx]);
 
-		printf("enable l2 for cluster %d %p\n", i, l2cache);
+			if (type & TP_ITYP_AV)
+				cluster_valid = 1;
+		}
 
-		out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
-		while ((in_be32(&l2cache->l2csr0) &
-			(L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
-			;
-		out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+		if (cluster_valid) {
+			/* set stash ID to (cluster) * 2 + 32 + 1 */
+			clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+
+			printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+			out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+			while ((in_be32(&l2cache->l2csr0)
+				& (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+					;
+			out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+		}
 		i++;
 	} while (!(cluster & TP_CLUSTER_EOC));
 
-- 
cgit v1.1


From e750cfaa01f195be3f3bf16d7f1be7b99b587351 Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Fri, 4 Jan 2013 08:13:59 +0000
Subject: powerpc/mpc8xxx: Enable entering DDR debugging by key press

Using environmental variable "ddr_interactive" to activate interactive DDR
debugging seomtiems is not enough. For example, after updating SPD with a
valid but wrong image, u-boot won't come up due to wrong DDR configuration.
By enabling key press method, we can enter debug mode to have a chance to
boot without using other tools to recover the board.

CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the
debug mode by key press, press key 'd' shortly after reset, like one would
do to abort auto booting. It is fixed to lower case 'd' at this moment.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/main.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index d6b73c7..a33c9e2 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -532,9 +532,11 @@ phys_size_t fsl_ddr_sdram(void)
 
 	/* Compute it once normally. */
 #ifdef CONFIG_FSL_DDR_INTERACTIVE
-	if (getenv("ddr_interactive"))
+	if (getenv("ddr_interactive")) {
 		total_memory = fsl_ddr_interactive(&info);
-	else
+	} else if (tstc() && (getc() == 'd')) {	/* we got a key press of 'd' */
+		total_memory = fsl_ddr_interactive(&info);
+	} else
 #endif
 		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 
-- 
cgit v1.1


From bf4189307fe4a3df784722e831683f9a7fdd2142 Mon Sep 17 00:00:00 2001
From: James Yang <James.Yang@freescale.com>
Date: Fri, 4 Jan 2013 08:14:00 +0000
Subject: Move DDR command parsing to separate function

Move the FSL DDR prompt command parsing to a separate function
so that it can be reused.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 153 ++++++++++++++---------------
 1 file changed, 74 insertions(+), 79 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index cb71f94..4d1cf3c 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -1369,14 +1369,15 @@ struct data_strings {
 
 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
 
-unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
-{
-	unsigned long long ddrsize;
-	const char *prompt = "FSL DDR>";
-	char buffer[CONFIG_SYS_CBSIZE];
-	char *argv[CONFIG_SYS_MAXARGS + 1];	/* NULL terminated */
-	int argc;
-	unsigned int next_step = STEP_GET_SPD;
+static unsigned int fsl_ddr_parse_interactive_cmd(
+	char **argv,
+	int argc,
+	unsigned int *pstep_mask,
+	unsigned int *pctlr_mask,
+	unsigned int *pdimm_mask,
+	unsigned int *pdimm_number_required
+	 ) {
+
 	static const struct data_strings options[] = {
 		DATA_OPTIONS(spd, STEP_GET_SPD, 1),
 		DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
@@ -1386,6 +1387,56 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 		DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	unsigned int i, j;
+	unsigned int error = 0;
+	unsigned int matched = 0;
+
+	for (i = 1; i < argc; i++) {
+		for (j = 0; j < n_opts; j++) {
+			if (strcmp(options[j].data_name, argv[i]) != 0)
+				continue;
+			*pstep_mask |= options[j].step_mask;
+			*pdimm_number_required =
+				options[j].dimm_number_required;
+			matched = 1;
+			break;
+		}
+
+		if (matched)
+			continue;
+
+		if (argv[i][0] == 'c') {
+			char c = argv[i][1];
+			if (isdigit(c))
+				*pctlr_mask |= 1 << (c - '0');
+			continue;
+		}
+
+		if (argv[i][0] == 'd') {
+			char c = argv[i][1];
+			if (isdigit(c))
+				*pdimm_mask |= 1 << (c - '0');
+			continue;
+		}
+
+		printf("unknown arg %s\n", argv[i]);
+		*pstep_mask = 0;
+		error = 1;
+		break;
+	}
+
+	return error;
+}
+
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
+{
+	unsigned long long ddrsize;
+	const char *prompt = "FSL DDR>";
+	char buffer[CONFIG_SYS_CBSIZE];
+	char *argv[CONFIG_SYS_MAXARGS + 1];	/* NULL terminated */
+	int argc;
+	unsigned int next_step = STEP_GET_SPD;
 	const char *usage = {
 		"commands:\n"
 		"print      print SPD and intermediate computed data\n"
@@ -1426,7 +1477,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 		}
 
 		if (strcmp(argv[0], "edit") == 0) {
-			unsigned int i, j;
 			unsigned int error = 0;
 			unsigned int step_mask = 0;
 			unsigned int ctlr_mask = 0;
@@ -1436,7 +1486,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 			unsigned int dimm_number_required = 0;
 			unsigned int ctrl_num;
 			unsigned int dimm_num;
-			unsigned int matched = 0;
 
 			if (argc == 1) {
 				/* Only the element and value must be last */
@@ -1448,41 +1497,13 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 				continue;
 			}
 
-			for (i = 1; i < argc - 2; i++) {
-				for (j = 0; j < n_opts; j++) {
-					if (strcmp(options[j].data_name,
-						argv[i]) != 0)
-						continue;
-					step_mask |= options[j].step_mask;
-					dimm_number_required =
-						options[j].dimm_number_required;
-					matched = 1;
-					break;
-				}
-
-				if (matched)
-					continue;
-
-				if (argv[i][0] == 'c') {
-					char c = argv[i][1];
-					if (isdigit(c))
-						ctlr_mask |= 1 << (c - '0');
-					continue;
-				}
-
-				if (argv[i][0] == 'd') {
-					char c = argv[i][1];
-					if (isdigit(c))
-						dimm_mask |= 1 << (c - '0');
-					continue;
-				}
-
-				printf("unknown arg %s\n", argv[i]);
-				step_mask = 0;
-				error = 1;
-				break;
-			}
-
+			error = fsl_ddr_parse_interactive_cmd(
+				argv, argc - 2,
+				&step_mask,
+				&ctlr_mask,
+				&dimm_mask,
+				&dimm_number_required
+			);
 
 			if (error)
 				continue;
@@ -1629,12 +1650,11 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 		}
 
 		if (strcmp(argv[0], "print") == 0) {
-			unsigned int i, j;
 			unsigned int error = 0;
 			unsigned int step_mask = 0;
 			unsigned int ctlr_mask = 0;
 			unsigned int dimm_mask = 0;
-			unsigned int matched = 0;
+			unsigned int dimm_number_required = 0;
 
 			if (argc == 1) {
 				printf("print [c<n>] [d<n>] [spd] [dimmparms] "
@@ -1642,38 +1662,13 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 				continue;
 			}
 
-			for (i = 1; i < argc; i++) {
-				for (j = 0; j < n_opts; j++) {
-					if (strcmp(options[j].data_name,
-						argv[i]) != 0)
-						continue;
-					step_mask |= options[j].step_mask;
-					matched = 1;
-					break;
-				}
-
-				if (matched)
-					continue;
-
-				if (argv[i][0] == 'c') {
-					char c = argv[i][1];
-					if (isdigit(c))
-						ctlr_mask |= 1 << (c - '0');
-					continue;
-				}
-
-				if (argv[i][0] == 'd') {
-					char c = argv[i][1];
-					if (isdigit(c))
-						dimm_mask |= 1 << (c - '0');
-					continue;
-				}
-
-				printf("unknown arg %s\n", argv[i]);
-				step_mask = 0;
-				error = 1;
-				break;
-			}
+			error = fsl_ddr_parse_interactive_cmd(
+				argv, argc,
+				&step_mask,
+				&ctlr_mask,
+				&dimm_mask,
+				&dimm_number_required
+			);
 
 			if (error)
 				continue;
-- 
cgit v1.1


From 992f2fb28ccce08613a34ce64b151f3a91ee3c3a Mon Sep 17 00:00:00 2001
From: James Yang <James.Yang@freescale.com>
Date: Fri, 4 Jan 2013 08:14:01 +0000
Subject: Fix data stage name matching issue

This fix allows the name of the stage to be specifed after the
controler and DIMM is specified.  Prior to this fix, if the
data stage name is not the first entry on the command line,
the operation is applied to all controller and DIMMs.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index 4d1cf3c..0474acc 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -1390,9 +1390,10 @@ static unsigned int fsl_ddr_parse_interactive_cmd(
 
 	unsigned int i, j;
 	unsigned int error = 0;
-	unsigned int matched = 0;
 
 	for (i = 1; i < argc; i++) {
+		unsigned int matched = 0;
+
 		for (j = 0; j < n_opts; j++) {
 			if (strcmp(options[j].data_name, argv[i]) != 0)
 				continue;
-- 
cgit v1.1


From 5926ee3800b3b09026993117318e09a8ddc33e2e Mon Sep 17 00:00:00 2001
From: James Yang <James.Yang@freescale.com>
Date: Fri, 4 Jan 2013 08:14:02 +0000
Subject: Add copy command to FSL DDR interactive

Add copy command which allows copying of DIMM/controller settings.
This saves tedious retyping of parameters for each identical DIMM
or controller.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 127 +++++++++++++++++++++++++++++
 1 file changed, 127 insertions(+)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index 0474acc..e5ee775 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -1445,6 +1445,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 		"recompute  reload SPD and options to default and recompute regs\n"
 		"edit       modify spd, parameter, or option\n"
 		"compute    recompute registers from current next_step to end\n"
+		"copy       copy parameters\n"
 		"next_step  shows current next_step\n"
 		"help       this message\n"
 		"go         program the memory controller and continue with u-boot\n"
@@ -1477,6 +1478,132 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 			continue;
 		}
 
+		if (strcmp(argv[0], "copy") == 0) {
+			unsigned int error = 0;
+			unsigned int step_mask = 0;
+			unsigned int src_ctlr_mask = 0;
+			unsigned int src_dimm_mask = 0;
+			unsigned int dimm_number_required = 0;
+			unsigned int src_ctlr_num = 0;
+			unsigned int src_dimm_num = 0;
+			unsigned int dst_ctlr_num = -1;
+			unsigned int dst_dimm_num = -1;
+			unsigned int i, num_dest_parms;
+
+			if (argc == 1) {
+				printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
+				continue;
+			}
+
+			error = fsl_ddr_parse_interactive_cmd(
+				argv, argc,
+				&step_mask,
+				&src_ctlr_mask,
+				&src_dimm_mask,
+				&dimm_number_required
+			);
+
+			/* XXX: only dimm_number_required and step_mask will
+			   be used by this function.  Parse the controller and
+			   DIMM number separately because it is easier.  */
+
+			if (error)
+				continue;
+
+			/* parse source destination controller / DIMM */
+
+			num_dest_parms = dimm_number_required ? 2 : 1;
+
+			for (i = 0; i < argc; i++) {
+				if (argv[i][0] == 'c') {
+					char c = argv[i][1];
+					if (isdigit(c)) {
+						src_ctlr_num = (c - '0');
+						break;
+					}
+				}
+			}
+
+			for (i = 0; i < argc; i++) {
+				if (argv[i][0] == 'd') {
+					char c = argv[i][1];
+					if (isdigit(c)) {
+						src_dimm_num = (c - '0');
+						break;
+					}
+				}
+			}
+
+			/* parse destination controller / DIMM */
+
+			for (i = argc - 1; i >= argc - num_dest_parms; i--) {
+				if (argv[i][0] == 'c') {
+					char c = argv[i][1];
+					if (isdigit(c)) {
+						dst_ctlr_num = (c - '0');
+						break;
+					}
+				}
+			}
+
+			for (i = argc - 1; i >= argc - num_dest_parms; i--) {
+				if (argv[i][0] == 'd') {
+					char c = argv[i][1];
+					if (isdigit(c)) {
+						dst_dimm_num = (c - '0');
+						break;
+					}
+				}
+			}
+
+			/* TODO: validate inputs */
+
+			debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
+				src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
+
+
+			switch (step_mask) {
+
+			case STEP_GET_SPD:
+				memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
+					&(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
+					sizeof(pinfo->spd_installed_dimms[0][0]));
+				break;
+
+			case STEP_COMPUTE_DIMM_PARMS:
+				memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
+					&(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
+					sizeof(pinfo->dimm_params[0][0]));
+				break;
+
+			case STEP_COMPUTE_COMMON_PARMS:
+				memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
+					&(pinfo->common_timing_params[src_ctlr_num]),
+					sizeof(pinfo->common_timing_params[0]));
+				break;
+
+			case STEP_GATHER_OPTS:
+				memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
+					&(pinfo->memctl_opts[src_ctlr_num]),
+					sizeof(pinfo->memctl_opts[0]));
+				break;
+
+			/* someday be able to have addresses to copy addresses... */
+
+			case STEP_COMPUTE_REGS:
+				memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
+					&(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
+					sizeof(pinfo->memctl_opts[0]));
+				break;
+
+			default:
+				printf("unexpected step_mask value\n");
+			}
+
+			continue;
+
+		}
+
 		if (strcmp(argv[0], "edit") == 0) {
 			unsigned int error = 0;
 			unsigned int step_mask = 0;
-- 
cgit v1.1


From e8ba6c503ffea6bcb7abba3638cc3f880d060504 Mon Sep 17 00:00:00 2001
From: James Yang <James.Yang@freescale.com>
Date: Mon, 7 Jan 2013 14:01:03 +0000
Subject: powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commands

This patch adds the ability for the FSL DDR interactive debugger to
automatically run the sequence of commands stored in the ddr_interactive
environment variable.  Commands are separated using ';'.

ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/ddr.h         |  3 +-
 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 47 ++++++++++++++++++++++++++----
 arch/powerpc/cpu/mpc8xxx/ddr/main.c        |  8 ++---
 3 files changed, 47 insertions(+), 11 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index c8b0f91..4dd55fc 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -86,7 +86,8 @@ void fsl_ddr_set_lawbar(
 		unsigned int memctl_interleaved,
 		unsigned int ctrl_num);
 
-unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo);
+int fsl_ddr_interactive_env_var_exists(void);
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 			   unsigned int ctrl_num);
 
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index e5ee775..46257c9 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -1430,11 +1430,23 @@ static unsigned int fsl_ddr_parse_interactive_cmd(
 	return error;
 }
 
-unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
+int fsl_ddr_interactive_env_var_exists(void)
+{
+	char buffer[CONFIG_SYS_CBSIZE];
+
+	if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
+		return 1;
+
+	return 0;
+}
+
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
 {
 	unsigned long long ddrsize;
 	const char *prompt = "FSL DDR>";
 	char buffer[CONFIG_SYS_CBSIZE];
+	char buffer2[CONFIG_SYS_CBSIZE];
+	char *p = NULL;
 	char *argv[CONFIG_SYS_MAXARGS + 1];	/* NULL terminated */
 	int argc;
 	unsigned int next_step = STEP_GET_SPD;
@@ -1451,16 +1463,39 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 		"go         program the memory controller and continue with u-boot\n"
 	};
 
+	if (var_is_set) {
+		if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
+			p = buffer2;
+		} else {
+			var_is_set = 0;
+		}
+	}
+
 	/*
 	 * The strategy for next_step is that it points to the next
 	 * step in the computation process that needs to be done.
 	 */
 	while (1) {
-		/*
-		 * No need to worry for buffer overflow here in
-		 * this function;  readline() maxes out at CFG_CBSIZE
-		 */
-		readline_into_buffer(prompt, buffer, 0);
+		if (var_is_set) {
+			char *pend = strchr(p, ';');
+			if (pend) {
+				/* found command separator, copy sub-command */
+				*pend = '\0';
+				strcpy(buffer, p);
+				p = pend + 1;
+			} else {
+				/* separator not found, copy whole string */
+				strcpy(buffer, p);
+				p = NULL;
+				var_is_set = 0;
+			}
+		} else {
+			/*
+			 * No need to worry for buffer overflow here in
+			 * this function;  readline() maxes out at CFG_CBSIZE
+			 */
+			readline_into_buffer(prompt, buffer, 0);
+		}
 		argc = parse_line(buffer, argv);
 		if (argc == 0)
 			continue;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index a33c9e2..5311a26 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -532,10 +532,10 @@ phys_size_t fsl_ddr_sdram(void)
 
 	/* Compute it once normally. */
 #ifdef CONFIG_FSL_DDR_INTERACTIVE
-	if (getenv("ddr_interactive")) {
-		total_memory = fsl_ddr_interactive(&info);
-	} else if (tstc() && (getc() == 'd')) {	/* we got a key press of 'd' */
-		total_memory = fsl_ddr_interactive(&info);
+	if (tstc() && (getc() == 'd')) {	/* we got a key press of 'd' */
+		total_memory = fsl_ddr_interactive(&info, 0);
+	} else if (fsl_ddr_interactive_env_var_exists()) {
+		total_memory = fsl_ddr_interactive(&info, 1);
 	} else
 #endif
 		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
-- 
cgit v1.1


From 35fe948e3b62789182610f57d48f97dbd5403aa8 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar@freescale.com>
Date: Wed, 23 Jan 2013 17:59:57 +0000
Subject: powerpc/mpc85xx: Add BSC9132/BSC9232 processor support

The BSC9132 is a highly integrated device that targets the evolving
 Microcell, Picocell, and Enterprise-Femto base station market subsegments.

 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
 core technologies with MAPLE-B2P baseband acceleration processing elements
 to address the need for a high performance, low cost, integrated solution
 that handles all required processing layers without the need for an
 external device except for an RF transceiver or, in a Micro base station
 configuration, a host device that handles the L3/L4 and handover between
 sectors.

 The BSC9132 SoC includes the following function and features:
    - Power Architecture subsystem including two e500 processors with
	512-Kbyte shared L2 cache
    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
	cache
    - 32 Kbyte of shared M3 memory
    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
      Processing (MAPLE-B2P)
    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
      ECC), up to 1333 MHz data rate
    - Dedicated security engine featuring trusted boot
    - Two DMA controllers
         - OCNDMA with four bidirectional channels
         - SysDMA with sixteen bidirectional channels
    - Interfaces
        - Four-lane SerDes PHY
	    - PCI Express controller complies with the PEX Specification-Rev 2.0
        - Two Common Public Radio Interface (CPRI) controller lanes
	    - High-speed USB 2.0 host and device controller with ULPI interface
        - Enhanced secure digital (SD/MMC) host controller (eSDHC)
	    - Antenna interface controller (AIC), supporting four industry
		standard JESD207/four custom ADI RF interfaces
       - ADI lanes support both full duplex FDD support & half duplex TDD
       - Universal Subscriber Identity Module (USIM) interface that
	   facilitates communication to SIM cards or Eurochip pre-paid phone
	   cards
       - Two DUART, two eSPI, and two I2C controllers
       - Integrated Flash memory controller (IFC)
       - GPIO
     - Sixteen 32-bit timers

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/Makefile         |  2 +
 arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 96 +++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc8xxx/cpu.c            |  2 +
 arch/powerpc/include/asm/config_mpc85xx.h | 15 +++++
 arch/powerpc/include/asm/immap_85xx.h     | 25 +++++++-
 arch/powerpc/include/asm/processor.h      |  2 +
 6 files changed, 140 insertions(+), 2 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 95994d3..6776c85 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -86,6 +86,7 @@ COBJS-$(CONFIG_PPC_T4240)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4420)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4860)	+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
+COBJS-$(CONFIG_BSC9132)		+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
@@ -138,6 +139,7 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
 COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
+COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
 
 COBJS-y	+= cpu.o
 COBJS-y	+= cpu_init.o
diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
new file mode 100644
index 0000000..300a4db
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES		4
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+	 [0] = {NONE, NONE, NONE, NONE},
+	 [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	 [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	 [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	 [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+	[12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[22] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[23] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[24] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[25] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[26] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+	[33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+	[44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+	[45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+	[46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+	[47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+	return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	int lane;
+
+	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
+		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+		return;
+	}
+
+	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+		serdes1_prtcl_map |= (1 << lane_prtcl);
+	}
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index e8613be..ab454f5 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -86,6 +86,8 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(B4220, B4220, 0),
 	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
+	CPU_TYPE_ENTRY(BSC9132, 9132, 2),
+	CPU_TYPE_ENTRY(BSC9232, 9232, 2),
 #elif defined(CONFIG_MPC86xx)
 	CPU_TYPE_ENTRY(8610, 8610, 1),
 	CPU_TYPE_ENTRY(8641, 8641, 2),
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f957fa3..7943fa4 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -493,6 +493,21 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+#elif defined(CONFIG_BSC9132)
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+
 #elif defined(CONFIG_PPC_T4240)
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 6a818c4..67b1a44 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2150,7 +2150,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
 #else
-#ifdef CONFIG_BSC9131
+#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
 #else
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003e00
@@ -2164,6 +2164,11 @@ typedef struct ccsr_gur {
 	u32	porbmsr;	/* POR boot mode status */
 #define MPC85xx_PORBMSR_HA		0x00070000
 #define MPC85xx_PORBMSR_HA_SHIFT	16
+#define MPC85XX_PORBMSR_ROMLOC_SHIFT	24
+#define PORBMSR_ROMLOC_SPI	0x6
+#define PORBMSR_ROMLOC_SDHC	0x7
+#define PORBMSR_ROMLOC_NAND_2K	0x9
+#define PORBMSR_ROMLOC_NOR	0xf
 	u32	porimpscr;	/* POR I/O impedance status & control */
 	u32	pordevsr;	/* POR I/O device status regsiter */
 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
@@ -2188,6 +2193,9 @@ typedef struct ccsr_gur {
 #if defined(CONFIG_P1010)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00600000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
+#elif defined(CONFIG_BSC9132)
+#define MPC85xx_PORDEVSR_IO_SEL		0x00FE0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	17
 #else
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19
@@ -2345,6 +2353,10 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen	0x00000002
 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76		0x00000003
 #endif
+#ifdef CONFIG_BSC9132
+#define MPC85xx_PMUXCR0_SIM_SEL_MASK	0x0003b000
+#define MPC85xx_PMUXCR0_SIM_SEL		0x00014000
+#endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR2_UART_GPIO		0x40000000
@@ -2375,6 +2387,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_ETSECUSB_MASK	0x001f8000
 #define MPC85xx_PMUXCR2_USB		0x00150000
 #endif
+#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #if defined(CONFIG_BSC9131)
 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD		0X40000000
 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS		0X80000000
@@ -2418,8 +2431,9 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53			0x00000004
 #define MPC85xx_PMUXCR2_ANT3_DO_TDM			0x00000001
 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49		0x00000002
+#endif
 	u32	pmuxcr3;
-
+#if defined(CONFIG_BSC9131)
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM			0x40000000
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51		0x80000000
 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B	0x10000000
@@ -2434,6 +2448,13 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94			0x00040000
 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD			0x00010000
 #define MPC85xx_PMUXCR3_ANT2_GPO89			0x00030000
+#endif
+#ifdef CONFIG_BSC9132
+#define MPC85xx_PMUXCR3_USB_SEL_MASK	0x0000ff00
+#define MPC85xx_PMUXCR3_UART2_SEL	0x00005000
+#define MPC85xx_PMUXCR3_UART3_SEL_MASK	0xc0000000
+#define MPC85xx_PMUXCR3_UART3_SEL	0x40000000
+#endif
 	u32 pmuxcr4;
 #else
 	u8	res6[8];
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 19fe250..8c91f08 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1113,6 +1113,8 @@
 
 #define SVR_9130	0x860001
 #define SVR_9131	0x860000
+#define SVR_9132	0x861000
+#define SVR_9232	0x861400
 
 #define SVR_Unknown	0xFFFFFF
 
-- 
cgit v1.1


From 31d084ddda7739762dd476b4fbb8a2d4b4ca1b25 Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Fri, 18 Jan 2013 15:45:58 +0000
Subject: powerpc/mpc85xx: add support for MMUv2 page sizes

e6500 implements MMUv2 and supports power-of-2 page sizes rather than
power-of-4.  Add support for such pages.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/start.S |  2 +-
 arch/powerpc/cpu/mpc85xx/tlb.c   | 19 +++++++++++----
 arch/powerpc/include/asm/mmu.h   | 52 ++++++++++++++++++++++++++--------------
 3 files changed, 49 insertions(+), 24 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index bb0dc1a..fb67469 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -449,7 +449,7 @@ nexti:	mflr	r1		/* R1 = our PC */
 
 	/* Set the size of the TLB to 4KB */
 	mfspr	r3, MAS1
-	li	r2, 0xF00
+	li	r2, 0xF80
 	andc	r3, r3, r2	/* Clear the TSIZE bits */
 	ori	r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
 	oris	r3, r3, MAS1_IPROT@h
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index f44fadc..23d3357 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -66,7 +66,7 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 	_mas1 = mfspr(MAS1);
 
 	*valid = (_mas1 & MAS1_VALID);
-	*tsize = (_mas1 >> 8) & 0xf;
+	*tsize = (_mas1 >> 7) & 0x1f;
 	*epn = mfspr(MAS2) & MAS2_EPN;
 	*rpn = mfspr(MAS3) & MAS3_RPN;
 #ifdef CONFIG_ENABLE_36BIT_PHYS
@@ -156,6 +156,13 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
 	if (tlb == 1)
 		use_tlb_cam(esel);
 
+	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
+	    tsize & 1) {
+		printf("%s: bad tsize %d on entry %d at 0x%08x\n",
+			__func__, tsize, tlb, epn);
+		return;
+	}
+
 	_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
 	_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
 	_mas2 = FSL_BOOKE_MAS2(epn, wimge);
@@ -251,7 +258,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 	unsigned int tlb_size;
 	unsigned int wimge = MAS2_M;
 	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
-	unsigned int max_cam;
+	unsigned int max_cam, tsize_mask;
 	u64 size, memsize = (u64)memsize_in_meg << 20;
 
 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
@@ -261,15 +268,17 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
 		/* Convert (4^max) kB to (2^max) bytes */
 		max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+		tsize_mask = ~1U;
 	} else {
 		/* Convert (2^max) kB to (2^max) bytes */
 		max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+		tsize_mask = ~0U;
 	}
 
 	for (i = 0; size && i < 8; i++) {
 		int ram_tlb_index = find_free_tlbcam();
-		u32 camsize = __ilog2_u64(size) & ~1U;
-		u32 align = __ilog2(ram_tlb_address) & ~1U;
+		u32 camsize = __ilog2_u64(size) & tsize_mask;
+		u32 align = __ilog2(ram_tlb_address) & tsize_mask;
 
 		if (ram_tlb_index == -1)
 			break;
@@ -281,7 +290,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 		if (camsize > max_cam)
 			camsize = max_cam;
 
-		tlb_size = (camsize - 10) / 2;
+		tlb_size = camsize - 10;
 
 		set_tlb(1, ram_tlb_address, p_addr,
 			MAS3_SX|MAS3_SW|MAS3_SR, wimge,
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 2e0e292..b700a3a 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -401,8 +401,8 @@ extern void print_bats(void);
 #define MAS1_IPROT	0x40000000
 #define MAS1_TID(x)	(((x) << 16) & 0x3FFF0000)
 #define MAS1_TS		0x00001000
-#define MAS1_TSIZE(x)	(((x) << 8) & 0x00000F00)
-#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10))
+#define MAS1_TSIZE(x)	(((x) << 7) & 0x00000F80)
+#define TSIZE_TO_BYTES(x) (1ULL << ((x) + 10))
 
 #define MAS2_EPN	0xFFFFF000
 #define MAS2_X0		0x00000040
@@ -458,22 +458,38 @@ extern void print_bats(void);
 #define FSL_BOOKE_MAS7(rpn) \
 		(((u64)(rpn)) >> 32)
 
-#define BOOKE_PAGESZ_1K         0
-#define BOOKE_PAGESZ_4K         1
-#define BOOKE_PAGESZ_16K        2
-#define BOOKE_PAGESZ_64K        3
-#define BOOKE_PAGESZ_256K       4
-#define BOOKE_PAGESZ_1M         5
-#define BOOKE_PAGESZ_4M         6
-#define BOOKE_PAGESZ_16M        7
-#define BOOKE_PAGESZ_64M        8
-#define BOOKE_PAGESZ_256M       9
-#define BOOKE_PAGESZ_1G		10
-#define BOOKE_PAGESZ_4G		11
-#define BOOKE_PAGESZ_16GB	12
-#define BOOKE_PAGESZ_64GB	13
-#define BOOKE_PAGESZ_256GB	14
-#define BOOKE_PAGESZ_1TB	15
+#define BOOKE_PAGESZ_1K		0
+#define BOOKE_PAGESZ_2K		1
+#define BOOKE_PAGESZ_4K		2
+#define BOOKE_PAGESZ_8K		3
+#define BOOKE_PAGESZ_16K	4
+#define BOOKE_PAGESZ_32K	5
+#define BOOKE_PAGESZ_64K	6
+#define BOOKE_PAGESZ_128K	7
+#define BOOKE_PAGESZ_256K	8
+#define BOOKE_PAGESZ_512K	9
+#define BOOKE_PAGESZ_1M		10
+#define BOOKE_PAGESZ_2M		11
+#define BOOKE_PAGESZ_4M		12
+#define BOOKE_PAGESZ_8M		13
+#define BOOKE_PAGESZ_16M	14
+#define BOOKE_PAGESZ_32M	15
+#define BOOKE_PAGESZ_64M	16
+#define BOOKE_PAGESZ_128M	17
+#define BOOKE_PAGESZ_256M	18
+#define BOOKE_PAGESZ_512M	19
+#define BOOKE_PAGESZ_1G		20
+#define BOOKE_PAGESZ_2G		21
+#define BOOKE_PAGESZ_4G		22
+#define BOOKE_PAGESZ_8G		23
+#define BOOKE_PAGESZ_16GB	24
+#define BOOKE_PAGESZ_32GB	25
+#define BOOKE_PAGESZ_64GB	26
+#define BOOKE_PAGESZ_128GB	27
+#define BOOKE_PAGESZ_256GB	28
+#define BOOKE_PAGESZ_512GB	29
+#define BOOKE_PAGESZ_1TB	30
+#define BOOKE_PAGESZ_2TB	31
 
 #define TLBIVAX_ALL		4
 #define TLBIVAX_TLB0		0
-- 
cgit v1.1


From 5b93394318c04791c9b4edda7ff4af140427ed8a Mon Sep 17 00:00:00 2001
From: Anatolij Gustschin <agust@denx.de>
Date: Mon, 21 Jan 2013 23:50:27 +0000
Subject: mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE

Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in
the board config file doesn't work and memory is always initialized
to the value 0xdeadbeef. Only use this default value if a board doesn't
define CONFIG_MEM_INIT_VALUE.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 8016bcd..26c42f7 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1190,7 +1190,11 @@ static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
 {
 	unsigned int init_value;	/* Initialization value */
 
+#ifdef CONFIG_MEM_INIT_VALUE
+	init_value = CONFIG_MEM_INIT_VALUE;
+#else
 	init_value = 0xDEADBEEF;
+#endif
 	ddr->ddr_data_init = init_value;
 }
 
-- 
cgit v1.1


From 5e95e2d84bdab9fef309392e51fd4b68a6a28949 Mon Sep 17 00:00:00 2001
From: Vakul Garg <vakul@freescale.com>
Date: Wed, 23 Jan 2013 22:52:31 +0000
Subject: powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node
 'crypto'

If property 'fsl,sec-era' is already present, it is updated.
This property is required so that applications can ascertain which
descriptor commands are supported on a particular CAAM version.

Signed-off-by: Vakul Garg <vakul@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/fdt.c        |  8 ++++
 arch/powerpc/cpu/mpc8xxx/fdt.c        | 78 ++++++++++++++++++++++++++++++++++-
 arch/powerpc/include/asm/immap_85xx.h |  7 ++++
 3 files changed, 92 insertions(+), 1 deletion(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 16d7f6a..3a268aa 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -607,6 +607,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	/* delete crypto node if not on an E-processor */
 	if (!IS_E_PROCESSOR(get_svr()))
 		fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+	else {
+		ccsr_sec_t __iomem *sec;
+
+		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+		fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms));
+	}
+#endif
 
 	fdt_fixup_ethernet(blob);
 
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 1986fea..2847094 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -297,10 +297,86 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
 		       fdt_strerror(err));
 }
 #elif CONFIG_SYS_FSL_SEC_COMPAT >= 4  /* SEC4 */
+static u8 caam_get_era(void)
+{
+	static const struct {
+		u16 ip_id;
+		u8 maj_rev;
+		u8 era;
+	} caam_eras[] = {
+		{0x0A10, 1, 1},
+		{0x0A10, 2, 2},
+		{0x0A12, 1, 3},
+		{0x0A14, 1, 3},
+		{0x0A14, 2, 4},
+		{0x0A16, 1, 4},
+		{0x0A10, 3, 4},
+		{0x0A11, 1, 4},
+		{0x0A18, 1, 4},
+		{0x0A11, 2, 5},
+		{0x0A12, 2, 5},
+		{0x0A13, 1, 5},
+		{0x0A1C, 1, 5}
+	};
+
+	ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	u32 secvid_ms = in_be32(&sec->secvid_ms);
+	u32 ccbvid = in_be32(&sec->ccbvid);
+	u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
+				SEC_SECVID_MS_IPID_SHIFT;
+	u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
+				SEC_SECVID_MS_MAJ_REV_SHIFT;
+	u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT;
+
+	int i;
+
+	if (era)	/* This is '0' prior to CAAM ERA-6 */
+		return era;
+
+	for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
+		if (caam_eras[i].ip_id == ip_id &&
+		    caam_eras[i].maj_rev == maj_rev)
+			return caam_eras[i].era;
+
+	return 0;
+}
+
+static void fdt_fixup_crypto_era(void *blob, u32 era)
+{
+	int err;
+	int crypto_node;
+
+	crypto_node = fdt_path_offset(blob, "crypto");
+	if (crypto_node < 0) {
+		printf("WARNING: Missing crypto node\n");
+		return;
+	}
+
+	err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
+			  sizeof(era));
+	if (err < 0) {
+		printf("ERROR: could not set fsl,sec-era property: %s\n",
+		       fdt_strerror(err));
+	}
+}
+
 void fdt_fixup_crypto_node(void *blob, int sec_rev)
 {
-	if (!sec_rev)
+	u8 era;
+
+	if (!sec_rev) {
 		fdt_del_node_and_alias(blob, "crypto");
+		return;
+	}
+
+	/* Add SEC ERA information in compatible */
+	era = caam_get_era();
+	if (era) {
+		fdt_fixup_crypto_era(blob, era);
+	} else {
+		printf("WARNING: Unable to get ERA for CAAM rev: %d\n",
+			sec_rev);
+	}
 }
 #endif
 
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 67b1a44..4eb3f79 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2748,6 +2748,12 @@ typedef struct ccsr_sec {
 #define SEC_CHANUM_MS_JRNUM_SHIFT	28
 #define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
 #define SEC_CHANUM_MS_DECONUM_SHIFT	24
+#define SEC_SECVID_MS_IPID_MASK	0xffff0000
+#define SEC_SECVID_MS_IPID_SHIFT	16
+#define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
+#define SEC_SECVID_MS_MAJ_REV_SHIFT	8
+#define SEC_CCBVID_ERA_MASK		0xff000000
+#define SEC_CCBVID_ERA_SHIFT		24
 #endif
 
 typedef struct ccsr_qman {
@@ -2983,6 +2989,7 @@ struct ccsr_pman {
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SNVS_OFFSET			0xE6000
-- 
cgit v1.1


From 72bd83cd0a12f411983d33b5f24adc16b9b77313 Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Date: Wed, 23 Jan 2013 19:56:23 +0000
Subject: powerpc/t4240: Adding workaround errata A-005871

When CoreNet Fabric (CCF) internal resources are consumed by the cores,
inbound SRIO messaging traffic through RMan can put the device into a
deadlock condition.

This errata workaround forces internal resources to be reserved for
upstream transactions. This ensures resources exist on the device for
upstream transactions and removes the deadlock condition.

The Workaround is for the T4240 silicon rev 1.0.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |  4 ++++
 arch/powerpc/cpu/mpc85xx/cpu_init.c       | 14 ++++++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h |  1 +
 3 files changed, 19 insertions(+)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index e5ecf5d..5d72f4c 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -240,6 +240,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
 	puts("Work-around for Erratum A004934 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
+	if (IS_SVR_REV(svr, 1, 0))
+		puts("Work-around for Erratum A005871 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
 	/* This work-around is implemented in PBI, so just check for it */
 	check_erratum_a4849(svr);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index cc09300..de9d916 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -548,6 +548,20 @@ skip_l2:
 	/* needs to be in ram since code uses global static vars */
 	fsl_serdes_init();
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
+	if (IS_SVR_REV(svr, 1, 0)) {
+		int i;
+		__be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
+
+		for (i = 0; i < 12; i++) {
+			p += i + (i > 5 ? 11 : 0);
+			out_be32(p, 0x2);
+		}
+		p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
+		out_be32(p, 0x34);
+	}
+#endif
+
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
 #ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7943fa4..d57c178 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -538,6 +538,7 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
 #elif defined(CONFIG_PPC_B4420)
-- 
cgit v1.1


From 5cb48582ac05931c66b00b46c60d3ee8c6fc7950 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:30 +0000
Subject: Add architecture-specific global data

We plan to move architecture-specific data into a separate structure so
that we can make the rest of it common.

As a first step, create struct arch_global_data to hold these fields.
Initially it is empty.

This patch applies to all archs at once. I can split it if this is really
a pain.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/include/asm/global_data.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index cb3a80b..df621da 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -27,6 +27,10 @@
 #include "config.h"
 #include "asm/types.h"
 
+/* Architecture-specific global data */
+struct arch_global_data {
+};
+
 /*
  * The following data structure is placed in some memory wich is
  * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
@@ -184,6 +188,7 @@ typedef	struct	global_data {
 #endif
 	void		**jt;		/* jump table */
 	char		env_buf[32];	/* buffer for getenv() before reloc. */
+	struct arch_global_data arch;	/* architecture-specific data */
 } gd_t;
 
 #include <asm-generic/global_data_flags.h>
-- 
cgit v1.1


From 1206c18403ff25814673a4dbfa071ae06bbefaef Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:44 +0000
Subject: ppc: Move brg_clk to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc8260/commproc.c    |  2 +-
 arch/powerpc/cpu/mpc8260/i2c.c         |  2 +-
 arch/powerpc/cpu/mpc8260/speed.c       |  4 ++--
 arch/powerpc/cpu/mpc83xx/speed.c       |  5 +++--
 arch/powerpc/cpu/mpc85xx/commproc.c    |  2 +-
 arch/powerpc/cpu/mpc85xx/speed.c       |  4 ++--
 arch/powerpc/cpu/mpc8xx/fdt.c          |  2 +-
 arch/powerpc/cpu/mpc8xx/speed.c        |  2 +-
 arch/powerpc/include/asm/global_data.h | 14 +++++++++-----
 arch/powerpc/lib/board.c               |  2 +-
 10 files changed, 22 insertions(+), 17 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c
index 082957e..e5bfed1 100644
--- a/arch/powerpc/cpu/mpc8260/commproc.c
+++ b/arch/powerpc/cpu/mpc8260/commproc.c
@@ -101,7 +101,7 @@ m8260_cpm_hostalloc(uint size, uint align)
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers).  Documentation uses 1-based numbering.
  */
-#define BRG_INT_CLK	gd->brg_clk
+#define BRG_INT_CLK	gd->arch.brg_clk
 #define BRG_UART_CLK	(BRG_INT_CLK / 16)
 
 /* This function is used by UARTs, or anything else that uses a 16x
diff --git a/arch/powerpc/cpu/mpc8260/i2c.c b/arch/powerpc/cpu/mpc8260/i2c.c
index 7382cba..b720b1f 100644
--- a/arch/powerpc/cpu/mpc8260/i2c.c
+++ b/arch/powerpc/cpu/mpc8260/i2c.c
@@ -259,7 +259,7 @@ void i2c_init(int speed, int slaveadd)
 	 * divide BRGCLK by 1)
 	 */
 	debug("[I2C] Setting rate...\n");
-	i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED);
+	i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED);
 
 	/* Set I2C controller in master mode */
 	i2c->i2c_i2com = 0x01;
diff --git a/arch/powerpc/cpu/mpc8260/speed.c b/arch/powerpc/cpu/mpc8260/speed.c
index bb50dee..4ad1ec2 100644
--- a/arch/powerpc/cpu/mpc8260/speed.c
+++ b/arch/powerpc/cpu/mpc8260/speed.c
@@ -145,7 +145,7 @@ int get_clocks (void)
 	gd->cpm_clk = gd->vco_out / 2;
 	gd->bus_clk = clkin;
 	gd->scc_clk = gd->vco_out / 4;
-	gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+	gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
 
 	if (cp->b2c_mult > 0) {
 		gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
@@ -231,7 +231,7 @@ int prt_8260_clks (void)
 			plldf, pllmf, pcidf);
 
 	printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
-			gd->vco_out, gd->scc_clk, gd->brg_clk);
+			gd->vco_out, gd->scc_clk, gd->arch.brg_clk);
 
 	printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
 			gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index b8c05d1..21e8b0a 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -496,7 +496,7 @@ int get_clocks(void)
 #endif
 #if defined(CONFIG_QE)
 	gd->qe_clk = qe_clk;
-	gd->brg_clk = brg_clk;
+	gd->arch.brg_clk = brg_clk;
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC837x)
@@ -540,7 +540,8 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
 #if defined(CONFIG_QE)
 	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
-	printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
+	printf("  BRG:                 %-4s MHz\n",
+	       strmhz(buf, gd->arch.brg_clk));
 #endif
 	printf("  Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
 	printf("  Local Bus:           %-4s MHz\n", strmhz(buf, gd->lclk_clk));
diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c b/arch/powerpc/cpu/mpc85xx/commproc.c
index 292b723..7f10476 100644
--- a/arch/powerpc/cpu/mpc85xx/commproc.c
+++ b/arch/powerpc/cpu/mpc85xx/commproc.c
@@ -110,7 +110,7 @@ m8560_cpm_hostalloc(uint size, uint align)
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers).  Documentation uses 1-based numbering.
  */
-#define BRG_INT_CLK	gd->brg_clk
+#define BRG_INT_CLK	gd->arch.brg_clk
 #define BRG_UART_CLK	((BRG_INT_CLK + 15) / 16)
 
 /* This function is used by UARTS, or anything else that uses a 16x
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 801ee07..8a581ef 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -395,7 +395,7 @@ int get_clocks (void)
 
 #ifdef CONFIG_QE
 	gd->qe_clk = sys_info.freqQE;
-	gd->brg_clk = gd->qe_clk / 2;
+	gd->arch.brg_clk = gd->qe_clk / 2;
 #endif
 	/*
 	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
@@ -438,7 +438,7 @@ int get_clocks (void)
 	gd->vco_out = 2*sys_info.freqSystemBus;
 	gd->cpm_clk = gd->vco_out / 2;
 	gd->scc_clk = gd->vco_out / 4;
-	gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+	gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
 #endif
 
 	if(gd->cpu_clk != 0) return (0);
diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c
index 7130983..7edd7e4 100644
--- a/arch/powerpc/cpu/mpc8xx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xx/fdt.c
@@ -37,7 +37,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"clock-frequency", bd->bi_intfreq, 1);
 	do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
-		gd->brg_clk, 1);
+		gd->arch.brg_clk, 1);
 
 	/* Fixup ethernet MAC addresses */
 	fdt_fixup_ethernet(blob);
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index 6e13e5d..091b49f 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -192,7 +192,7 @@ void get_brgclk(uint sccr)
 			divider = 64;
 			break;
 	}
-	gd->brg_clk = gd->cpu_clk/divider;
+	gd->arch.brg_clk = gd->cpu_clk/divider;
 }
 
 #if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index df621da..ac348c6 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -29,6 +29,15 @@
 
 /* Architecture-specific global data */
 struct arch_global_data {
+#if defined(CONFIG_8xx)
+	unsigned long brg_clk;
+#endif
+#if defined(CONFIG_CPM2)
+	unsigned long brg_clk;
+#endif
+#if defined(CONFIG_QE)
+	u32 brg_clk;
+#endif
 };
 
 /*
@@ -45,15 +54,11 @@ typedef	struct	global_data {
 	unsigned int	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz! */
 	unsigned long	bus_clk;
-#if defined(CONFIG_8xx)
-	unsigned long	brg_clk;
-#endif
 #if defined(CONFIG_CPM2)
 	/* There are many clocks on the MPC8260 - see page 9-5 */
 	unsigned long	vco_out;
 	unsigned long	cpm_clk;
 	unsigned long	scc_clk;
-	unsigned long	brg_clk;
 #ifdef CONFIG_PCI
 	unsigned long	pci_clk;
 #endif
@@ -106,7 +111,6 @@ typedef	struct	global_data {
 #endif
 #if defined(CONFIG_QE)
 	u32 qe_clk;
-	u32 brg_clk;
 	uint mp_alloc_base;
 	uint mp_alloc_top;
 #endif /* CONFIG_QE */
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 6a7bf4b..b1069a6 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -581,7 +581,7 @@ void board_init_f(ulong bootflag)
 	bd->bi_busfreq = gd->bus_clk;	/* Bus Freq,      in Hz */
 #if defined(CONFIG_CPM2)
 	bd->bi_cpmfreq = gd->cpm_clk;
-	bd->bi_brgfreq = gd->brg_clk;
+	bd->bi_brgfreq = gd->arch.brg_clk;
 	bd->bi_sccfreq = gd->scc_clk;
 	bd->bi_vco = gd->vco_out;
 #endif /* CONFIG_CPM2 */
-- 
cgit v1.1


From 9fb23624a644d9a09f85fc1230b34829005c0021 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:45 +0000
Subject: ppc: Remove extra pci_clk fields from global_data

PPC has several of these fields, selected by chip type, although only one
is ever compiled in.

Instead, use a single field. It would be nice if this could be selected
by CONFIG_PCI, but some chips (e.g. mpc5xxx) use pci_clk even when
CONFIG_PCI is not enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/include/asm/global_data.h | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index ac348c6..8e3a726 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -54,14 +54,13 @@ typedef	struct	global_data {
 	unsigned int	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz! */
 	unsigned long	bus_clk;
+	/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
+	unsigned long	pci_clk;
 #if defined(CONFIG_CPM2)
 	/* There are many clocks on the MPC8260 - see page 9-5 */
 	unsigned long	vco_out;
 	unsigned long	cpm_clk;
 	unsigned long	scc_clk;
-#ifdef CONFIG_PCI
-	unsigned long	pci_clk;
-#endif
 #endif
 	unsigned long   mem_clk;
 #if defined(CONFIG_MPC83xx)
@@ -85,7 +84,6 @@ typedef	struct	global_data {
 	u32 enc_clk;
 	u32 lbiu_clk;
 	u32 lclk_clk;
-	u32 pci_clk;
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC837x)
 	u32 pciexp1_clk;
@@ -122,17 +120,14 @@ typedef	struct	global_data {
 #endif
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	ipb_clk;
-	unsigned long	pci_clk;
 #endif
 #if defined(CONFIG_MPC512X)
 	u32 ips_clk;
 	u32 csb_clk;
-	u32 pci_clk;
 #endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC8220)
 	unsigned long   bExtUart;
 	unsigned long   inp_clk;
-	unsigned long   pci_clk;
 	unsigned long   vco_clk;
 	unsigned long   pev_clk;
 	unsigned long   flb_clk;
-- 
cgit v1.1


From 748cd0591a9fe9eb23f20748bcb23035cd5ff517 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:46 +0000
Subject: ppc: Move clock fields to arch_global_data

Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy
up. Leave pci_clk on its own since this should really depend only on
CONFIG_PCI and not any particular chip type.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc8260/speed.c       | 16 ++++++++--------
 arch/powerpc/cpu/mpc85xx/speed.c       |  8 ++++----
 arch/powerpc/include/asm/global_data.h |  4 ++++
 arch/powerpc/lib/board.c               |  6 +++---
 4 files changed, 19 insertions(+), 15 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8260/speed.c b/arch/powerpc/cpu/mpc8260/speed.c
index 4ad1ec2..7841e8a 100644
--- a/arch/powerpc/cpu/mpc8260/speed.c
+++ b/arch/powerpc/cpu/mpc8260/speed.c
@@ -135,17 +135,17 @@ int get_clocks (void)
 	    (get_pvr () == PVR_8260_HIP7R1) ||
 	    (get_pvr () == PVR_8260_HIP7RA)) {
 		pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
-		gd->vco_out = clkin * (pllmf + 1);
+		gd->arch.vco_out = clkin * (pllmf + 1);
 	} else {                        /* HiP3, HiP4 */
 		pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
 		plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
-		gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
+		gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
 	}
 
-	gd->cpm_clk = gd->vco_out / 2;
+	gd->arch.cpm_clk = gd->arch.vco_out / 2;
 	gd->bus_clk = clkin;
-	gd->scc_clk = gd->vco_out / 4;
-	gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+	gd->arch.scc_clk = gd->arch.vco_out / 4;
+	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
 
 	if (cp->b2c_mult > 0) {
 		gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
@@ -173,7 +173,7 @@ int get_clocks (void)
 			pci_div = pcidf + 1;
 		}
 
-		gd->pci_clk = (gd->cpm_clk * 2) / pci_div;
+		gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div;
 	}
 #endif
 
@@ -231,10 +231,10 @@ int prt_8260_clks (void)
 			plldf, pllmf, pcidf);
 
 	printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
-			gd->vco_out, gd->scc_clk, gd->arch.brg_clk);
+			gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk);
 
 	printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
-			gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
+			gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk);
 #ifdef CONFIG_PCI
 	printf (" - pci_clk %10ld\n", gd->pci_clk);
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 8a581ef..c4ca481 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -435,10 +435,10 @@ int get_clocks (void)
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
 #if defined(CONFIG_CPM2)
-	gd->vco_out = 2*sys_info.freqSystemBus;
-	gd->cpm_clk = gd->vco_out / 2;
-	gd->scc_clk = gd->vco_out / 4;
-	gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+	gd->arch.vco_out = 2*sys_info.freqSystemBus;
+	gd->arch.cpm_clk = gd->arch.vco_out / 2;
+	gd->arch.scc_clk = gd->arch.vco_out / 4;
+	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
 #endif
 
 	if(gd->cpu_clk != 0) return (0);
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 8e3a726..7d0115d 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -33,6 +33,10 @@ struct arch_global_data {
 	unsigned long brg_clk;
 #endif
 #if defined(CONFIG_CPM2)
+	/* There are many clocks on the MPC8260 - see page 9-5 */
+	unsigned long vco_out;
+	unsigned long cpm_clk;
+	unsigned long scc_clk;
 	unsigned long brg_clk;
 #endif
 #if defined(CONFIG_QE)
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index b1069a6..988039f 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -580,10 +580,10 @@ void board_init_f(ulong bootflag)
 	bd->bi_intfreq = gd->cpu_clk;	/* Internal Freq, in Hz */
 	bd->bi_busfreq = gd->bus_clk;	/* Bus Freq,      in Hz */
 #if defined(CONFIG_CPM2)
-	bd->bi_cpmfreq = gd->cpm_clk;
+	bd->bi_cpmfreq = gd->arch.cpm_clk;
 	bd->bi_brgfreq = gd->arch.brg_clk;
-	bd->bi_sccfreq = gd->scc_clk;
-	bd->bi_vco = gd->vco_out;
+	bd->bi_sccfreq = gd->arch.scc_clk;
+	bd->bi_vco = gd->arch.vco_out;
 #endif /* CONFIG_CPM2 */
 #if defined(CONFIG_MPC512X)
 	bd->bi_ipsfreq = gd->ips_clk;
-- 
cgit v1.1


From c6731fe22ab1cc2f5c2b8be9b1db276d777f12c3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:47 +0000
Subject: ppc: Move mpc83xx clock fields to arch_global_data

Move al mpc83xx fields into arch_global_data and tidy up. Also indent
the nested #ifdef for clarity.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc83xx/cpu.c         |  2 +-
 arch/powerpc/cpu/mpc83xx/fdt.c         |  2 +-
 arch/powerpc/cpu/mpc83xx/pcie.c        |  4 +-
 arch/powerpc/cpu/mpc83xx/speed.c       | 81 ++++++++++++++++++++--------------
 arch/powerpc/include/asm/global_data.h | 73 ++++++++++++++----------------
 5 files changed, 86 insertions(+), 76 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index e64b0c3..cc20234 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -122,7 +122,7 @@ int checkcpu(void)
 
 	printf(" at %s MHz, ", strmhz(buf, clock));
 
-	printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
+	printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
 
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index 1f54781..fe553a7 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -118,7 +118,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"bus-frequency", bd->bi_busfreq, 1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-		"clock-frequency", gd->core_clk, 1);
+		"clock-frequency", gd->arch.core_clk, 1);
 	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 		"bus-frequency", bd->bi_busfreq, 1);
 	do_fixup_by_compat_u32(blob, "fsl,soc",
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 52d4461..609b133 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -286,8 +286,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
 	get_clocks();
 	/* Configure the PCIE controller core clock ratio */
 	out_le32(hose_cfg_base + PEX_GCLK_RATIO,
-		(((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
-		/ 333);
+		(((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
+			/ 1000000) * 16) / 333);
 	udelay(1000000);
 
 	/* Do Type 1 bridge configuration */
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 21e8b0a..7f98ee8 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -462,37 +462,37 @@ int get_clocks(void)
 	brg_clk = qe_clk / 2;
 #endif
 
-	gd->csb_clk = csb_clk;
+	gd->arch.csb_clk = csb_clk;
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
-	gd->tsec1_clk = tsec1_clk;
-	gd->tsec2_clk = tsec2_clk;
-	gd->usbdr_clk = usbdr_clk;
+	gd->arch.tsec1_clk = tsec1_clk;
+	gd->arch.tsec2_clk = tsec2_clk;
+	gd->arch.usbdr_clk = usbdr_clk;
 #elif defined(CONFIG_MPC8309)
-	gd->usbdr_clk = usbdr_clk;
+	gd->arch.usbdr_clk = usbdr_clk;
 #endif
 #if defined(CONFIG_MPC834x)
-	gd->usbmph_clk = usbmph_clk;
+	gd->arch.usbmph_clk = usbmph_clk;
 #endif
 #if defined(CONFIG_MPC8315)
-	gd->tdm_clk = tdm_clk;
+	gd->arch.tdm_clk = tdm_clk;
 #endif
 #if defined(CONFIG_FSL_ESDHC)
 	gd->sdhc_clk = sdhc_clk;
 #endif
-	gd->core_clk = core_clk;
+	gd->arch.core_clk = core_clk;
 	gd->i2c1_clk = i2c1_clk;
 #if !defined(CONFIG_MPC832x)
 	gd->i2c2_clk = i2c2_clk;
 #endif
 #if !defined(CONFIG_MPC8309)
-	gd->enc_clk = enc_clk;
+	gd->arch.enc_clk = enc_clk;
 #endif
-	gd->lbiu_clk = lbiu_clk;
-	gd->lclk_clk = lclk_clk;
+	gd->arch.lbiu_clk = lbiu_clk;
+	gd->arch.lclk_clk = lclk_clk;
 	gd->mem_clk = mem_clk;
 #if defined(CONFIG_MPC8360)
-	gd->mem_sec_clk = mem_sec_clk;
+	gd->arch.mem_sec_clk = mem_sec_clk;
 #endif
 #if defined(CONFIG_QE)
 	gd->qe_clk = qe_clk;
@@ -500,15 +500,15 @@ int get_clocks(void)
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC837x)
-	gd->pciexp1_clk = pciexp1_clk;
-	gd->pciexp2_clk = pciexp2_clk;
+	gd->arch.pciexp1_clk = pciexp1_clk;
+	gd->arch.pciexp2_clk = pciexp2_clk;
 #endif
 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
-	gd->sata_clk = sata_clk;
+	gd->arch.sata_clk = sata_clk;
 #endif
 	gd->pci_clk = pci_sync_in;
-	gd->cpu_clk = gd->core_clk;
-	gd->bus_clk = gd->csb_clk;
+	gd->cpu_clk = gd->arch.core_clk;
+	gd->bus_clk = gd->arch.csb_clk;
 	return 0;
 
 }
@@ -519,7 +519,7 @@ int get_clocks(void)
  *********************************************/
 ulong get_bus_freq(ulong dummy)
 {
-	return gd->csb_clk;
+	return gd->arch.csb_clk;
 }
 
 /********************************************
@@ -536,50 +536,65 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	char buf[32];
 
 	printf("Clock configuration:\n");
-	printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
-	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
+	printf("  Core:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.core_clk));
+	printf("  Coherent System Bus: %-4s MHz\n",
+	       strmhz(buf, gd->arch.csb_clk));
 #if defined(CONFIG_QE)
 	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
 	printf("  BRG:                 %-4s MHz\n",
 	       strmhz(buf, gd->arch.brg_clk));
 #endif
-	printf("  Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
-	printf("  Local Bus:           %-4s MHz\n", strmhz(buf, gd->lclk_clk));
+	printf("  Local Bus Controller:%-4s MHz\n",
+	       strmhz(buf, gd->arch.lbiu_clk));
+	printf("  Local Bus:           %-4s MHz\n",
+	       strmhz(buf, gd->arch.lclk_clk));
 	printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
 #if defined(CONFIG_MPC8360)
-	printf("  DDR Secondary:       %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
+	printf("  DDR Secondary:       %-4s MHz\n",
+	       strmhz(buf, gd->arch.mem_sec_clk));
 #endif
 #if !defined(CONFIG_MPC8309)
-	printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
+	printf("  SEC:                 %-4s MHz\n",
+	       strmhz(buf, gd->arch.enc_clk));
 #endif
 	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
 #if !defined(CONFIG_MPC832x)
 	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
 #endif
 #if defined(CONFIG_MPC8315)
-	printf("  TDM:                 %-4s MHz\n", strmhz(buf, gd->tdm_clk));
+	printf("  TDM:                 %-4s MHz\n",
+	       strmhz(buf, gd->arch.tdm_clk));
 #endif
 #if defined(CONFIG_FSL_ESDHC)
 	printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
-	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
-	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
-	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+	printf("  TSEC1:               %-4s MHz\n",
+	       strmhz(buf, gd->arch.tsec1_clk));
+	printf("  TSEC2:               %-4s MHz\n",
+	       strmhz(buf, gd->arch.tsec2_clk));
+	printf("  USB DR:              %-4s MHz\n",
+	       strmhz(buf, gd->arch.usbdr_clk));
 #elif defined(CONFIG_MPC8309)
-	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+	printf("  USB DR:              %-4s MHz\n",
+	       strmhz(buf, gd->arch.usbdr_clk));
 #endif
 #if defined(CONFIG_MPC834x)
-	printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
+	printf("  USB MPH:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.usbmph_clk));
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC837x)
-	printf("  PCIEXP1:             %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
-	printf("  PCIEXP2:             %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
+	printf("  PCIEXP1:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.pciexp1_clk));
+	printf("  PCIEXP2:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.pciexp2_clk));
 #endif
 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
-	printf("  SATA:                %-4s MHz\n", strmhz(buf, gd->sata_clk));
+	printf("  SATA:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.sata_clk));
 #endif
 	return 0;
 }
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 7d0115d..b7bb035 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -42,64 +42,59 @@ struct arch_global_data {
 #if defined(CONFIG_QE)
 	u32 brg_clk;
 #endif
-};
-
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned int	baudrate;
-	unsigned long	cpu_clk;	/* CPU clock in Hz! */
-	unsigned long	bus_clk;
-	/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
-	unsigned long	pci_clk;
-#if defined(CONFIG_CPM2)
-	/* There are many clocks on the MPC8260 - see page 9-5 */
-	unsigned long	vco_out;
-	unsigned long	cpm_clk;
-	unsigned long	scc_clk;
-#endif
-	unsigned long   mem_clk;
+	/* TODO: sjg@chromium.org: Should these be unslgned long? */
 #if defined(CONFIG_MPC83xx)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
-#elif defined(CONFIG_MPC8309)
+# elif defined(CONFIG_MPC8309)
 	u32 usbdr_clk;
-#endif
-#if defined (CONFIG_MPC834x)
+# endif
+# if defined(CONFIG_MPC834x)
 	u32 usbmph_clk;
-#endif /* CONFIG_MPC834x */
-#if defined(CONFIG_MPC8315)
+# endif /* CONFIG_MPC834x */
+# if defined(CONFIG_MPC8315)
 	u32 tdm_clk;
-#endif
+# endif
 	u32 core_clk;
 	u32 enc_clk;
 	u32 lbiu_clk;
 	u32 lclk_clk;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC837x)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
-#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+# endif
+# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	u32 sata_clk;
+# endif
+# if defined(CONFIG_MPC8360)
+	u32 mem_sec_clk;
+# endif /* CONFIG_MPC8360 */
 #endif
-#if defined(CONFIG_MPC8360)
-	u32  mem_sec_clk;
-#endif /* CONFIG_MPC8360 */
-#endif
+};
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ */
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned int	baudrate;
+	unsigned long	cpu_clk;	/* CPU clock in Hz! */
+	unsigned long	bus_clk;
+	/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
+	unsigned long pci_clk;
+	unsigned long   mem_clk;
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-- 
cgit v1.1


From 67ac13b1b9b6ca00893714fbc8cbf556bab6fd59 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:48 +0000
Subject: ppc: Move lbc_clk and cpu to arch_global_data

Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/powerpc/cpu/mpc85xx/cpu.c         | 2 +-
 arch/powerpc/cpu/mpc85xx/fdt.c         | 4 ++--
 arch/powerpc/cpu/mpc85xx/speed.c       | 2 +-
 arch/powerpc/cpu/mpc86xx/cpu.c         | 2 +-
 arch/powerpc/cpu/mpc86xx/fdt.c         | 4 ++--
 arch/powerpc/cpu/mpc86xx/speed.c       | 2 +-
 arch/powerpc/cpu/mpc8xxx/cpu.c         | 8 ++++----
 arch/powerpc/include/asm/global_data.h | 8 ++++----
 arch/powerpc/lib/board.c               | 7 ++++---
 9 files changed, 20 insertions(+), 19 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 9b9832c..df2ab6d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -104,7 +104,7 @@ int checkcpu (void)
 		puts("CPU:   ");
 	}
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 
 	puts(cpu->name);
 	if (IS_E_PROCESSOR(svr))
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 3a268aa..d381cf9 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -637,9 +637,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 		"bus-frequency", bd->bi_busfreq, 1);
 
 	do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
-		"bus-frequency", gd->lbc_clk, 1);
+		"bus-frequency", gd->arch.lbc_clk, 1);
 	do_fixup_by_compat_u32(blob, "fsl,elbc",
-		"bus-frequency", gd->lbc_clk, 1);
+		"bus-frequency", gd->arch.lbc_clk, 1);
 #ifdef CONFIG_QE
 	ft_qe_setup(blob);
 	ft_fixup_qe_snum(blob);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index c4ca481..f3132fb 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -391,7 +391,7 @@ int get_clocks (void)
 	gd->cpu_clk = sys_info.freqProcessor[0];
 	gd->bus_clk = sys_info.freqSystemBus;
 	gd->mem_clk = sys_info.freqDDRBus;
-	gd->lbc_clk = sys_info.freqLocalBus;
+	gd->arch.lbc_clk = sys_info.freqLocalBus;
 
 #ifdef CONFIG_QE
 	gd->qe_clk = sys_info.freqQE;
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
index d2c8c78..c553415 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu.c
@@ -67,7 +67,7 @@ checkcpu(void)
 	}
 	puts("CPU:   ");
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 
 	puts(cpu->name);
 
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index 2f955fe..26a65c5 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c
@@ -34,10 +34,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 #if defined(CONFIG_MPC8641)
 	do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus",
-			       "bus-frequency", gd->lbc_clk, 1);
+			       "bus-frequency", gd->arch.lbc_clk, 1);
 #endif
 	do_fixup_by_compat_u32(blob, "fsl,elbc",
-			       "bus-frequency", gd->lbc_clk, 1);
+			       "bus-frequency", gd->arch.lbc_clk, 1);
 
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index a2d0a8a..e5798ee 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -120,7 +120,7 @@ int get_clocks(void)
 	get_sys_info(&sys_info);
 	gd->cpu_clk = sys_info.freqProcessor;
 	gd->bus_clk = sys_info.freqSystemBus;
-	gd->lbc_clk = sys_info.freqLocalBus;
+	gd->arch.lbc_clk = sys_info.freqLocalBus;
 
 	/*
 	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index ab454f5..39525fb 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -148,7 +148,7 @@ struct cpu_type *identify_cpu(u32 ver)
 u32 cpu_mask(void)
 {
 	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
-	struct cpu_type *cpu = gd->cpu;
+	struct cpu_type *cpu = gd->arch.cpu;
 
 	/* better to query feature reporting register than just assume 1 */
 	if (cpu == &cpu_type_unknown)
@@ -166,7 +166,7 @@ u32 cpu_mask(void)
  */
 int cpu_numcores(void)
 {
-	struct cpu_type *cpu = gd->cpu;
+	struct cpu_type *cpu = gd->arch.cpu;
 
 	/*
 	 * Report # of cores in terms of the cpu_mask if we haven't
@@ -196,7 +196,7 @@ int probecpu (void)
 	svr = get_svr();
 	ver = SVR_SOC_VER(svr);
 
-	gd->cpu = identify_cpu(ver);
+	gd->arch.cpu = identify_cpu(ver);
 
 	return 0;
 }
@@ -204,7 +204,7 @@ int probecpu (void)
 /* Once in memory, compute mask & # cores once and save them off */
 int fixup_cpu(void)
 {
-	struct cpu_type *cpu = gd->cpu;
+	struct cpu_type *cpu = gd->arch.cpu;
 
 	if (cpu->num_cores == 0) {
 		cpu->mask = cpu_mask();
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index b7bb035..d924673 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -76,6 +76,10 @@ struct arch_global_data {
 	u32 mem_sec_clk;
 # endif /* CONFIG_MPC8360 */
 #endif
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+	u32 lbc_clk;
+	void *cpu;
+#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
 };
 
 /*
@@ -98,10 +102,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
-	u32 lbc_clk;
-	void *cpu;
-#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
 #if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	u32 i2c1_clk;
 	u32 i2c2_clk;
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 988039f..22bd713 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -649,10 +649,11 @@ void board_init_r(gd_t *id, ulong dest_addr)
 
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	/*
-	 * The gd->cpu pointer is set to an address in flash before relocation.
-	 * We need to update it to point to the same CPU entry in RAM.
+	 * The gd->arch.cpu pointer is set to an address in flash before
+	 * relocation.  We need to update it to point to the same CPU entry
+	 * in RAM.
 	 */
-	gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
+	gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
 
 	/*
 	 * If we didn't know the cpu mask & # cores, we can save them of
-- 
cgit v1.1


From 609e6ec3f623f3c3aa2a056654fbc5886e092897 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:49 +0000
Subject: ppc: m68k: Move i2c1_clk, i2c2_clk to arch_global_data

Move these fields into arch_global_data and tidy up. This is needed for
both ppc and m68k since they share the i2c driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc83xx/speed.c       | 10 ++++++----
 arch/powerpc/cpu/mpc85xx/speed.c       | 10 +++++-----
 arch/powerpc/cpu/mpc86xx/speed.c       |  6 +++---
 arch/powerpc/include/asm/global_data.h |  9 +++++----
 4 files changed, 19 insertions(+), 16 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 7f98ee8..a40a055 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -481,9 +481,9 @@ int get_clocks(void)
 	gd->sdhc_clk = sdhc_clk;
 #endif
 	gd->arch.core_clk = core_clk;
-	gd->i2c1_clk = i2c1_clk;
+	gd->arch.i2c1_clk = i2c1_clk;
 #if !defined(CONFIG_MPC832x)
-	gd->i2c2_clk = i2c2_clk;
+	gd->arch.i2c2_clk = i2c2_clk;
 #endif
 #if !defined(CONFIG_MPC8309)
 	gd->arch.enc_clk = enc_clk;
@@ -558,9 +558,11 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("  SEC:                 %-4s MHz\n",
 	       strmhz(buf, gd->arch.enc_clk));
 #endif
-	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
+	printf("  I2C1:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.i2c1_clk));
 #if !defined(CONFIG_MPC832x)
-	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
+	printf("  I2C2:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.i2c2_clk));
 #endif
 #if defined(CONFIG_MPC8315)
 	printf("  TDM:                 %-4s MHz\n",
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f3132fb..81c80e7 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -406,7 +406,7 @@ int get_clocks (void)
 	 */
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
 	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
-	gd->i2c1_clk = sys_info.freqSystemBus;
+	gd->arch.i2c1_clk = sys_info.freqSystemBus;
 #elif defined(CONFIG_MPC8544)
 	/*
 	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
@@ -416,14 +416,14 @@ int get_clocks (void)
 	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 	 */
 	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
-		gd->i2c1_clk = sys_info.freqSystemBus / 3;
+		gd->arch.i2c1_clk = sys_info.freqSystemBus / 3;
 	else
-		gd->i2c1_clk = sys_info.freqSystemBus / 2;
+		gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #else
 	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
-	gd->i2c1_clk = sys_info.freqSystemBus / 2;
+	gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #endif
-	gd->i2c2_clk = gd->i2c1_clk;
+	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 #if defined(CONFIG_FSL_ESDHC)
 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index e5798ee..18c1eea 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -130,11 +130,11 @@ int get_clocks(void)
 	 * AN2919.
 	 */
 #ifdef CONFIG_MPC8610
-	gd->i2c1_clk = sys_info.freqSystemBus;
+	gd->arch.i2c1_clk = sys_info.freqSystemBus;
 #else
-	gd->i2c1_clk = sys_info.freqSystemBus / 2;
+	gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #endif
-	gd->i2c2_clk = gd->i2c1_clk;
+	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 	if (gd->cpu_clk != 0)
 		return 0;
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index d924673..b710f25 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -80,6 +80,11 @@ struct arch_global_data {
 	u32 lbc_clk;
 	void *cpu;
 #endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+		defined(CONFIG_MPC86xx)
+	u32 i2c1_clk;
+	u32 i2c2_clk;
+#endif
 };
 
 /*
@@ -102,10 +107,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
-	u32 i2c1_clk;
-	u32 i2c2_clk;
-#endif
 #if defined(CONFIG_QE)
 	u32 qe_clk;
 	uint mp_alloc_base;
-- 
cgit v1.1


From 45bae2e3cf6b0653a0c68526be51457f50750dd5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:50 +0000
Subject: ppc: Move CONFIG_QE to arch_global_data

Move the quantative easing fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc83xx/speed.c       |  5 +++--
 arch/powerpc/cpu/mpc85xx/speed.c       |  4 ++--
 arch/powerpc/include/asm/global_data.h | 14 ++++++--------
 3 files changed, 11 insertions(+), 12 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index a40a055..ba8b285 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -495,7 +495,7 @@ int get_clocks(void)
 	gd->arch.mem_sec_clk = mem_sec_clk;
 #endif
 #if defined(CONFIG_QE)
-	gd->qe_clk = qe_clk;
+	gd->arch.qe_clk = qe_clk;
 	gd->arch.brg_clk = brg_clk;
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
@@ -541,7 +541,8 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("  Coherent System Bus: %-4s MHz\n",
 	       strmhz(buf, gd->arch.csb_clk));
 #if defined(CONFIG_QE)
-	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
+	printf("  QE:                  %-4s MHz\n",
+	       strmhz(buf, gd->arch.qe_clk));
 	printf("  BRG:                 %-4s MHz\n",
 	       strmhz(buf, gd->arch.brg_clk));
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 81c80e7..7173c07 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -394,8 +394,8 @@ int get_clocks (void)
 	gd->arch.lbc_clk = sys_info.freqLocalBus;
 
 #ifdef CONFIG_QE
-	gd->qe_clk = sys_info.freqQE;
-	gd->arch.brg_clk = gd->qe_clk / 2;
+	gd->arch.qe_clk = sys_info.freqQE;
+	gd->arch.brg_clk = gd->arch.qe_clk / 2;
 #endif
 	/*
 	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index b710f25..760cdab 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -39,9 +39,6 @@ struct arch_global_data {
 	unsigned long scc_clk;
 	unsigned long brg_clk;
 #endif
-#if defined(CONFIG_QE)
-	u32 brg_clk;
-#endif
 	/* TODO: sjg@chromium.org: Should these be unslgned long? */
 #if defined(CONFIG_MPC83xx)
 	/* There are other clocks in the MPC83XX */
@@ -85,6 +82,12 @@ struct arch_global_data {
 	u32 i2c1_clk;
 	u32 i2c2_clk;
 #endif
+#if defined(CONFIG_QE)
+	u32 qe_clk;
+	u32 brg_clk;
+	uint mp_alloc_base;
+	uint mp_alloc_top;
+#endif /* CONFIG_QE */
 };
 
 /*
@@ -107,11 +110,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-#if defined(CONFIG_QE)
-	u32 qe_clk;
-	uint mp_alloc_base;
-	uint mp_alloc_top;
-#endif /* CONFIG_QE */
 #if defined(CONFIG_FSL_LAW)
 	u32 used_laws;
 #endif
-- 
cgit v1.1


From 8670dbc95361340c3082b62abbbbb3d1ffbb89cb Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:51 +0000
Subject: ppc: Move used_laws to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc8xxx/law.c         | 16 ++++++++--------
 arch/powerpc/include/asm/global_data.h |  6 +++---
 2 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index ce1d71e..6f9d568 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -69,7 +69,7 @@ static inline void set_law_base_addr(int idx, phys_addr_t addr)
 
 void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {
-	gd->used_laws |= (1 << idx);
+	gd->arch.used_laws |= (1 << idx);
 
 	out_be32(LAWAR_ADDR(idx), 0);
 	set_law_base_addr(idx, addr);
@@ -81,7 +81,7 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 
 void disable_law(u8 idx)
 {
-	gd->used_laws &= ~(1 << idx);
+	gd->arch.used_laws &= ~(1 << idx);
 
 	out_be32(LAWAR_ADDR(idx), 0);
 	set_law_base_addr(idx, 0);
@@ -112,7 +112,7 @@ static int get_law_entry(u8 i, struct law_entry *e)
 
 int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {
-	u32 idx = ffz(gd->used_laws);
+	u32 idx = ffz(gd->arch.used_laws);
 
 	if (idx >= FSL_HW_NUM_LAWS)
 		return -1;
@@ -128,11 +128,11 @@ int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 	u32 idx;
 
 	/* we have no LAWs free */
-	if (gd->used_laws == -1)
+	if (gd->arch.used_laws == -1)
 		return -1;
 
 	/* grab the last free law */
-	idx = __ilog2(~(gd->used_laws));
+	idx = __ilog2(~(gd->arch.used_laws));
 
 	if (idx >= FSL_HW_NUM_LAWS)
 		return -1;
@@ -240,9 +240,9 @@ void init_laws(void)
 	int i;
 
 #if FSL_HW_NUM_LAWS < 32
-	gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
+	gd->arch.used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
 #elif FSL_HW_NUM_LAWS == 32
-	gd->used_laws = 0;
+	gd->arch.used_laws = 0;
 #else
 #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
 #endif
@@ -255,7 +255,7 @@ void init_laws(void)
 		u32 lawar = in_be32(LAWAR_ADDR(i));
 
 		if (lawar & LAW_EN)
-			gd->used_laws |= (1 << i);
+			gd->arch.used_laws |= (1 << i);
 	}
 
 #if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 760cdab..c7ce7fd 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -88,6 +88,9 @@ struct arch_global_data {
 	uint mp_alloc_base;
 	uint mp_alloc_top;
 #endif /* CONFIG_QE */
+#if defined(CONFIG_FSL_LAW)
+	u32 used_laws;
+#endif
 };
 
 /*
@@ -110,9 +113,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-#if defined(CONFIG_FSL_LAW)
-	u32 used_laws;
-#endif
 #if defined(CONFIG_E500)
 	u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
 #endif
-- 
cgit v1.1


From 7c80c6c51ab39b4509b4ca79035490eabab0af86 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:52 +0000
Subject: ppc: Move used_tlb_cams to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc85xx/tlb.c         | 8 ++++----
 arch/powerpc/include/asm/global_data.h | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 23d3357..0dff37f 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -99,7 +99,7 @@ static inline void use_tlb_cam(u8 idx)
 	int i = idx / 32;
 	int bit = idx % 32;
 
-	gd->used_tlb_cams[i] |= (1 << bit);
+	gd->arch.used_tlb_cams[i] |= (1 << bit);
 }
 
 static inline void free_tlb_cam(u8 idx)
@@ -107,7 +107,7 @@ static inline void free_tlb_cam(u8 idx)
 	int i = idx / 32;
 	int bit = idx % 32;
 
-	gd->used_tlb_cams[i] &= ~(1 << bit);
+	gd->arch.used_tlb_cams[i] &= ~(1 << bit);
 }
 
 void init_used_tlb_cams(void)
@@ -116,7 +116,7 @@ void init_used_tlb_cams(void)
 	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
 
 	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
-		gd->used_tlb_cams[i] = 0;
+		gd->arch.used_tlb_cams[i] = 0;
 
 	/* walk all the entries */
 	for (i = 0; i < num_cam; i++) {
@@ -133,7 +133,7 @@ int find_free_tlbcam(void)
 	u32 idx;
 
 	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
-		idx = ffz(gd->used_tlb_cams[i]);
+		idx = ffz(gd->arch.used_tlb_cams[i]);
 
 		if (idx != 32)
 			break;
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index c7ce7fd..ca36ca3 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -91,6 +91,9 @@ struct arch_global_data {
 #if defined(CONFIG_FSL_LAW)
 	u32 used_laws;
 #endif
+#if defined(CONFIG_E500)
+	u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
+#endif
 };
 
 /*
@@ -113,9 +116,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-#if defined(CONFIG_E500)
-	u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
-#endif
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	ipb_clk;
 #endif
-- 
cgit v1.1


From b28774966c933780e891998b472528ba0724b8e0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:53 +0000
Subject: ppc: Move mpc5xxx clocks to arch_global_data

Move ipb_clk and pci_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc5xxx/i2c.c         |  2 +-
 arch/powerpc/cpu/mpc5xxx/ide.c         |  2 +-
 arch/powerpc/cpu/mpc5xxx/serial.c      |  4 ++--
 arch/powerpc/cpu/mpc5xxx/speed.c       | 18 ++++++++++++------
 arch/powerpc/cpu/mpc8220/fec.c         |  8 +++++---
 arch/powerpc/include/asm/global_data.h |  6 +++---
 arch/powerpc/lib/board.c               |  2 +-
 7 files changed, 25 insertions(+), 17 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc5xxx/i2c.c b/arch/powerpc/cpu/mpc5xxx/i2c.c
index b423d2f..8d5f47b 100644
--- a/arch/powerpc/cpu/mpc5xxx/i2c.c
+++ b/arch/powerpc/cpu/mpc5xxx/i2c.c
@@ -310,7 +310,7 @@ static int mpc_get_fdr(int speed)
 			{126, 128}
 		};
 
-		ipb = gd->ipb_clk;
+		ipb = gd->arch.ipb_clk;
 		for (i = 7; i >= 0; i--) {
 			for (j = 7; j >= 0; j--) {
 				scl = 2 * (scltap[j].scl2tap +
diff --git a/arch/powerpc/cpu/mpc5xxx/ide.c b/arch/powerpc/cpu/mpc5xxx/ide.c
index d337abb..094f62b 100644
--- a/arch/powerpc/cpu/mpc5xxx/ide.c
+++ b/arch/powerpc/cpu/mpc5xxx/ide.c
@@ -75,7 +75,7 @@ int ide_preinit (void)
 	psdma->PtdCntrl |= 1;
 
 	/* Init timings : we use PIO mode 0 timings */
-	period = 1000000000 / gd->ipb_clk;	/* period in ns */
+	period = 1000000000 / gd->arch.ipb_clk;	/* period in ns */
 
 	t0 = CALC_TIMING (600);
 	t2_8 = CALC_TIMING (290);
diff --git a/arch/powerpc/cpu/mpc5xxx/serial.c b/arch/powerpc/cpu/mpc5xxx/serial.c
index eb14161..1ccb4e3 100644
--- a/arch/powerpc/cpu/mpc5xxx/serial.c
+++ b/arch/powerpc/cpu/mpc5xxx/serial.c
@@ -89,7 +89,7 @@ int serial_init_dev (unsigned long dev_base)
 
 	/* select clock sources */
 	psc->psc_clock_select = 0;
-	baseclk = (gd->ipb_clk + 16) / 32;
+	baseclk = (gd->arch.ipb_clk + 16) / 32;
 
 	/* switch to UART mode */
 	psc->sicr = 0;
@@ -169,7 +169,7 @@ void serial_setbrg_dev (unsigned long dev_base)
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
 	unsigned long baseclk, div;
 
-	baseclk = (gd->ipb_clk + 16) / 32;
+	baseclk = (gd->arch.ipb_clk + 16) / 32;
 
 	/* set up UART divisor */
 	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
diff --git a/arch/powerpc/cpu/mpc5xxx/speed.c b/arch/powerpc/cpu/mpc5xxx/speed.c
index 8027d3e..5353e3d 100644
--- a/arch/powerpc/cpu/mpc5xxx/speed.c
+++ b/arch/powerpc/cpu/mpc5xxx/speed.c
@@ -66,14 +66,20 @@ int get_clocks (void)
 
 	val = *(vu_long *)MPC5XXX_CDM_CFG;
 	if (val & (1 << 8)) {
-		gd->ipb_clk = gd->bus_clk / 2;
+		gd->arch.ipb_clk = gd->bus_clk / 2;
 	} else {
-		gd->ipb_clk = gd->bus_clk;
+		gd->arch.ipb_clk = gd->bus_clk;
 	}
 	switch (val & 3) {
-		case 0: gd->pci_clk = gd->ipb_clk; break;
-		case 1: gd->pci_clk = gd->ipb_clk / 2; break;
-		default: gd->pci_clk = gd->bus_clk / 4; break;
+	case 0:
+		gd->pci_clk = gd->arch.ipb_clk;
+		break;
+	case 1:
+		gd->pci_clk = gd->arch.ipb_clk / 2;
+		break;
+	default:
+		gd->pci_clk = gd->bus_clk / 4;
+		break;
 	}
 
 	return (0);
@@ -85,7 +91,7 @@ int prt_mpc5xxx_clks (void)
 
 	printf ("       Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
 		strmhz(buf1, gd->bus_clk),
-		strmhz(buf2, gd->ipb_clk),
+		strmhz(buf2, gd->arch.ipb_clk),
 		strmhz(buf3, gd->pci_clk)
 	);
 	return (0);
diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c
index aaf9be1..43fa802 100644
--- a/arch/powerpc/cpu/mpc8220/fec.c
+++ b/arch/powerpc/cpu/mpc8220/fec.c
@@ -288,9 +288,11 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 		 * and do not drop the Preamble.
 		 */
-		/* tbd - rtm */
-		/*fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); */
-		/* No MII for 7-wire mode */
+		/*
+		 * tbd - rtm
+		 * fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
+		 * No MII for 7-wire mode
+		 */
 		fec->eth->mii_speed = 0x00000030;
 	}
 
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index ca36ca3..423e792 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -94,6 +94,9 @@ struct arch_global_data {
 #if defined(CONFIG_E500)
 	u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
 #endif
+#if defined(CONFIG_MPC5xxx)
+	unsigned long ipb_clk;
+#endif
 };
 
 /*
@@ -116,9 +119,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-#if defined(CONFIG_MPC5xxx)
-	unsigned long	ipb_clk;
-#endif
 #if defined(CONFIG_MPC512X)
 	u32 ips_clk;
 	u32 csb_clk;
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 22bd713..63118a3 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -589,7 +589,7 @@ void board_init_f(ulong bootflag)
 	bd->bi_ipsfreq = gd->ips_clk;
 #endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC5xxx)
-	bd->bi_ipbfreq = gd->ipb_clk;
+	bd->bi_ipbfreq = gd->arch.ipb_clk;
 	bd->bi_pcifreq = gd->pci_clk;
 #endif /* CONFIG_MPC5xxx */
 	bd->bi_baudrate = gd->baudrate;	/* Console Baudrate     */
-- 
cgit v1.1


From fefb098b187caab34edc72df141125925c9bba62 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:54 +0000
Subject: ppc: Move mpc512x clocks to arch_global_data

Move ips_clk and csb_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc512x/cpu.c         |  2 +-
 arch/powerpc/cpu/mpc512x/i2c.c         |  2 +-
 arch/powerpc/cpu/mpc512x/ide.c         |  2 +-
 arch/powerpc/cpu/mpc512x/serial.c      |  2 +-
 arch/powerpc/cpu/mpc512x/speed.c       | 15 +++++++++------
 arch/powerpc/include/asm/global_data.h |  8 ++++----
 arch/powerpc/lib/board.c               |  2 +-
 7 files changed, 18 insertions(+), 15 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc512x/cpu.c b/arch/powerpc/cpu/mpc512x/cpu.c
index a1a3bd4..641120f 100644
--- a/arch/powerpc/cpu/mpc512x/cpu.c
+++ b/arch/powerpc/cpu/mpc512x/cpu.c
@@ -68,7 +68,7 @@ int checkcpu (void)
 	}
 	printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
 		strmhz(buf1, clock),
-		strmhz(buf2, gd->csb_clk),
+		strmhz(buf2, gd->arch.csb_clk),
 		gd->reset_status & 0xffff);
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc512x/i2c.c b/arch/powerpc/cpu/mpc512x/i2c.c
index 0ea1280..59040f8 100644
--- a/arch/powerpc/cpu/mpc512x/i2c.c
+++ b/arch/powerpc/cpu/mpc512x/i2c.c
@@ -250,7 +250,7 @@ static int mpc_get_fdr (int speed)
 			{126, 128}
 		};
 
-		ips = gd->ips_clk;
+		ips = gd->arch.ips_clk;
 		for (i = 7; i >= 0; i--) {
 			for (j = 7; j >= 0; j--) {
 				scl = 2 * (scltap[j].scl2tap +
diff --git a/arch/powerpc/cpu/mpc512x/ide.c b/arch/powerpc/cpu/mpc512x/ide.c
index dd6b2f4..7a49673 100644
--- a/arch/powerpc/cpu/mpc512x/ide.c
+++ b/arch/powerpc/cpu/mpc512x/ide.c
@@ -100,7 +100,7 @@ int ide_preinit (void)
 	ide_set_reset(0);
 
 	/* Init timings : we use PIO mode 0 timings */
-	t = 1000000000 / gd->ips_clk;	/* period in ns */
+	t = 1000000000 / gd->arch.ips_clk;	/* period in ns */
 	cfg.bytes.field1 = 3;
 	cfg.bytes.field2 = 3;
 	cfg.bytes.field3 = (pio_specs.t1 + t) / t;
diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c
index 58587fd..3afbe81 100644
--- a/arch/powerpc/cpu/mpc512x/serial.c
+++ b/arch/powerpc/cpu/mpc512x/serial.c
@@ -140,7 +140,7 @@ void serial_setbrg_dev(unsigned int idx)
 	}
 
 	/* calculate divisor for setting PSC CTUR and CTLR registers */
-	baseclk = (gd->ips_clk + 8) / 16;
+	baseclk = (gd->arch.ips_clk + 8) / 16;
 	div = (baseclk + (baudrate / 2)) / baudrate;
 
 	out_8(&psc->ctur, (div >> 8) & 0xff);
diff --git a/arch/powerpc/cpu/mpc512x/speed.c b/arch/powerpc/cpu/mpc512x/speed.c
index 9d749f2..9a8f315 100644
--- a/arch/powerpc/cpu/mpc512x/speed.c
+++ b/arch/powerpc/cpu/mpc512x/speed.c
@@ -113,9 +113,9 @@ int get_clocks (void)
 		pci_clk = 333333;
 	}
 
-	gd->ips_clk = ips_clk;
+	gd->arch.ips_clk = ips_clk;
 	gd->pci_clk = pci_clk;
-	gd->csb_clk = csb_clk;
+	gd->arch.csb_clk = csb_clk;
 	gd->cpu_clk = core_clk;
 	gd->bus_clk = csb_clk;
 	return 0;
@@ -128,7 +128,7 @@ int get_clocks (void)
  *********************************************/
 ulong get_bus_freq (ulong dummy)
 {
-	return gd->csb_clk;
+	return gd->arch.csb_clk;
 }
 
 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
@@ -137,10 +137,13 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 
 	printf("Clock configuration:\n");
 	printf("  CPU:                 %-4s MHz\n", strmhz(buf, gd->cpu_clk));
-	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-	printf("  IPS Bus:             %-4s MHz\n", strmhz(buf, gd->ips_clk));
+	printf("  Coherent System Bus: %-4s MHz\n",
+	       strmhz(buf, gd->arch.csb_clk));
+	printf("  IPS Bus:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.ips_clk));
 	printf("  PCI:                 %-4s MHz\n", strmhz(buf, gd->pci_clk));
-	printf("  DDR:                 %-4s MHz\n", strmhz(buf, 2*gd->csb_clk));
+	printf("  DDR:                 %-4s MHz\n",
+	       strmhz(buf, 2 * gd->arch.csb_clk));
 	return 0;
 }
 
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 423e792..fa5c504 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -97,6 +97,10 @@ struct arch_global_data {
 #if defined(CONFIG_MPC5xxx)
 	unsigned long ipb_clk;
 #endif
+#if defined(CONFIG_MPC512X)
+	u32 ips_clk;
+	u32 csb_clk;
+#endif /* CONFIG_MPC512X */
 };
 
 /*
@@ -119,10 +123,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-#if defined(CONFIG_MPC512X)
-	u32 ips_clk;
-	u32 csb_clk;
-#endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC8220)
 	unsigned long   bExtUart;
 	unsigned long   inp_clk;
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 63118a3..3190468 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -586,7 +586,7 @@ void board_init_f(ulong bootflag)
 	bd->bi_vco = gd->arch.vco_out;
 #endif /* CONFIG_CPM2 */
 #if defined(CONFIG_MPC512X)
-	bd->bi_ipsfreq = gd->ips_clk;
+	bd->bi_ipsfreq = gd->arch.ips_clk;
 #endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC5xxx)
 	bd->bi_ipbfreq = gd->arch.ipb_clk;
-- 
cgit v1.1


From 1c356135fa1fd2c2f6d775ba1b2f86e4823d8338 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:55 +0000
Subject: ppc: Move mpc8220 clocks to arch_global_data

Move these fields into arch_global_data and tidy up. The bExtUart field
does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc8220/speed.c       | 12 +++++++-----
 arch/powerpc/include/asm/global_data.h | 13 ++++++-------
 arch/powerpc/lib/board.c               | 14 +++++++-------
 3 files changed, 20 insertions(+), 19 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8220/speed.c b/arch/powerpc/cpu/mpc8220/speed.c
index 62ac845..bb72e5c 100644
--- a/arch/powerpc/cpu/mpc8220/speed.c
+++ b/arch/powerpc/cpu/mpc8220/speed.c
@@ -71,7 +71,7 @@ int get_clocks (void)
 #error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN
 #endif
 
-	gd->inp_clk = CONFIG_SYS_MPC8220_CLKIN;
+	gd->arch.inp_clk = CONFIG_SYS_MPC8220_CLKIN;
 
 	/* Read XLB to PCI(INP) clock multiplier */
 	pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
@@ -85,7 +85,7 @@ int get_clocks (void)
 
 	/* FlexBus is temporary set as the same as input clock */
 	/* will do dynamic in the future */
-	gd->flb_clk = CONFIG_SYS_MPC8220_CLKIN;
+	gd->arch.flb_clk = CONFIG_SYS_MPC8220_CLKIN;
 
 	/* CPU Clock - Read HID1 */
 	asm volatile ("mfspr %0, 1009":"=r" (hid1):);
@@ -97,12 +97,14 @@ int get_clocks (void)
 	for (i = 0; i < size; i++)
 		if (hid1 == bus2core[i].hid1) {
 			gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
-			gd->vco_clk = CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
+			gd->arch.vco_clk =
+				CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER *
+				(gd->pci_clk * bus2core[i].vco_div) / 2;
 			break;
 		}
 
 	/* hardcoded 81MHz for now */
-	gd->pev_clk = 81000000;
+	gd->arch.pev_clk = 81000000;
 
 	return (0);
 }
@@ -115,7 +117,7 @@ int prt_mpc8220_clks (void)
 		strmhz(buf1, gd->bus_clk),
 		strmhz(buf2, gd->cpu_clk),
 		strmhz(buf3, gd->pci_clk),
-		strmhz(buf4, gd->vco_clk)
+		strmhz(buf4, gd->arch.vco_clk)
 	);
 	return (0);
 }
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index fa5c504..656117b 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -101,6 +101,12 @@ struct arch_global_data {
 	u32 ips_clk;
 	u32 csb_clk;
 #endif /* CONFIG_MPC512X */
+#if defined(CONFIG_MPC8220)
+	unsigned long inp_clk;
+	unsigned long vco_clk;
+	unsigned long pev_clk;
+	unsigned long flb_clk;
+#endif
 };
 
 /*
@@ -123,13 +129,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
-#if defined(CONFIG_MPC8220)
-	unsigned long   bExtUart;
-	unsigned long   inp_clk;
-	unsigned long   vco_clk;
-	unsigned long   pev_clk;
-	unsigned long   flb_clk;
-#endif
 	phys_size_t	ram_size;	/* RAM size */
 	unsigned long	reset_status;	/* reset status register at boot	*/
 #if defined(CONFIG_MPC83xx)
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 3190468..12270a4 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -556,11 +556,11 @@ void board_init_f(ulong bootflag)
 #endif
 #if defined(CONFIG_MPC8220)
 	bd->bi_mbar_base = CONFIG_SYS_MBAR;	/* base of internal registers */
-	bd->bi_inpfreq = gd->inp_clk;
+	bd->bi_inpfreq = gd->arch.inp_clk;
 	bd->bi_pcifreq = gd->pci_clk;
-	bd->bi_vcofreq = gd->vco_clk;
-	bd->bi_pevfreq = gd->pev_clk;
-	bd->bi_flbfreq = gd->flb_clk;
+	bd->bi_vcofreq = gd->arch.vco_clk;
+	bd->bi_pevfreq = gd->arch.pev_clk;
+	bd->bi_flbfreq = gd->arch.flb_clk;
 
 	/* store bootparam to sram (backward compatible), here? */
 	{
@@ -568,10 +568,10 @@ void board_init_f(ulong bootflag)
 
 		*sram++ = gd->ram_size;
 		*sram++ = gd->bus_clk;
-		*sram++ = gd->inp_clk;
+		*sram++ = gd->arch.inp_clk;
 		*sram++ = gd->cpu_clk;
-		*sram++ = gd->vco_clk;
-		*sram++ = gd->flb_clk;
+		*sram++ = gd->arch.vco_clk;
+		*sram++ = gd->arch.flb_clk;
 		*sram++ = 0xb8c3ba11;	/* boot signature */
 	}
 #endif
-- 
cgit v1.1


From 3c4c308c0057bb731ac20de1f2b9a3c509008ad0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:56 +0000
Subject: ppc: Move reset_status to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc512x/cpu.c         | 2 +-
 arch/powerpc/cpu/mpc512x/cpu_init.c    | 2 +-
 arch/powerpc/cpu/mpc8260/cpu_init.c    | 4 ++--
 arch/powerpc/cpu/mpc83xx/cpu_init.c    | 4 ++--
 arch/powerpc/include/asm/global_data.h | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc512x/cpu.c b/arch/powerpc/cpu/mpc512x/cpu.c
index 641120f..bb03c6d 100644
--- a/arch/powerpc/cpu/mpc512x/cpu.c
+++ b/arch/powerpc/cpu/mpc512x/cpu.c
@@ -69,7 +69,7 @@ int checkcpu (void)
 	printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
 		strmhz(buf1, clock),
 		strmhz(buf2, gd->arch.csb_clk),
-		gd->reset_status & 0xffff);
+		gd->arch.reset_status & 0xffff);
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c b/arch/powerpc/cpu/mpc512x/cpu_init.c
index fe6beaf..32ade1b 100644
--- a/arch/powerpc/cpu/mpc512x/cpu_init.c
+++ b/arch/powerpc/cpu/mpc512x/cpu_init.c
@@ -62,7 +62,7 @@ void cpu_init_f (volatile immap_t * im)
 #endif
 
 	/* RSR - Reset Status Register - clear all status */
-	gd->reset_status = im->reset.rsr;
+	gd->arch.reset_status = im->reset.rsr;
 	out_be32(&im->reset.rsr, ~RSR_RES);
 
 	/*
diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c
index acd48a9..3964e60 100644
--- a/arch/powerpc/cpu/mpc8260/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8260/cpu_init.c
@@ -120,7 +120,7 @@ void cpu_init_f (volatile immap_t * immr)
 	memset ((void *) gd, 0, sizeof (gd_t));
 
 	/* RSR - Reset Status Register - clear all status (5-4) */
-	gd->reset_status = immr->im_clkrst.car_rsr;
+	gd->arch.reset_status = immr->im_clkrst.car_rsr;
 	immr->im_clkrst.car_rsr = RSR_ALLBITS;
 
 	/* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
@@ -274,7 +274,7 @@ int prt_8260_rsr (void)
 		RSR_EHRS, "External Hard"}
 	};
 	static int n = sizeof bits / sizeof bits[0];
-	ulong rsr = gd->reset_status;
+	ulong rsr = gd->arch.reset_status;
 	int i;
 	char *sep;
 
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 20d0600..9325110 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -232,7 +232,7 @@ void cpu_init_f (volatile immap_t * im)
 	clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 
 	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
-	gd->reset_status = __raw_readl(&im->reset.rsr);
+	gd->arch.reset_status = __raw_readl(&im->reset.rsr);
 	__raw_writel(~(RSR_RES), &im->reset.rsr);
 
 	/* AER - Arbiter Event Register - store status */
@@ -499,7 +499,7 @@ int prt_83xx_rsr(void)
 		RSR_HRS,  "External/Internal Hard"}
 	};
 	static int n = sizeof bits / sizeof bits[0];
-	ulong rsr = gd->reset_status;
+	ulong rsr = gd->arch.reset_status;
 	int i;
 	char *sep;
 
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 656117b..136b918 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -107,6 +107,7 @@ struct arch_global_data {
 	unsigned long pev_clk;
 	unsigned long flb_clk;
 #endif
+	unsigned long reset_status;	/* reset status register at boot */
 };
 
 /*
@@ -130,7 +131,6 @@ typedef	struct	global_data {
 	u32 sdhc_clk;
 #endif
 	phys_size_t	ram_size;	/* RAM size */
-	unsigned long	reset_status;	/* reset status register at boot	*/
 #if defined(CONFIG_MPC83xx)
 	unsigned long	arbiter_event_attributes;
 	unsigned long	arbiter_event_address;
-- 
cgit v1.1


From 43e60814b3ee690c02ebf86391b341aeaef9fb0e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:57 +0000
Subject: ppc: Move arbiter fields to arch_global_data

Move arbiter_event_attributes and arbiter_event_address into
arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc83xx/cpu_init.c    | 28 +++++++++++++++-------------
 arch/powerpc/include/asm/global_data.h |  8 ++++----
 2 files changed, 19 insertions(+), 17 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 9325110..5153351 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -236,8 +236,8 @@ void cpu_init_f (volatile immap_t * im)
 	__raw_writel(~(RSR_RES), &im->reset.rsr);
 
 	/* AER - Arbiter Event Register - store status */
-	gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
-	gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
+	gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
+	gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 
 	/*
 	 * RMR - Reset Mode Register
@@ -440,42 +440,44 @@ static int print_83xx_arb_event(int force)
 		"reserved"
 	};
 
-	int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
+	int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
 	            >> AEATR_EVENT_SHIFT;
-	int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
+	int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
 	              >> AEATR_MSTR_ID_SHIFT;
-	int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
+	int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
 	           >> AEATR_TBST_SHIFT;
-	int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
+	int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
 	            >> AEATR_TSIZE_SHIFT;
-	int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
+	int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
 	            >> AEATR_TTYPE_SHIFT;
 
-	if (!force && !gd->arbiter_event_address)
+	if (!force && !gd->arch.arbiter_event_address)
 		return 0;
 
 	puts("Arbiter Event Status:\n");
-	printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
+	printf("       Event Address: 0x%08lX\n",
+	       gd->arch.arbiter_event_address);
 	printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 	printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 	printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 				tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 	printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 
-	return gd->arbiter_event_address;
+	return gd->arch.arbiter_event_address;
 }
 
 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 
 static int print_83xx_arb_event(int force)
 {
-	if (!force && !gd->arbiter_event_address)
+	if (!force && !gd->arch.arbiter_event_address)
 		return 0;
 
 	printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
-		gd->arbiter_event_attributes, gd->arbiter_event_address);
+		gd->arch.arbiter_event_attributes,
+		gd->arch.arbiter_event_address);
 
-	return gd->arbiter_event_address;
+	return gd->arch.arbiter_event_address;
 }
 #endif /* CONFIG_DISPLAY_AER_xxxx */
 
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 136b918..b7534cd 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -108,6 +108,10 @@ struct arch_global_data {
 	unsigned long flb_clk;
 #endif
 	unsigned long reset_status;	/* reset status register at boot */
+#if defined(CONFIG_MPC83xx)
+	unsigned long arbiter_event_attributes;
+	unsigned long arbiter_event_address;
+#endif
 };
 
 /*
@@ -131,10 +135,6 @@ typedef	struct	global_data {
 	u32 sdhc_clk;
 #endif
 	phys_size_t	ram_size;	/* RAM size */
-#if defined(CONFIG_MPC83xx)
-	unsigned long	arbiter_event_attributes;
-	unsigned long	arbiter_event_address;
-#endif
 	unsigned long	env_addr;	/* Address  of Environment struct	*/
 	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
 	unsigned long	have_console;	/* serial_init() was called		*/
-- 
cgit v1.1


From 6bb9ba72608e766e9ce859b78f19bb7ea8f63a18 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:58 +0000
Subject: ppc: Move dp_alloc_base, dp_alloc_top to arch_global_data

Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc8260/commproc.c    | 19 ++++++++++---------
 arch/powerpc/cpu/mpc85xx/commproc.c    | 19 ++++++++++---------
 arch/powerpc/cpu/mpc8xx/commproc.c     | 20 ++++++++++----------
 arch/powerpc/include/asm/global_data.h |  8 ++++----
 4 files changed, 34 insertions(+), 32 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c
index e5bfed1..22cef3e 100644
--- a/arch/powerpc/cpu/mpc8260/commproc.c
+++ b/arch/powerpc/cpu/mpc8260/commproc.c
@@ -30,8 +30,8 @@ m8260_cpm_reset(void)
 
 	/* Reclaim the DP memory for our use.
 	*/
-	gd->dp_alloc_base = CPM_DATAONLY_BASE;
-	gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
+	gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+	gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
 
 	/*
 	 * Reset CPM
@@ -60,21 +60,22 @@ m8260_cpm_dpalloc(uint size, uint align)
 	uint	savebase;
 
 	align_mask = align - 1;
-	savebase = gd->dp_alloc_base;
+	savebase = gd->arch.dp_alloc_base;
 
-	if ((off = (gd->dp_alloc_base & align_mask)) != 0)
-		gd->dp_alloc_base += (align - off);
+	off = gd->arch.dp_alloc_base & align_mask;
+	if (off != 0)
+		gd->arch.dp_alloc_base += (align - off);
 
 	if ((off = size & align_mask) != 0)
 		size += align - off;
 
-	if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
-		gd->dp_alloc_base = savebase;
+	if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
+		gd->arch.dp_alloc_base = savebase;
 		panic("m8260_cpm_dpalloc: ran out of dual port ram!");
 	}
 
-	retloc = gd->dp_alloc_base;
-	gd->dp_alloc_base += size;
+	retloc = gd->arch.dp_alloc_base;
+	gd->arch.dp_alloc_base += size;
 
 	memset((void *)&immr->im_dprambase[retloc], 0, size);
 
diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c b/arch/powerpc/cpu/mpc85xx/commproc.c
index 7f10476..37e7062 100644
--- a/arch/powerpc/cpu/mpc85xx/commproc.c
+++ b/arch/powerpc/cpu/mpc85xx/commproc.c
@@ -43,8 +43,8 @@ m8560_cpm_reset(void)
 
 	/* Reclaim the DP memory for our use.
 	*/
-	gd->dp_alloc_base = CPM_DATAONLY_BASE;
-	gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
+	gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+	gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
 
 	/*
 	 * Reset CPM
@@ -69,21 +69,22 @@ m8560_cpm_dpalloc(uint size, uint align)
 	uint	savebase;
 
 	align_mask = align - 1;
-	savebase = gd->dp_alloc_base;
+	savebase = gd->arch.dp_alloc_base;
 
-	if ((off = (gd->dp_alloc_base & align_mask)) != 0)
-		gd->dp_alloc_base += (align - off);
+	off = gd->arch.dp_alloc_base & align_mask;
+	if (off != 0)
+		gd->arch.dp_alloc_base += (align - off);
 
 	if ((off = size & align_mask) != 0)
 		size += align - off;
 
-	if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
-		gd->dp_alloc_base = savebase;
+	if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
+		gd->arch.dp_alloc_base = savebase;
 		panic("m8560_cpm_dpalloc: ran out of dual port ram!");
 	}
 
-	retloc = gd->dp_alloc_base;
-	gd->dp_alloc_base += size;
+	retloc = gd->arch.dp_alloc_base;
+	gd->arch.dp_alloc_base += size;
 
 	memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
 
diff --git a/arch/powerpc/cpu/mpc8xx/commproc.c b/arch/powerpc/cpu/mpc8xx/commproc.c
index 5fe01ff..a364782 100644
--- a/arch/powerpc/cpu/mpc8xx/commproc.c
+++ b/arch/powerpc/cpu/mpc8xx/commproc.c
@@ -31,8 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
 int dpram_init (void)
 {
 	/* Reclaim the DP memory for our use. */
-	gd->dp_alloc_base = CPM_DATAONLY_BASE;
-	gd->dp_alloc_top  = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE;
+	gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+	gd->arch.dp_alloc_top  = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE;
 
 	return (0);
 }
@@ -43,19 +43,19 @@ int dpram_init (void)
  */
 uint dpram_alloc (uint size)
 {
-	uint addr = gd->dp_alloc_base;
+	uint addr = gd->arch.dp_alloc_base;
 
-	if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top)
+	if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top)
 		return (CPM_DP_NOSPACE);
 
-	gd->dp_alloc_base += size;
+	gd->arch.dp_alloc_base += size;
 
 	return addr;
 }
 
 uint dpram_base (void)
 {
-	return gd->dp_alloc_base;
+	return gd->arch.dp_alloc_base;
 }
 
 /* Allocate some memory from the dual ported ram.  We may want to
@@ -66,12 +66,12 @@ uint dpram_alloc_align (uint size, uint align)
 {
 	uint addr, mask = align - 1;
 
-	addr = (gd->dp_alloc_base + mask) & ~mask;
+	addr = (gd->arch.dp_alloc_base + mask) & ~mask;
 
-	if ((addr + size) >= gd->dp_alloc_top)
+	if ((addr + size) >= gd->arch.dp_alloc_top)
 		return (CPM_DP_NOSPACE);
 
-	gd->dp_alloc_base = addr + size;
+	gd->arch.dp_alloc_base = addr + size;
 
 	return addr;
 }
@@ -80,6 +80,6 @@ uint dpram_base_align (uint align)
 {
 	uint mask = align - 1;
 
-	return (gd->dp_alloc_base + mask) & ~mask;
+	return (gd->arch.dp_alloc_base + mask) & ~mask;
 }
 #endif	/* CONFIG_SYS_ALLOC_DPRAM */
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index b7534cd..87f9268 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -112,6 +112,10 @@ struct arch_global_data {
 	unsigned long arbiter_event_attributes;
 	unsigned long arbiter_event_address;
 #endif
+#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
+	unsigned int dp_alloc_base;
+	unsigned int dp_alloc_top;
+#endif
 };
 
 /*
@@ -141,10 +145,6 @@ typedef	struct	global_data {
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
 #endif
-#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
-	unsigned int	dp_alloc_base;
-	unsigned int	dp_alloc_top;
-#endif
 #if defined(CONFIG_4xx)
 	u32  uart_clk;
 #endif /* CONFIG_4xx */
-- 
cgit v1.1


From 3a1dc8f1251e03c06d45120612a27ae2c448bae7 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:48:59 +0000
Subject: arm: Move uart_clk to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/ppc4xx/4xx_uart.c     | 4 ++--
 arch/powerpc/cpu/ppc4xx/fdt.c          | 4 ++--
 arch/powerpc/include/asm/global_data.h | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
index 38ba60b..2ab185f 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
@@ -296,10 +296,10 @@ int get_serial_clock(void)
 	 * the UART divisor is available
 	 */
 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
-	gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
+	gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 #else
 	get_sys_info(&sys_info);
-	gd->uart_clk = sys_info.freqUART / udiv;
+	gd->arch.uart_clk = sys_info.freqUART / udiv;
 #endif
 
 	return clk;
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index 5ddb880..37f5817 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -141,7 +141,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 	/*
 	 * Fixup all UART clocks for CPU internal UARTs
-	 * (only these UARTs are definitely clocked by gd->uart_clk)
+	 * (only these UARTs are definitely clocked by gd->arch.uart_clk)
 	 *
 	 * These UARTs are direct childs of /plb/opb. This code
 	 * does not touch any UARTs that are connected to the ebc.
@@ -160,7 +160,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 		    (fdt_node_check_compatible(blob, off, "ns16550") == 0))
 			fdt_setprop(blob, off,
 				    "clock-frequency",
-				    (void*)&(gd->uart_clk), 4);
+				    (void *)&gd->arch.uart_clk, 4);
 	}
 
 	/*
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 87f9268..2d7be45 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -116,6 +116,9 @@ struct arch_global_data {
 	unsigned int dp_alloc_base;
 	unsigned int dp_alloc_top;
 #endif
+#if defined(CONFIG_4xx)
+	u32 uart_clk;
+#endif /* CONFIG_4xx */
 };
 
 /*
@@ -145,9 +148,6 @@ typedef	struct	global_data {
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
 #endif
-#if defined(CONFIG_4xx)
-	u32  uart_clk;
-#endif /* CONFIG_4xx */
 #if defined(CONFIG_SYS_GT_6426x)
 	unsigned int	mirror_hack[16];
 #endif
-- 
cgit v1.1


From 7e15d6dbf30d49e0c9cffdefa4e7e94ddf815d1d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:49:00 +0000
Subject: ppc: Move mirror_hack to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/include/asm/global_data.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 2d7be45..b9037c4 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -119,6 +119,9 @@ struct arch_global_data {
 #if defined(CONFIG_4xx)
 	u32 uart_clk;
 #endif /* CONFIG_4xx */
+#if defined(CONFIG_SYS_GT_6426x)
+	unsigned int mirror_hack[16];
+#endif
 };
 
 /*
@@ -148,9 +151,6 @@ typedef	struct	global_data {
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
 #endif
-#if defined(CONFIG_SYS_GT_6426x)
-	unsigned int	mirror_hack[16];
-#endif
 #if defined(CONFIG_A3000)	|| \
     defined(CONFIG_HIDDEN_DRAGON)  || \
     defined(CONFIG_MUSENKI)	||  \
-- 
cgit v1.1


From 7273ccec61e26adef6149ddaf261217b30c4f8a9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:49:01 +0000
Subject: ppc: Remove console_addr from global data

This does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/include/asm/global_data.h | 6 ------
 1 file changed, 6 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index b9037c4..6f88b76 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -151,12 +151,6 @@ typedef	struct	global_data {
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
 #endif
-#if defined(CONFIG_A3000)	|| \
-    defined(CONFIG_HIDDEN_DRAGON)  || \
-    defined(CONFIG_MUSENKI)	||  \
-    defined(CONFIG_SANDPOINT)
-	void *		console_addr;
-#endif
 	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
 #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
 	unsigned long	fb_base;	/* Base address of framebuffer memory	*/
-- 
cgit v1.1


From 923a662f2fb09aa67c1ec0de25474c218fad2690 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:49:02 +0000
Subject: ppc: Move fpga_state to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/include/asm/global_data.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 6f88b76..52aece0 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -122,6 +122,9 @@ struct arch_global_data {
 #if defined(CONFIG_SYS_GT_6426x)
 	unsigned int mirror_hack[16];
 #endif
+#ifdef CONFIG_SYS_FPGA_COUNT
+	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
+#endif
 };
 
 /*
@@ -170,9 +173,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
 	unsigned long kbd_status;
 #endif
-#ifdef CONFIG_SYS_FPGA_COUNT
-	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
-#endif
 #if defined(CONFIG_WD_MAX_RATE)
 	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
 #endif
-- 
cgit v1.1


From a0d3c820c43e040b001c912a717942219e0fe3ab Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:49:03 +0000
Subject: ppc: Move wdt_last to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/include/asm/global_data.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 52aece0..b138e64 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -125,6 +125,9 @@ struct arch_global_data {
 #ifdef CONFIG_SYS_FPGA_COUNT
 	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
 #endif
+#if defined(CONFIG_WD_MAX_RATE)
+	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
+#endif
 };
 
 /*
@@ -173,9 +176,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
 	unsigned long kbd_status;
 #endif
-#if defined(CONFIG_WD_MAX_RATE)
-	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
-#endif
 	void		**jt;		/* jump table */
 	char		env_buf[32];	/* buffer for getenv() before reloc. */
 	struct arch_global_data arch;	/* architecture-specific data */
-- 
cgit v1.1


From 225ca83dfea4f9b9a313c5233297132206bff431 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:49:04 +0000
Subject: ppc: Move kbd_status to arch_global_data

Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/include/asm/global_data.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index b138e64..ea67537 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -128,6 +128,9 @@ struct arch_global_data {
 #if defined(CONFIG_WD_MAX_RATE)
 	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
 #endif
+#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
+	unsigned long kbd_status;
+#endif
 };
 
 /*
@@ -173,9 +176,6 @@ typedef	struct	global_data {
 	unsigned long do_mdm_init;
 	unsigned long be_quiet;
 #endif
-#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
-	unsigned long kbd_status;
-#endif
 	void		**jt;		/* jump table */
 	char		env_buf[32];	/* buffer for getenv() before reloc. */
 	struct arch_global_data arch;	/* architecture-specific data */
-- 
cgit v1.1


From e9adeca3fc4fd9b353f2514daa7d799076ae079c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:49:05 +0000
Subject: ppc: arm: Move sdhc_clk into arch_global_data

This is used by both powerpc and arm, but I think it still qualifies as
architecture-specific.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/cpu/mpc83xx/speed.c       | 5 +++--
 arch/powerpc/cpu/mpc85xx/speed.c       | 4 ++--
 arch/powerpc/include/asm/global_data.h | 6 +++---
 3 files changed, 8 insertions(+), 7 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index ba8b285..6be0e3a 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -478,7 +478,7 @@ int get_clocks(void)
 	gd->arch.tdm_clk = tdm_clk;
 #endif
 #if defined(CONFIG_FSL_ESDHC)
-	gd->sdhc_clk = sdhc_clk;
+	gd->arch.sdhc_clk = sdhc_clk;
 #endif
 	gd->arch.core_clk = core_clk;
 	gd->arch.i2c1_clk = i2c1_clk;
@@ -570,7 +570,8 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	       strmhz(buf, gd->arch.tdm_clk));
 #endif
 #if defined(CONFIG_FSL_ESDHC)
-	printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
+	printf("  SDHC:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.sdhc_clk));
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 7173c07..297f2ed 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -428,9 +428,9 @@ int get_clocks (void)
 #if defined(CONFIG_FSL_ESDHC)
 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
        defined(CONFIG_P1014)
-	gd->sdhc_clk = gd->bus_clk;
+	gd->arch.sdhc_clk = gd->bus_clk;
 #else
-	gd->sdhc_clk = gd->bus_clk / 2;
+	gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index ea67537..9bf18fb 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -29,6 +29,9 @@
 
 /* Architecture-specific global data */
 struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+	u32 sdhc_clk;
+#endif
 #if defined(CONFIG_8xx)
 	unsigned long brg_clk;
 #endif
@@ -150,9 +153,6 @@ typedef	struct	global_data {
 	/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
 	unsigned long pci_clk;
 	unsigned long   mem_clk;
-#if defined(CONFIG_FSL_ESDHC)
-	u32 sdhc_clk;
-#endif
 	phys_size_t	ram_size;	/* RAM size */
 	unsigned long	env_addr;	/* Address  of Environment struct	*/
 	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
-- 
cgit v1.1


From 2ab575e05d715a1b9818b4a1f6a9d7ccb5bdb32a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 13 Dec 2012 20:49:23 +0000
Subject: powerpc: Use generic global_data

Move powerpc over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/powerpc/include/asm/global_data.h | 47 +---------------------------------
 1 file changed, 1 insertion(+), 46 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 9bf18fb..d5db854 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -136,52 +136,7 @@ struct arch_global_data {
 #endif
 };
 
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned int	baudrate;
-	unsigned long	cpu_clk;	/* CPU clock in Hz! */
-	unsigned long	bus_clk;
-	/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
-	unsigned long pci_clk;
-	unsigned long   mem_clk;
-	phys_size_t	ram_size;	/* RAM size */
-	unsigned long	env_addr;	/* Address  of Environment struct	*/
-	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
-	unsigned long	have_console;	/* serial_init() was called		*/
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
-#endif
-	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
-	unsigned long	fb_base;	/* Base address of framebuffer memory	*/
-#endif
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-	unsigned long	post_log_word;  /* Record POST activities */
-	unsigned long	post_log_res; /* success of POST test */
-	unsigned long	post_init_f_time;  /* When post_init_f started */
-#endif
-#ifdef CONFIG_BOARD_TYPES
-	unsigned long	board_type;
-#endif
-#ifdef CONFIG_MODEM_SUPPORT
-	unsigned long do_mdm_init;
-	unsigned long be_quiet;
-#endif
-	void		**jt;		/* jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-	struct arch_global_data arch;	/* architecture-specific data */
-} gd_t;
-
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #if 1
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r2")
-- 
cgit v1.1


From 12e06fe03fdcd9cb9e9805ff78d1027377a1416d Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Wed, 16 Jan 2013 13:59:04 +0000
Subject: treewide: include libfdt_env.h before fdt.h

and, if including libfdt.h which includes libfdt_env.h in
the correct order, don't include fdt.h before libfdt.h.

this is needed to get the fdt type definitions set from
the project environment before fdt.h uses them.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
---
 arch/powerpc/lib/bootm.c | 1 -
 1 file changed, 1 deletion(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 7088293..33d013f 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -36,7 +36,6 @@
 #include <asm/mp.h>
 
 #if defined(CONFIG_OF_LIBFDT)
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
-- 
cgit v1.1


From 8aa5ec6e1628116e655fbd036391ebc1987588f9 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Wed, 16 Jan 2013 14:00:11 +0000
Subject: common/fdt_support.c: sparse fixes

trivial:

fdt_support.c:89:64: warning: Using plain integer as NULL pointer
fdt_support.c:325:65: warning: Using plain integer as NULL pointer
fdt_support.c:352:65: warning: Using plain integer as NULL pointer

For the following bad constant expression, We hardcode the max. number of
memory banks to four for the foreseeable future, and add an error with
instructions on what to do once it's exceeded:

fdt_support.c:397:22: error: bad constant expression

For the rest below, sparse found a couple of wrong endian conversions
in of_bus_default_translate() and fdt_get_base_address(), but
otherwise the rest is mostly annotation fixes:

fdt_support.c:64:24: warning: cast to restricted __be32
fdt_support.c:192:21: warning: incorrect type in assignment (different base types)
fdt_support.c:192:21:    expected unsigned int [unsigned] [usertype] tmp
fdt_support.c:192:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:201:21: warning: incorrect type in assignment (different base types)
fdt_support.c:201:21:    expected unsigned int [unsigned] [addressable] [usertype] tmp
fdt_support.c:201:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:304:13: warning: incorrect type in assignment (different base types)
fdt_support.c:304:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:304:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:333:13: warning: incorrect type in assignment (different base types)
fdt_support.c:333:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:333:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:359:13: warning: incorrect type in assignment (different base types)
fdt_support.c:359:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:359:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:373:21: warning: cast to restricted __be32
fdt_support.c:963:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:963:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:963:48:    got unsigned int [usertype] *<noident>
fdt_support.c:971:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:971:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:971:48:    got unsigned int [usertype] *<noident>
fdt_support.c:984:29: warning: incorrect type in argument 1 (different base types)
fdt_support.c:984:29:    expected restricted __be32 const [usertype] *cell
fdt_support.c:984:29:    got unsigned int [usertype] *addr
fdt_support.c:996:32: warning: incorrect type in argument 1 (different base types)
fdt_support.c:996:32:    expected restricted __be32 const [usertype] *cell
fdt_support.c:996:32:    got unsigned int [usertype] *addr
fdt_support.c:1041:41: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1041:41:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1041:41:    got unsigned int [usertype] *addr
fdt_support.c:1053:41: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1053:41:    expected restricted __be32 const [usertype] *range
fdt_support.c:1053:41:    got unsigned int const [usertype] *[assigned] ranges
fdt_support.c:1064:53: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1064:53:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1064:53:    got unsigned int [usertype] *addr
fdt_support.c:1110:50: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1110:50:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1110:50:    got unsigned int *<noident>
fdt_support.c:1121:49: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1121:49:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1121:49:    got unsigned int *<noident>
fdt_support.c:1147:60: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1147:60:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1147:60:    got unsigned int *<noident>
fdt_support.c:1081:5: warning: symbol '__of_translate_address' was not declared. Should it be static?
fdt_support.c:1154:5: error: symbol 'fdt_translate_address' redeclared with different type (originally declared at include/fdt_support.h:95) - incompatible argument 3 (different base types)
fdt_support.c: In function 'fdt_node_offset_by_compat_reg':
fdt_support.c:1173:17: warning: initialization discards 'const' qualifier from pointer target type [enabled by default]

See also linux kernel commit 0131d897 "of/address: use proper
endianess in get_flags".

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
---
 arch/powerpc/cpu/mpc85xx/fdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index d381cf9..24eb978 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -811,7 +811,7 @@ int ft_verify_fdt(void *fdt)
 #ifdef CONFIG_SYS_LBC_ADDR
 	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
 	if (off > 0) {
-		const u32 *reg = fdt_getprop(fdt, off, "reg", NULL);
+		const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
 		if (reg) {
 			uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
 
-- 
cgit v1.1


From 58864ddc7276ca7403ddbb716da5853638f37519 Mon Sep 17 00:00:00 2001
From: Gerald Van Baren <gvb@unssw.com>
Date: Thu, 7 Feb 2013 19:49:54 -0500
Subject: Clean up libfdt.h includes

The libfdt.h file is the definition file for libfdt.  It is unnecessary
to include other fdt header files (the necessary ones are pulled in
by libfdt.h).

Signed-off-by: Gerald Van Baren <gvb@unssw.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
---
 arch/powerpc/cpu/mpc5xxx/cpu.c | 1 -
 arch/powerpc/cpu/mpc8260/cpu.c | 1 -
 arch/powerpc/cpu/mpc8xx/cpu.c  | 1 -
 arch/powerpc/cpu/ppc4xx/fdt.c  | 1 -
 arch/powerpc/lib/bootm.c       | 1 -
 5 files changed, 5 deletions(-)

(limited to 'arch/powerpc')

diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c
index 0c1eebd..dc021e3 100644
--- a/arch/powerpc/cpu/mpc5xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc5xxx/cpu.c
@@ -36,7 +36,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif
 
diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c
index 220c1e2..f8bc5a9 100644
--- a/arch/powerpc/cpu/mpc8260/cpu.c
+++ b/arch/powerpc/cpu/mpc8260/cpu.c
@@ -50,7 +50,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif
 
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index b3fcfe5..b6b733d 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -45,7 +45,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif
 
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index 37f5817..3cdd531 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -29,7 +29,6 @@
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #include <asm/4xx_pcie.h>
 
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 33d013f..0119a7b 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -38,7 +38,6 @@
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #include <fdt_support.h>
-
 #endif
 
 #ifdef CONFIG_SYS_INIT_RAM_LOCK
-- 
cgit v1.1