From 51370d561842ae7438337e77a93177e13796ac45 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 28 Dec 2016 08:43:45 -0800 Subject: ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu.c | 22 +++++++++++----------- arch/powerpc/cpu/mpc85xx/cpu_init.c | 16 ++++++++-------- 2 files changed, 19 insertions(+), 19 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index d180c73..cc30fa6 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -482,17 +482,17 @@ static void dump_spd_ddr_reg(void) int i, j, k, m; u8 *p_8; u32 *p_32; - struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS]; generic_spd_eeprom_t - spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; + spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR]; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR); puts("SPD data of all dimms (zero value is omitted)...\n"); puts("Byte (hex) "); k = 1; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) printf("Dimm%d ", k++); } @@ -500,7 +500,7 @@ static void dump_spd_ddr_reg(void) for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { m = 0; printf("%3d (0x%02x) ", k, k); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { p_8 = (u8 *) &spd[i][j]; if (p_8[k]) { @@ -516,22 +516,22 @@ static void dump_spd_ddr_reg(void) puts("\r"); } - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { switch (i) { case 0: ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) case 3: ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; @@ -545,13 +545,13 @@ static void dump_spd_ddr_reg(void) printf("DDR registers dump for all controllers " "(zero value is omitted)...\n"); puts("Offset (hex) "); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); puts("\n"); for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { m = 0; printf("%6d (0x%04x)", k * 4, k * 4); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { p_32 = (u32 *) ddr[i]; if (p_32[k]) { printf(" 0x%08x", p_32[k]); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4dff5c8..822844d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -378,10 +378,10 @@ void fsl_erratum_a007212_workaround(void) u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); #endif @@ -409,25 +409,25 @@ void fsl_erratum_a007212_workaround(void) ddr_pll_ratio >>= 1; setbits_be32(plldadcr1, 0x02000001); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) setbits_be32(plldadcr2, 0x02000001); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) setbits_be32(plldadcr3, 0x02000001); #endif #endif setbits_be32(dpdovrcr4, 0xe0000000); out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); #endif #endif udelay(100); clrbits_be32(plldadcr1, 0x02000001); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) clrbits_be32(plldadcr2, 0x02000001); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) clrbits_be32(plldadcr3, 0x02000001); #endif #endif -- cgit v1.1