From 8e2615752ee6d5daf8ce2e1e599a0512750f24b9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 20:09:58 +0900 Subject: bd_info: remove bi_barudrate member from struct bd_info gd->bd->bi_baudrate is a copy of gd->baudrate. Since baudrate is a common feature for all architectures, keep gd->baudrate only. It is true that bi_baudrate was passed to the kernel in that structure but it was a long time ago. Signed-off-by: Masahiro Yamada Cc: Tom Rini Cc: Simon Glass Cc: Wolfgang Denk Cc: Heiko Schocher Acked-by: Michal Simek (For microblaze) --- arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- arch/powerpc/include/asm/u-boot.h | 1 - arch/powerpc/lib/board.c | 1 - 3 files changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 0cc21c7..ed80a84 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -674,7 +674,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_CPM2 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", - "current-speed", bd->bi_baudrate, 1); + "current-speed", gd->baudrate, 1); do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", "clock-frequency", bd->bi_brgfreq, 1); diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index f4d4a6b..e1b566f 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -64,7 +64,6 @@ typedef struct bd_info { unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ #if defined(CONFIG_405) || \ defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || \ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 8b03d3a..57b4a09 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -547,7 +547,6 @@ void board_init_f(ulong bootflag) bd->bi_ipbfreq = gd->arch.ipb_clk; bd->bi_pcifreq = gd->pci_clk; #endif /* CONFIG_MPC5xxx */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CONFIG_SYS_EXTBDINFO strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); -- cgit v1.1 From 6f2ed0e9faa87a0b14ada74727297f62e02868cd Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 28 Apr 2014 10:17:10 +0900 Subject: cosmetic: delete misleading comment /* CONFIG_BOARDDIR */ CONFIG_BOARDDIR is not referenced in these linker scripts. The comment /* CONFIG_BOARDDIR */ is misleading. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 2 +- arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 2 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 2 +- arch/powerpc/cpu/mpc85xx/u-boot.lds | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index d77a6dc..f933b21 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "config.h" /* CONFIG_BOARDDIR */ +#include "config.h" #ifndef CONFIG_SYS_MONITOR_LEN #define CONFIG_SYS_MONITOR_LEN 0x80000 diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 844f7e9..b83c553 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -7,7 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "config.h" /* CONFIG_BOARDDIR */ +#include "config.h" OUTPUT_ARCH(powerpc) SECTIONS diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 8453f3a..5ae7b3e 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -7,7 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "config.h" /* CONFIG_BOARDDIR */ +#include "config.h" OUTPUT_ARCH(powerpc) #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 0b9086d..2cf0b25 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "config.h" /* CONFIG_BOARDDIR */ +#include "config.h" #ifdef CONFIG_RESET_VECTOR_ADDRESS #define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS -- cgit v1.1 From 0b2e13d9ccbe56e32dc674cf896b2fb55684368c Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Mon, 14 Apr 2014 18:42:06 +0800 Subject: powerpc/85xx: Add T4240RDB board support T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h] --- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index f181315..1a3cb33 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -64,11 +64,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +#ifdef CONFIG_SYS_SRIO struct srio_liodn_id_table srio_liodn_tbl[] = { SET_SRIO_LIODN_BASE(1, 307), SET_SRIO_LIODN_BASE(2, 387), }; int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN -- cgit v1.1 From 4067815998a45ed18e4e42ac9cf655ad07d1d4df Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 22 Apr 2014 15:16:48 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana Signed-off-by: Aneesh Bansal --- arch/powerpc/include/asm/fsl_secure_boot.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 29bef91..9a0cb20 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -21,7 +21,7 @@ defined(CONFIG_T4240QDS) || \ defined(CONFIG_T2080QDS) || \ defined(CONFIG_T1040QDS) || \ - defined(CONFIG_T1040RDB) + defined(CONFIG_T104xRDB) #define CONFIG_SYS_CPC_REINIT_F #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 -- cgit v1.1 From e47c2a68517a3acd8e7668e0fc16a2c168ac30b4 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 22 Apr 2014 15:17:06 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal --- arch/powerpc/include/asm/fsl_secure_boot.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 9a0cb20..74c5d8f 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -20,6 +20,7 @@ #if defined(CONFIG_B4860QDS) || \ defined(CONFIG_T4240QDS) || \ defined(CONFIG_T2080QDS) || \ + defined(CONFIG_T2080RDB) || \ defined(CONFIG_T1040QDS) || \ defined(CONFIG_T104xRDB) #define CONFIG_SYS_CPC_REINIT_F -- cgit v1.1 From c665c473b605349b1c58890493255dd70e0b60fe Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 24 Apr 2014 11:10:09 +0800 Subject: powerpc/t208x: enable errata A006261, A006593, A006379 Enable errata A006261, A006593, A006379 for T208x. Additionally enable CONFIG_CMD_ERRATA for T2080RDB. Signed-off-by: Shengzhou Liu --- arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/fsl_errata.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 864e74c..0d6eb49 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -798,6 +798,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 4eba85c..d820121 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -52,6 +52,9 @@ static inline bool has_erratum_a006261(void) return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T1040: return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0); case SVR_P5040: return IS_SVR_REV(svr, 1, 0); } -- cgit v1.1 From 5122dfae5d3cd68e0b6e5e08597df91ba79770aa Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 25 Apr 2014 16:31:22 +0800 Subject: powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu --- arch/powerpc/cpu/mpc85xx/Makefile | 2 ++ arch/powerpc/cpu/mpc85xx/cpu.c | 24 ++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 ++++++++- arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 16 +++++++++++----- arch/powerpc/include/asm/fsl_errata.h | 2 ++ arch/powerpc/include/asm/immap_85xx.h | 6 ++++-- arch/powerpc/include/asm/processor.h | 1 + 10 files changed, 56 insertions(+), 10 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4094785..ad26b43 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o obj-$(CONFIG_PPC_P5040) += p5040_ids.o obj-$(CONFIG_PPC_T4240) += t4240_ids.o obj-$(CONFIG_PPC_T4160) += t4240_ids.o +obj-$(CONFIG_PPC_T4080) += t4240_ids.o obj-$(CONFIG_PPC_B4420) += b4860_ids.o obj-$(CONFIG_PPC_B4860) += b4860_ids.o obj-$(CONFIG_PPC_T1040) += t1040_ids.o @@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o obj-$(CONFIG_PPC_P5040) += p5040_serdes.o obj-$(CONFIG_PPC_T4240) += t4240_serdes.o obj-$(CONFIG_PPC_T4160) += t4240_serdes.o +obj-$(CONFIG_PPC_T4080) += t4240_serdes.o obj-$(CONFIG_PPC_B4420) += b4860_serdes.o obj-$(CONFIG_PPC_B4860) += b4860_serdes.o obj-$(CONFIG_BSC9132) += bsc9132_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 12e8e10..684d400 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -77,6 +77,30 @@ int checkcpu (void) major = SVR_MAJ(svr); minor = SVR_MIN(svr); +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + if (SVR_SOC_VER(svr) == SVR_T4080) { + ccsr_rcpm_t *rcpm = + (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + + setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || + FSL_CORENET_DEVDISR2_DTSEC1_9); + setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); + setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); + + /* It needs SW to disable core4~7 as HW design sake on T4080 */ + for (i = 4; i < 8; i++) + cpu_disable(i); + + /* request core4~7 into PH20 state, prior to entering PCL10 + * state, all cores in cluster should be placed in PH20 state. + */ + setbits_be32(&rcpm->pcph20setr, 0xf0); + + /* put the 2nd cluster into PCL10 state */ + setbits_be32(&rcpm->clpcl10setr, 1 << 1); + } +#endif + if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 36ef232..7e27464 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -462,10 +462,17 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); int enable_cluster_l2(void) { int i = 0; - u32 cluster; + u32 cluster, svr = get_svr(); ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache; + /* only the L2 of first cluster should be enabled as expected on T4080, + * but there is no EOC in the first cluster as HW sake, so return here + * to skip enabling L2 cache of the 2nd cluster. + */ + if (SVR_SOC_VER(svr) == SVR_T4080) + return 0; + cluster = in_be32(&gur->tp_cluster[i].lower); if (cluster & TP_CLUSTER_EOC) return 0; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index d516d4e..3236f6a 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -123,7 +123,8 @@ void get_sys_info(sys_info_t *sys_info) * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) if (SVR_MAJ(get_svr()) >= 2) mem_pll_rat *= 2; #endif diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index ff55e3c..1f99a0a 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -172,7 +172,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 35795c4..dfedc53 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -62,6 +62,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T4240, T4240, 0), CPU_TYPE_ENTRY(T4120, T4120, 0), CPU_TYPE_ENTRY(T4160, T4160, 0), + CPU_TYPE_ENTRY(T4080, T4080, 4), CPU_TYPE_ENTRY(B4860, B4860, 0), CPU_TYPE_ENTRY(G4860, G4860, 0), CPU_TYPE_ENTRY(G4060, G4060, 0), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0d6eb49..8a7d4d8 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -595,7 +595,8 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -611,13 +612,18 @@ #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 #else -#define CONFIG_MAX_CPUS 8 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 7 +#define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#if defined(CONFIG_PPC_T4160) +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#elif defined(CONFIG_PPC_T4080) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } +#endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index d820121..64da4bb 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -16,6 +16,7 @@ static inline bool has_erratum_a006379(void) u32 svr = get_svr(); if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || @@ -49,6 +50,7 @@ static inline bool has_erratum_a006261(void) return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T4240: case SVR_T4160: + case SVR_T4080: return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T1040: return IS_SVR_REV(svr, 1, 0); diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 741b861..eff573b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1748,7 +1748,8 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1848,7 +1849,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 72f30fe..a6f121e 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1111,6 +1111,7 @@ #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 #define SVR_T4160 0x824100 +#define SVR_T4080 0x824102 #define SVR_C291 0x850000 #define SVR_C292 0x850020 #define SVR_C293 0x850030 -- cgit v1.1 From b539534d120c3f017965b25aa36fcfb75db8383c Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 30 Apr 2014 19:21:10 +0200 Subject: PPC 85xx QEMU: Always assume 1 core We only need u-boot to bother about a single core in the QEMU machine. Everything that would require additional knowledge of more cores gets handled by QEMU and passed straight into the payload we execute. Because of this setup, it would be counterproductive to enable SMP support in u-boot. We would have to rip CPUs out of already existing spin tables and respin them from u-boot. It would be a pretty big mess. So only assume we have a single core. This fixes errors about CONFIG_MP being disabled. Signed-off-by: Alexander Graf --- arch/powerpc/cpu/mpc8xxx/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index dfedc53..13bd0ac 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -177,7 +177,7 @@ struct cpu_type *identify_cpu(u32 ver) /* * Return a 32-bit mask indicating which cores are present on this SOC. */ -u32 cpu_mask(void) +__weak u32 cpu_mask(void) { ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->arch.cpu; @@ -196,7 +196,7 @@ u32 cpu_mask(void) /* * Return the number of cores on this SOC. */ -int cpu_numcores(void) +__weak int cpu_numcores(void) { struct cpu_type *cpu = gd->arch.cpu; -- cgit v1.1 From a6c46b994d90f892b608b1b233a04f1fc54f7ab7 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 30 Apr 2014 19:21:11 +0200 Subject: PPC 85xx QEMU: Don't use HID1 For the QEMU machine type, we can plug in either e500v2, e500mc, e5500 or e6500 style cores into the system. U-boot has to work with all of them. So avoid using HID1 which is not available on e500mc systems to make sure we don't trap on it. Signed-off-by: Alexander Graf --- arch/powerpc/cpu/mpc85xx/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 0e3c86a..0149146 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -314,7 +314,7 @@ l2_disabled: #endif mtspr HID0,r0 -#ifndef CONFIG_E500MC +#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500) li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mfspr r3,PVR andi. r3,r3, 0xff -- cgit v1.1 From f13c9156a9b790fa1991ce41a7f9b7261ff85c33 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 30 Apr 2014 19:21:12 +0200 Subject: powerpc/mpc85xx: Update TLB CAMs in relocated mode We want to use the TLB mapping helpers in relocated mode as well. These helpers need to have awareness of already occupied TLB entries. We already had them in sync in non-relocated mode, but need to resync them when we move into relocated. Signed-off-by: Alexander Graf --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 7e27464..2656b79 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -895,6 +895,7 @@ skip_l2: } #endif + init_used_tlb_cams(); return 0; } -- cgit v1.1 From 73a56b6e9f3f1cc2412b5b8a75a3c71f48586c94 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 30 Apr 2014 14:43:45 -0700 Subject: powerpc/mpc85xx: Ignore FDT pointer for non-QEMU in cpu_init_early_f() The pointer of device tree comes from r3 for QEMU. This is not the case for normal SoCs out of reset. Having gd->fdt_blob as 0 is important for other functions to detect the non-existence of device tree. Signed-off-by: York Sun CC: Alexander Graf --- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 998781b..47b712d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -102,11 +102,13 @@ void cpu_init_early_f(void *fdt) for (i = 0; i < sizeof(gd_t); i++) ((char *)gd)[i] = 0; +#ifdef CONFIG_QEMU_E500 /* * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, * so we need to populate it before it accesses it. */ gd->fdt_blob = fdt; +#endif mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); -- cgit v1.1 From 701e640145474131161de53a407d95d0d2f77082 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 30 Apr 2014 14:43:47 -0700 Subject: powerpc/mpc85xx: Fix boot_flag for calling board_init_f() baord_init_f takes one argument, boot_flag. It has not been used for powerpc, until recently changing to use generic board architecture. The boot flag is added as a return value from cpu_init_f(). Signed-off-by: York Sun CC: Alexander Graf --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 ++++--- arch/powerpc/cpu/mpc85xx/spl_minimal.c | 4 +++- arch/powerpc/cpu/mpc85xx/start.S | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2656b79..d6cf885 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -368,12 +368,12 @@ void fsl_erratum_a007212_workaround(void) } #endif -void cpu_init_f (void) +ulong cpu_init_f(void) { + ulong flag = 0; extern void m8560_cpm_reset (void); #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); #endif #if defined(CONFIG_SECURE_BOOT) struct law_entry law; @@ -442,13 +442,14 @@ void cpu_init_f (void) #ifdef CONFIG_DEEP_SLEEP /* disable the console if boot from deep sleep */ if (in_be32(&gur->scrtsr[0]) & (1 << 3)) - gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; #endif #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 fsl_erratum_a007212_workaround(); #endif + return flag; } /* Implement a dummy function for those platforms w/o SERDES */ diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 9e4c6c9..cc45f71 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; -void cpu_init_f(void) +ulong cpu_init_f(void) { #ifdef CONFIG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; @@ -27,6 +27,8 @@ void cpu_init_f(void) out_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); #endif + + return 0; } #ifndef CONFIG_SYS_FSL_TBCLK_DIV diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 0149146..d8c9fb6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1158,7 +1158,7 @@ _start_cont: mtmsr r3 isync - bl cpu_init_f + bl cpu_init_f /* return boot_flag for calling board_init_f */ bl board_init_f isync -- cgit v1.1 From 8bae330f5c6542638da7136f39bc9c13214592cc Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 30 Apr 2014 14:43:48 -0700 Subject: powerpc/mpc86xx: Fix boot_flag for calling board_init_f() The argument boot_flag of board_inti_f() hasn't been used for powerpc until recent changing to use generic board. Set it to 0 as a proper value. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc86xx/start.S | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S index e33672a..ec5f4a7 100644 --- a/arch/powerpc/cpu/mpc86xx/start.S +++ b/arch/powerpc/cpu/mpc86xx/start.S @@ -273,6 +273,7 @@ diag_done: /* bl l2cache_enable */ /* run 1st part of board init code (from Flash) */ + li r3, 0 /* clear boot_flag for calling board_init_f */ bl board_init_f sync -- cgit v1.1 From f1a96ec1a9920854c3308a062caca0b339bd1e3b Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Wed, 7 May 2014 10:50:20 +0800 Subject: fsl/pci: Add workaround for erratum A-005434 By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: Minghuan Lian Signed-off-by: Chunhe Lan Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + 2 files changed, 4 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 9d8acd0..3d37a76 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -299,6 +299,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 check_erratum_a007212(); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + puts("Work-around for Erratum A-005434 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8a7d4d8..e124b07 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -591,6 +591,7 @@ #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A005434 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -- cgit v1.1 From 9c3fdd883a8c9aa32b52abf8ccc180bd4929826f Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Wed, 7 May 2014 14:43:23 +0530 Subject: powerpc/mpc85xx: Added B4460 support B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: Shaveta Leekha Signed-off-by: Sandeep Singh Signed-off-by: Poonam Aggrwal Reviewed-by: York Sun --- arch/powerpc/cpu/mpc8xxx/cpu.c | 1 + arch/powerpc/include/asm/processor.h | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 13bd0ac..15561a1 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -67,6 +67,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(G4860, G4860, 0), CPU_TYPE_ENTRY(G4060, G4060, 0), CPU_TYPE_ENTRY(B4440, B4440, 0), + CPU_TYPE_ENTRY(B4460, B4460, 0), CPU_TYPE_ENTRY(G4440, G4440, 0), CPU_TYPE_ENTRY(B4420, B4420, 0), CPU_TYPE_ENTRY(B4220, B4220, 0), diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index a6f121e..edd7375 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1117,6 +1117,7 @@ #define SVR_C293 0x850030 #define SVR_B4860 0X868000 #define SVR_G4860 0x868001 +#define SVR_B4460 0x868003 #define SVR_G4060 0x868003 #define SVR_B4440 0x868100 #define SVR_G4440 0x868101 -- cgit v1.1 From 80ba6a6f2ae347b84a607ec085c6f0acd1584aaa Mon Sep 17 00:00:00 2001 From: ramneek mehresh Date: Tue, 13 May 2014 15:36:07 +0530 Subject: mpc85xx/p1020:Define number of USB controllers used on P1020RDB-PD platform P1020 SoC which has two USB controllers, but only first one is used on this platform. Signed-off-by: Ramneek Mehresh Reviewed-by: York Sun --- arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index e124b07..34fc8fb 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -247,7 +247,9 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 -- cgit v1.1