From ac337168ad81a18e768e5e3cfff8d229adeb2b25 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 27 Mar 2015 16:07:32 +0100 Subject: powerpc: add 2 common dcache assembly functions This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp Reviewed-by: Tom Rini Reviewed-by: York Sun --- arch/powerpc/lib/ppccache.S | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch/powerpc/lib/ppccache.S') diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index 349a1c1..b96dbc6 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -9,6 +9,9 @@ #include #include +#include + +#include /*------------------------------------------------------------------------------- */ /* Function: ppcDcbf */ @@ -54,3 +57,48 @@ ppcDcbz: ppcSync: sync blr + +/* + * Write any modified data cache blocks out to memory and invalidate them. + * Does not invalidate the corresponding instruction cache blocks. + * + * flush_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + +1: dcbf 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Like above, but invalidate the D-cache. This is used by the 8xx + * to invalidate the cache so the PPC core doesn't get stale data + * from the CPM (no cache snooping here :-). + * + * invalidate_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(invalidate_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + + sync +1: dcbi 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbi's to get to ram */ + blr + -- cgit v1.1