From f9d379a7078f93433a98f3402a27f582a3868878 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 2 Jul 2013 09:22:23 +0530 Subject: board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi Signed-off-by: Priyanka Jain Acked-by: York Sun --- arch/powerpc/include/asm/immap_85xx.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/powerpc/include') diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9097680..37f1edb 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3047,6 +3047,12 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 +#if defined(CONFIG_BSC9132) +#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 +#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ + (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) +#endif + #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ -- cgit v1.1