From e3b28e67329de99a315d509920760dcbc565f8c6 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Sat, 24 Apr 2010 19:27:05 +0200 Subject: mpc512x: add multi serial PSC support Extend mpc512x serial driver to support multiple PSC ports. Subsequent patches for PDM360NG board support make use of this functionality by defining CONFIG_SERIAL_MULTI in the board config file. Additionally the used PSC devices are specified by defining e.g. CONFIG_SYS_PSC1, CONFIG_SYS_PSC4 and CONFIG_SYS_PSC6. Support for PSC devices other than 1, 3, 4 and 6 is not added by this patch because these aren't used currently. In the future it can be easily added using DECLARE_PSC_SERIAL_FUNCTIONS(N) and INIT_PSC_SERIAL_STRUCTURE(N) macros in cpu/mpc512x/serial.c. Additionally you have to add code for registering added devices in serial_initialize() in common/serial.c. Signed-off-by: Anatolij Gustschin --- arch/powerpc/include/asm/immap_512x.h | 108 +++++++++++++++++----------------- 1 file changed, 55 insertions(+), 53 deletions(-) (limited to 'arch/powerpc/include') diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index 95350fd..8bce586 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -1116,66 +1116,68 @@ typedef struct fifoc512x { * * Overall size of FIFOC memory is not documented in the MPC5121e RM, but * tests indicate that it is 1024 words total. + * + * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice. */ -#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */ +#define FIFOC_PSC0_TX_SIZE 0x04 #define FIFOC_PSC0_TX_ADDR 0x0 -#define FIFOC_PSC0_RX_SIZE 0x0 -#define FIFOC_PSC0_RX_ADDR 0x0 +#define FIFOC_PSC0_RX_SIZE 0x04 +#define FIFOC_PSC0_RX_ADDR 0x10 -#define FIFOC_PSC1_TX_SIZE 0x0 -#define FIFOC_PSC1_TX_ADDR 0x0 -#define FIFOC_PSC1_RX_SIZE 0x0 -#define FIFOC_PSC1_RX_ADDR 0x0 +#define FIFOC_PSC1_TX_SIZE 0x04 +#define FIFOC_PSC1_TX_ADDR 0x20 +#define FIFOC_PSC1_RX_SIZE 0x04 +#define FIFOC_PSC1_RX_ADDR 0x30 -#define FIFOC_PSC2_TX_SIZE 0x0 -#define FIFOC_PSC2_TX_ADDR 0x0 -#define FIFOC_PSC2_RX_SIZE 0x0 -#define FIFOC_PSC2_RX_ADDR 0x0 +#define FIFOC_PSC2_TX_SIZE 0x04 +#define FIFOC_PSC2_TX_ADDR 0x40 +#define FIFOC_PSC2_RX_SIZE 0x04 +#define FIFOC_PSC2_RX_ADDR 0x50 #define FIFOC_PSC3_TX_SIZE 0x04 -#define FIFOC_PSC3_TX_ADDR 0x0 +#define FIFOC_PSC3_TX_ADDR 0x60 #define FIFOC_PSC3_RX_SIZE 0x04 -#define FIFOC_PSC3_RX_ADDR 0x10 - -#define FIFOC_PSC4_TX_SIZE 0x0 -#define FIFOC_PSC4_TX_ADDR 0x0 -#define FIFOC_PSC4_RX_SIZE 0x0 -#define FIFOC_PSC4_RX_ADDR 0x0 - -#define FIFOC_PSC5_TX_SIZE 0x0 -#define FIFOC_PSC5_TX_ADDR 0x0 -#define FIFOC_PSC5_RX_SIZE 0x0 -#define FIFOC_PSC5_RX_ADDR 0x0 - -#define FIFOC_PSC6_TX_SIZE 0x0 -#define FIFOC_PSC6_TX_ADDR 0x0 -#define FIFOC_PSC6_RX_SIZE 0x0 -#define FIFOC_PSC6_RX_ADDR 0x0 - -#define FIFOC_PSC7_TX_SIZE 0x0 -#define FIFOC_PSC7_TX_ADDR 0x0 -#define FIFOC_PSC7_RX_SIZE 0x0 -#define FIFOC_PSC7_RX_ADDR 0x0 - -#define FIFOC_PSC8_TX_SIZE 0x0 -#define FIFOC_PSC8_TX_ADDR 0x0 -#define FIFOC_PSC8_RX_SIZE 0x0 -#define FIFOC_PSC8_RX_ADDR 0x0 - -#define FIFOC_PSC9_TX_SIZE 0x0 -#define FIFOC_PSC9_TX_ADDR 0x0 -#define FIFOC_PSC9_RX_SIZE 0x0 -#define FIFOC_PSC9_RX_ADDR 0x0 - -#define FIFOC_PSC10_TX_SIZE 0x0 -#define FIFOC_PSC10_TX_ADDR 0x0 -#define FIFOC_PSC10_RX_SIZE 0x0 -#define FIFOC_PSC10_RX_ADDR 0x0 - -#define FIFOC_PSC11_TX_SIZE 0x0 -#define FIFOC_PSC11_TX_ADDR 0x0 -#define FIFOC_PSC11_RX_SIZE 0x0 -#define FIFOC_PSC11_RX_ADDR 0x0 +#define FIFOC_PSC3_RX_ADDR 0x70 + +#define FIFOC_PSC4_TX_SIZE 0x04 +#define FIFOC_PSC4_TX_ADDR 0x80 +#define FIFOC_PSC4_RX_SIZE 0x04 +#define FIFOC_PSC4_RX_ADDR 0x90 + +#define FIFOC_PSC5_TX_SIZE 0x04 +#define FIFOC_PSC5_TX_ADDR 0xa0 +#define FIFOC_PSC5_RX_SIZE 0x04 +#define FIFOC_PSC5_RX_ADDR 0xb0 + +#define FIFOC_PSC6_TX_SIZE 0x04 +#define FIFOC_PSC6_TX_ADDR 0xc0 +#define FIFOC_PSC6_RX_SIZE 0x04 +#define FIFOC_PSC6_RX_ADDR 0xd0 + +#define FIFOC_PSC7_TX_SIZE 0x04 +#define FIFOC_PSC7_TX_ADDR 0xe0 +#define FIFOC_PSC7_RX_SIZE 0x04 +#define FIFOC_PSC7_RX_ADDR 0xf0 + +#define FIFOC_PSC8_TX_SIZE 0x04 +#define FIFOC_PSC8_TX_ADDR 0x100 +#define FIFOC_PSC8_RX_SIZE 0x04 +#define FIFOC_PSC8_RX_ADDR 0x110 + +#define FIFOC_PSC9_TX_SIZE 0x04 +#define FIFOC_PSC9_TX_ADDR 0x120 +#define FIFOC_PSC9_RX_SIZE 0x04 +#define FIFOC_PSC9_RX_ADDR 0x130 + +#define FIFOC_PSC10_TX_SIZE 0x04 +#define FIFOC_PSC10_TX_ADDR 0x140 +#define FIFOC_PSC10_RX_SIZE 0x04 +#define FIFOC_PSC10_RX_ADDR 0x150 + +#define FIFOC_PSC11_TX_SIZE 0x04 +#define FIFOC_PSC11_TX_ADDR 0x160 +#define FIFOC_PSC11_RX_SIZE 0x04 +#define FIFOC_PSC11_RX_ADDR 0x170 /* * SATA -- cgit v1.1