From 1f97987a513cf0a107b472b766e98ea94bedc8b0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 13 May 2011 01:16:07 -0500 Subject: powerpc/85xx: Add P2041 processor support The P2041 is similar to P2040, however has a 10G port and backside L2 Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 16 ++++++++++++++++ arch/powerpc/include/asm/processor.h | 2 ++ 2 files changed, 18 insertions(+) (limited to 'arch/powerpc/include') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d5c0aee..04ca989 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -273,6 +273,22 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#elif defined(CONFIG_PPC_P2041) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index c5b03b4..9c4651a 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1103,6 +1103,8 @@ #define SVR_P2020_E 0x80EA00 #define SVR_P2040 0x821000 #define SVR_P2040_E 0x821800 +#define SVR_P2041 0x821001 +#define SVR_P2041_E 0x821801 #define SVR_P3041 0x821103 #define SVR_P3041_E 0x821903 #define SVR_P4040 0x820100 -- cgit v1.1