From 1d0b59a9b049443397f484ad03b88c6314bc7ebb Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 27 Mar 2015 13:24:39 +0800 Subject: fsl/pci: Set CFG_READY for PCIe v3.0 and later Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout Signed-off-by: Roy Zang Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- arch/powerpc/include/asm/fsl_pci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/include') diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 5be718b..8bee8ca 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -19,6 +19,7 @@ #define FSL_PCI_PBFR 0x44 #define FSL_PCIE_CFG_RDY 0x4b0 +#define FSL_PCIE_V3_CFG_RDY 0x1 #define FSL_PROG_IF_AGENT 0x1 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ -- cgit v1.1