From 09bfd962bdc97359b916bfbf18a17e2a85396d65 Mon Sep 17 00:00:00 2001 From: Tony O'Brien Date: Fri, 2 Dec 2016 09:22:34 +1300 Subject: mpc85xx: pcie: Implement workaround for Erratum A007815 The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin Signed-off-by: Tony O'Brien [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun --- arch/powerpc/include/asm/fsl_pci.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/include/asm') diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 8bee8ca..cad341e 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -79,7 +79,9 @@ typedef struct ccsr_pci { u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ u32 pm_command; /* 0x02c - PCIE PM Command register */ - char res4[3016]; /* (- #xbf8 #x30)3016 */ + char res3[2188]; /* (0x8bc - 0x30 = 2188) */ + u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */ + char res4[824]; /* (0xbf8 - 0x8c0 = 824) */ u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ -- cgit v1.1