From 73b5396b25c52463aa71c782316e2d77a4b8d5ed Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 17 Aug 2012 08:22:37 +0000 Subject: powerpc/mpc8xxx: Add fine timing support for DDR3 When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/fsl_ddr_dimm_params.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/include/asm/fsl_ddr_dimm_params.h') diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h index 982b809..ffe4db8 100644 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h @@ -43,6 +43,7 @@ typedef struct dimm_params_s { /* DIMM timing parameters */ unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ + unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */ unsigned int tFAW_ps; /* four active window delay, only for ddr3 */ -- cgit v1.1